You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Some chip design companies openly state what their total transistor count is, so it's mostly bragging rights, and they often round to the nearest billion transistors for the largest SoC designs. In the early days of ASICs and FPGA designs, the companies would often cite Gate count, where a Gate...
Taylor, Texas reminds me of Aloha, Oregon, because Intel's first Oregon fab was placed in the tiny community of Aloha in 1974, for exactly the same reasons, tax incentives.
Several companies have announced stacked DRAM chips:
https://arxiv.org/abs/1809.08828
https://www.vikingtechnology.com/dram-modules/dram-memory-stacking/
https://www.slashgear.com/samsung-12-layer-3d-tsv-stacks-12-dram-chips-in-the-same-space-as-8-07594321/...
The average cost of a 180nm mask set is $100,000.00, however that same IC layout, but using 40nm masks will cost you $900,000.00. https://anysilicon.com/semiconductor-wafer-mask-costs/
The gate oxide is thinner for 40nm versus 180nm, which then effects the Vt of the transistor. So moving from...
Good point. The DRC rule deck grows by several X as you move down each smaller process node, so that's an interesting question to run a 180nm mask set on a 40nm process. I'm not sure that it would pass the DRC and ERC. Certainly the timing would change, because the smaller nodes have higher...
Each foundry process has a Process Design Kit (PDK) that is unique, and migrating from 180nm to a smaller process node requires engineering work like: functional simulation, logic synthesis using a new cell library, buying and integrating new 3rd party IP blocks, floor planning, standard cell...
Good eye, the handful of different die are there for testing purposes to make precise measurements about that wafer. On the test die they can more easily and efficiently measure IV curves, junction leakages, ESD breakdown voltages, P vs N channel conductance, resistivity of interconnect, etc.
Most foundries do not publish details about capacity per process node, because it’s confidential, although there are companies that will gladly sell you a report estimating these numbers.
Google is your friend:
https://epsnews.com/2021/02/10/5-fabs-own-54-of-global-semiconductor-capacity/
https://www.mordorintelligence.com/industry-reports/semiconductor-foundry-market
https://www.semi.org/en/news-media-press/semi-press-releases/global-200mm-fab-capacity-record-growth...
I was expecting a link to the Hejian web site, but found none in your article. There's a fab named Hejian that has an insecure website, but no mention of EDA software.
Quick Google search, 68020 was $487.00 at introduction in 1984, while the 68000 at the same time was priced down to just $15.00.
https://www.nytimes.com/1984/06/29/business/motorola-s-powerful-new-chip.html
Lam Research has a big footprint in Tualatin, they are located just a few blocks from my house, and Sherwood is turning much of its countryside into industrial and residential use. Growth is good for the semi business.
The mmWave support of 5G in the iPhone 13 could give you faster data rates, but the antenna needs to be within line of sight, even a tree branch or pane of glass will attenuate the signal, dropping your speeds.
https://www.tomsguide.com/news/iphone-13-could-get-a-major-5g-boost-heres-why
With the rapid expansion of semiconductor companies in China, the banks were too willing to extend credit in efforts to expand quicker. Let's see which Chinese venture picks up the pieces of Tsinghua Unigroup.
Paul, think about Pizza for a moment, why do they bake the entire pizza all at once, instead of 12 individual pieces? Answer: It’s faster, cheaper and offers greater quality control to fabricate an entire 200mm or 300mm wafer at one time, instead of 5,000 times.
