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Search results

  1. F

    EUV's productivity, and 157i

    The EUV mask lifetime has not been considered an issue, but TSMC reported they are trying to increase pellicle lifetime to match DUV. The EUV collector does have a lifetime though (power gradual drop), so its replacement was made easier on NXE 3400C.
  2. F

    AMD getting comfortable with Samsung 4nm?

    Some word on the internet in the last 24 hrs is that the 2200's inclusion of RDNA2 did not help the performance. If it pans out, then AMD would not be comfortable with Samsung 4nm.
  3. F

    EUV's productivity, and 157i

    From an SPIE paper on half-field overlay last year (1160907, Gabor et al., "Effect of high NA “half-field” printing on overlay error"), NXE 3400C throughput dropped 26% and NXT1980D dropped 36% by going to half-field.
  4. F

    AMD getting comfortable with Samsung 4nm?

    https://www.itpro.co.uk/hardware/361998/samsung-exynos-2200-official-amd-graphics Samsung's latest 4nm Exynos 2200 was co-designed with AMD. Is AMD using the same playbook as Qualcomm?
  5. F

    EUV's productivity, and 157i

    I almost overlooked a clarification that this would apply to the high-NA tools only due to their half-field. The two-exposure stitching is expected, since the older tools will continue to use as much of full-field as possible.
  6. F

    EUV's productivity, and 157i

    Two-photon has a side effect of ionization, since the sum of two photon energies is at least 10 eV for DUV. Probably dual-tone resist process is more what you are after.
  7. F

    EUV's productivity, and 157i

    157i did not give enough resolution boost beyond 193i, and required substantial materials changes all around. If there were an immersion fluid with n=1.7, the maximum NA could go to ~1.58, that would be the minimum resolution boost I think. However, the last published index values were not so...
  8. F

    Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

    My understanding was that 5/4nm already had some EUV multipatterning and 3nm even more. For something like SALELE for the metal layers, it would be 4 masks. The center-to-center for contacts could be less than 30 nm, requiring triple patterning. Perhaps for TSMC, the multipatterning barrier is...
  9. F

    Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

    It seems polarization is something they possibly want to control for high NA EUV: https://www.spiedigitallibrary.org/conference-proceedings-of-spie/11875/118750L/Simulation-study-on-EUV-multilayer-polarization-effects/10.1117/12.2599904.short?SSO=1 The normalized image log-slope (NILS), the key...
  10. F

    Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

    https://research.ibm.com/publications/effect-of-high-na-half-field-printing-on-overlay-error. The forced use of only half of the 26 mm x 33 mm on current tools led to 36% loss of productivity on the immersion tool and 26% loss of productivity on the current EUV tool.
  11. F

    iPhone 13 A15 Bionic SoC N5P details (from UnitedLex)

    So, some aspects gleaned from these pictures: 1. Fin layer (pitch ~52 nm) is done by SAQP, as there are 3 etch depths. 2. Gate layer uses a cut mask. 3. If M0 includes 28 nm pitch (not shown here), then it must be done by SALELE (4-mask multipatterning: LELE + 2 cuts). 4. 50 nm gate pitch and...
  12. F

    Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

    SoC dies generally fit into much less than 26 mm x 16.5 mm, but multiple dies are stuffed into the 26 mm x 33 mm to maximize productivity on the current tools. For example 2 x 3 dies, for a 9 mm x 11 mm Bionic SoC. This would require stitching in order for 26 x 16.5 mm to accommodate...
  13. F

    Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

    The maximum exposure field size on high NA is 26 mm x 16.5 mm, whereas on all the current platforms it's 26 mm x 33 mm. Most masks make use of most of the 26 mm x 33 mm area, so the high-NA needs to expose in two steps, with alignment (stitching) between the two exposures, like a double...
  14. F

    iPhone 13 A15 Bionic SoC N5P details (from UnitedLex)

    https://unitedlex.com/insights/revealing-the-hidden-innovations-within-the-a15-bionic-soc-found-in-the "Key layout and process features observed include tight diffusion termination (e.g., unique single diffusion break), contact over the active gate (COAG), optimized gate cut after replacement...
  15. F

    Different estimates of EUV tool allocation at TSMC and Samsung but same trends

    For Samsung, the same fab (being very large) can be used to do NAND, DRAM, Foundry independently.
  16. F

    Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

    MOL may be where it is suddenly needed as the center-to-center spacing goes below 40 nm.
  17. F

    Different estimates of EUV tool allocation at TSMC and Samsung but same trends

    Samsung's allocation between DRAM and foundry is still unknown; perhaps that is undercounted. TSMC's portion is still expected to be the majority, based on the number of fabs and layers where EUV is allocated. With the total known, and a reasonable range of estimates for TSMC, Samsung, and even...
  18. F

    Over 100 million wafers shipped with EUV multipatterning, >95% claimed by Lam Research

    Lam Research claims over 95% of the more than 100 million wafers processed with multipatterning (193i and EUV), particularly highlighting 5nm logic node. https://m.blog.naver.com/PostView.naver?blogId=jkhan012&logNo=222410469787&categoryNo=30&proxyReferer=https:%2F%2Fwww.linkedin.com%2F
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