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  1. Daniel Payne

    Aldec at SC19: Showcasing Multi-FPGA Partitioning Software for Multi-FPGA-based Algorithm Accelerators

    November 18-21, Denver Colorado Booth #228, Aldec Inc. We will showcase the recently introduced automatic FPGA partitioning feature of our popular HES-DVM™ tool, our fully automated and scalable hybrid verification environment for large SoC designs. Manual partitioning of designs with...
  2. Daniel Payne

    With proFPGA quad Intel® Stratix® 10 GX 10M System, PRO DESIGN Reaches a new Level in FPGA-based Prototyping

    Munich, 18 November 2019 - PRO DESIGN, leading supplier of high-speed ASIC and SoC verification platforms, today announced the launch of its innovative high-capacity proFPGA quad Stratix® 10 GX 10M system. It is the next generation of its successful, modular, scalable and most compact...
  3. Daniel Payne

    IP Security Assurance Standard - White paper

    Authors Brent Sherman, Intel Corporation Mike Borza, Synopsys James Pangburn, Cadence Design Systems, Inc. Ambar Sarkar, NVIDIA Corporation Wen Chen, NXP Semiconductors Anders Nordstrom, Synopsys Kathy Herring Hayashi, Qualcomm Michael Munsey, Methodics John Hallman, OneSpin Solutions Alric...
  4. Daniel Payne

    1.2 Trillion transistor chip? Yes - Cerebras

    Yeah, the largest wafer-scale chip on the planet award goes to Cerebras at 1.2 trillion transistors. Aimed at speeding up ML operations, this is outrageously interesting. In theory as a die size increases the yield should approach zero, so how did Cerebras and TSMC team up to create this mammoth...
  5. Daniel Payne

    ISQED'20 - Call for Contributions, deadline September 14

    21st ISQED - March 25-26, 2020 - Santa Clara Convention Center, California About the Conference A pioneer and leading interdisciplinary conference, the 21st International Symposium on Quality Electronic Design (ISQED2020) accepts and promotes original and unpublished papers related to the topics...
  6. Daniel Payne

    ISQED 2020 - Call for papers

    21st ISQED - March 2020, Santa Clara Convention Center, California Submission Deadline: Sept. 14th, 2019 About the Conference A pioneer and leading interdisciplinary conference, the 21st International Symposium on Quality Electronic Design (ISQED2020) accepts and promotes original and...
  7. Daniel Payne

    DVCon U.S. 2020 Announces Call for Extended Abstracts, Panels, Tutorials and Short Workshop Proposals

    Submission site for extended abstracts is open; other submission sites to open August 6, 2019 Louisville, CO—July 9, 2019 —The 2020 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announces its call for extended...
  8. Daniel Payne

    Asia South Pacific DAC - Call for papers

    Call for Papers ASP-DAC 2020 http://www.aspdac.com January 13-16, 2020 China National Convention Center (CNCC), Beijing, China Aims of the Conference: ASP-DAC 2020 is the 25th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most...
  9. Daniel Payne

    ISQED 2020 - Call for Papers

    Call for Papers 21st ISQED - March 2020, Santa Clara Convention Center, California Submission Deadline: Sept. 14th, 2019 About the Conference A pioneer and leading interdisciplinary conference, the 21st International Symposium on Quality Electronic Design (ISQED2020) accepts and promotes...
  10. Daniel Payne

    DAC 2019 - Marie Pistilli Award Recipient

    R. Iris Bahar to Receive Marie R. Pistilli Women in Engineering Achievement Award Brown University professor honored for outstanding technical contributions in energy efficient and reliable electronic systems, nanoelectronics, and nanotechnology LOUISVILLE, Colo. – April 24, 2019 –– Iris...
  11. Daniel Payne

    DVCon Europe 2019 to be held on 29th and 30th October in Munich

    Scope broadened to include embedded software. Calls for papers, tutorials and panels issued. Munich, Germany – March 21st, 2019 - The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced the call for papers, tutorials...
  12. Daniel Payne

    2nd MOS-AK India Conference, Feb 25-27, 2019 - Summary

    2019 IEEE International Conference on Modeling of Systems Circuits and Devices Organised by Joint Chapter of CAS /ED Societies, IEEE Hyderabad Section 2nd MOS-AK India Conference (IEEE Conference #45395) Venue: IIT Hyderabad February 25-27, 2019 The MOS-AK Compact Modeling Association, a...
  13. Daniel Payne

    LSCC - stock jumps on Q4 sales and revenue guidance

    Lattice Semi a turnaround story? Shares at highest point in 15 years - oregonlive.com Lattice is the third, but smaller competitor to Xilinx and Intel in the FPGA market.
  14. Daniel Payne

    Another automation approach for analog schematic porting

    Thalia-DA unveils AMALIA analog schematic porting capability Automation accelerates analog design reuse projects by up to 50% CWMBRAN, UK 7 February 2019 - Thalia Design Automation today introduces advanced analog schematic porting capabilities within its AMALIA analog design automation tool...
  15. Daniel Payne

    Who is the CEO Emeritus at Mentor?

    Walden Rhines is officially now the CEO Emeritus at Mentor, as Tony Hemmelgarn takes the CEO title. Executive Team - Mentor Graphics I would typically expect a press release issued about a change in CEO title. Siemens has done a fine job acquiring Mentor and letting the product divisions...
  16. Daniel Payne

    11th annual MOS-AK Workshop Summary, Silicon Valley, December 5, 2018

    Modeling of Systems and Parameter Extraction Working Group Summary of the 11th International MOS-AK Workshop Silvaco Inc. Headquarters, Silicon Valley, December 5, 2018 The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its 11th MOS-AK...
  17. Daniel Payne

    How safe is it to work in a fab?

    I live in Oregon and wonder about how safe it is for Intel workers in the fab, or even neighbors living nearby. Emergency crews back at Intel for another possible toxic exposure incident | OregonLive.com Intel: ‘no hazardous materials release’ in incident that sent 15 to the hospital |...
  18. Daniel Payne

    Intento Design offers analog circuit sizing tool through CMP

    INTENTO DESIGN and CMP Make Evaluation of ID-Xplore™ Tool Available through CMP Agreement gives CMP users a remote or on site access to for evaluation of Intento Design ID-Xplore™ Analog Design Exploration Tool Grenoble, France - November 21st, 2018 - INTENTO DESIGN and...
  19. Daniel Payne

    16th MOS-AK Workshop at ESSDERC/ESSCIRC

    MOS-AK Workshop Dresden 2018 Dresden, Sept. 3, 2018 The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 16th MOS-AK Workshop in the timeframe of ESSDERC/ESSCIRC. The event was hosted on September 3rd, 2018, by the TU Dresden in...
  20. Daniel Payne

    Drones used for assassination attempt

    I've always wondered why it took so long for the bad guys to use technology like drones and robots for political assassinations or even bank robberies. From the report in Venezuela it sounds like the security team was able to thwart the path of the drones and steer them away from the intended...
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