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Search results

  1. F

    Root scientific causes of TSMC's leadership / Intel and Samsung's failure,based%20on%20the%20abovementioned%20regulations.
  2. F

    The computer chip industry has a dirty climate secret

    Water levels and power consumption are also critical in Taiwan.
  3. F

    TSM has taken Collaboration to an Art Form

    It may be argued, though, some partners may inevitably be favored over others, like Apple over Qualcomm.
  4. F

    Root scientific causes of TSMC's leadership / Intel and Samsung's failure

    Technologically, the multipatterning choices may also have made a difference. At 7nm TSMC had a 4-mask process (SALELE) which included some self-alignment, while Samsung 8nm had 4 masks without self-alignment (LELELELE), and Intel 10nm reportedly had over 4 masks, even with self-alignment (SAQP).
  5. F

    Will China master 14nm and what is their future in semi production?

    14nm was set up with Qualcomm/IMEC/Huawei collaboration initially.
  6. F

    Difference between processing-in-memory and computing-in-memory

    It's supposed to be implementing logic operations (like AND, OR) or matrix-vector operations with memory cells instead of logic gates. But actually 3D NAND and DRAM makes use of external specialized computing units (known as controllers, often using FinFET logic), so there is computing or...
  7. F

    Micron's rushed sale of Lehi fab

    This particular fab was a remnant of Micron's collaboration with Intel, formerly IMFlash, which included development of 3D NAND (based on floating gate) and 3D XPoint. In the end, both development collaborations ended, at different times. This would amount to somewhat of a waste of...
  8. F

    Micron's rushed sale of Lehi fab

    Reading this, I got the impression that Micron tried to sell off its Lehi fab very quickly, and TI didn't even take all of it: The 40% in "tools and assets" still yet to be disposed.
  9. F

    Google's Tensor-based mobile SoC ?
  10. F

    TSMC to reduce EUV layers for 3nm as part of CIP

    From the abstract: We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt...
  11. F

    TSMC to reduce EUV layers for 3nm as part of CIP

    It's 10nm+ compared to the first version. The comparison was only the layer list and the MIM difference was mentioned. They did not show reliability comparison actually but presented the slew of reliability tests.
  12. F

    Gaussian random field EUV stochastic models - 2021 SPIE paper by Siemens Digital Industries (formerly Mentor Graphics EDA)

    Mentor Graphics was acquired by Siemens in 2017. EDA is now part of Siemens Digital Industries. This year, they published a paper for SPIE EUV virtual conference, "Gaussian Random Field EUV stochastic models, their generalizations and lithographically meaningful stochastic metrics."...
  13. F

    TSMC to reduce EUV layers for 3nm as part of CIP

    Last year at IRPS, Intel revealed after all the delay they didn't change anything for their 10nm process at that time (being used for Tiger Lake), except adding an upper metal layer, and making the MIM capacitor denser...
  14. F

    TSMC to reduce EUV layers for 3nm as part of CIP

    That's right, the limited supply of EUV tools on schedule would be their most pressing issue. It would drive more efficient multipatterning.
  15. F

    TSMC to reduce EUV layers for 3nm as part of CIP As part of a Continuous Improvement Plan (CIP), TSMC will target reducing EUV machine use. From 25 EUV layers for 3nm down to 20, for example. Tool cost is one issue. Another is the heavy utility consumption (electric power, water), which is...
  16. F

    Intel boxed out Apple and AMD?

    Nikkei reports Apple should be first but Intel may have more volume:
  17. F

    Samsung to begin using EUV pellicles in 2023 They have their work cut out for them.