You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
Thanks for the quick response Daniel!
For A2, what about the effect on the dynamic power of the system? would one expect somewhat of a constant margin difference in power usage?
So I have two questions, and these are kinda hefty so I apologize for that
Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement...