Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?members/vibeguy.35652/recent-content
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Recent content by vibeguy

  1. V

    Equivalent ASIC and FPGA designs

    Thanks for the quick response Daniel! For A2, what about the effect on the dynamic power of the system? would one expect somewhat of a constant margin difference in power usage?
  2. V

    Equivalent ASIC and FPGA designs

    So I have two questions, and these are kinda hefty so I apologize for that Q1: If we use reprogrammable FPGAs to test implementations of IP, can an ASIC be designed and manufactured that looks almost identical; and vice versa: if we have an ASIC with known layout, is it possible to implement...
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