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The following comments from C.C. today contradict this:
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C. C. Wei
Okay. Great. Hi. This is C. C. Wei. Let me answer the second part of the question first. [Indiscernible] costs definitely it is higher than N5. That is because of technical complexity and...
Dylan got roasted on the /r/hardware Reddit comment thread for this Anandtech article for claiming "no CPU gains," and rightfully so. Most people probably didn't read beyond the headline of his article so they didn't understand the context which was that the IPC gains are minimal due to a delay...
I think that's a given. The power+cost advantage of integrating it into the SoC is the main reason to design your own modem, otherwise it's probably better to just pay the extra $10-15 per unit to Qualcomm or even Samsung if cost saving at inferior performance is what they're after.
I look...
Yes but paying royalties to Qualcomm is cheaper than buying its modems. Just like the cost+performance advantage of licensing ARM's instruction set and designing your own SoC compared to buy one from another vendor.
Usually when Apple decides to take something previously outsourced and do it in-house there is a major power or performance advantage (custom CPU + GPU + Power Management) but on the modem side this is less likely. If Intel couldn't match Qualcomm before, I doubt they can under Apple. However...
The revised schedule+++ :)
All that probably means is the datacenter ramp up volumes will be a month or two ahead of most recent expectations. AFAIK they only only specified a broad 2020H1 launch, 2020H2 HVM.
That's great news. A common concern brought up at semiengineering.com is that fewer and fewer customers can afford to design for the latest node. But now it seems design cost will stay flat for the next ~5 years as EUV replaces more multi-patterned layers.
Is it only quad-patterning DUV that...
Ah ok I see, so design complexity doesn't scale linearly with the number of layers. Going from a quad-patterned layer to single EUV won't just be a 75% reduction, but more because of the inter-mask dependencies (I'm guessing alignment is the biggest challenge here) of multi-patterning being...
Daniel, could you explain how the design rules are affected by mask/layer count? In Scotten Jones' article "TSMC and Samsung 5nm Comparison," the tables show TSMC's total layer count dropping from 75 at 7nm to 59 at 5nm, and I presume the numbers going from Intel's 10nm to 7nm node to be in the...
"We expect our customers' end products using N7+ will be in the market in high volume this quarter. We expect strong demand to continue into next year." -Dr. C. C. Wei
TSMC said in the Jan 2019 call that 7+ would generate less than NT $1B, or ~$32 million USD in 2019 (EDIT nvm this obviously...
