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Recent content by SPQR54

  1. S

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    Doubt that it is always the case, otherwise EUV would not sell. For some layers it is clearly an economic advantage somehow. Excellent point. That was the oversimplification that fails the moment we deals with stochasticity. At that point we move from classical to quantum optics and the...
  2. S

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    Agreed, but definitely the number and cost of overall processing steps went down with EUV introduction at 7 and 5nm. Will that still be true is part of the question I think. Not so much into litho as at one time, but I think that the debate, for those that can have access to EUV, will be...
  3. S

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    As for any other process, is not a matter of "best technology" but of "what does it well enough at the right cost". Then the issues are "well enough" and "right cost" that may differ among players. EUV certainly does it well enough (even "better" arguably) and cheaper than multi-patterning at 7...
  4. S

    AI/ML Needed for Unbiased Solutions

    Bias can be in the programming and can be in the training data set. The problem is exacerbated in Gen AI as it uses vastly larger and diffentiated datasets than those used in machine learning, and so are even more difficult to sceen and control. That is why they put some hard rules on the...
  5. S

    The Bleeding Edge of Semiconductors: A Tale of Three Companies || Peter Zeihan

    There was actually only one 157nm tool I remember delivered: the ASML/SVG/PE Micrascan to imec. In the meantime ASML was working on the immersion 193 prototype and, as soon as the first images printed with it came out, 157nm was dead. Intel invested a lot in programs in 157nm over the years and...
  6. S

    The Bleeding Edge of Semiconductors: A Tale of Three Companies || Peter Zeihan

    157nm, good all times. Intel declaring at SPIE the needs of tons of CaF2 crystals for the hundreds of steppers they were going to buy just 3 weeks before ditching everything. Schott ever so glad of keeping with the plan of waiting until the first full demonstration of the stepper before boosting...
  7. S

    Will AMD become serious competition to Nvidia?

    Competing agains NVidia on AI now is like competing with Xilinx in the past for FPGA. So much is tied in the software that either you are fully compatible or you do not get market share for your hardware. So you are always at a disadvantage.
  8. S

    AMAT's patterning advantage over ASML?

    A patent is worth only how much you are ready to spend to enforce it. Is AMAT going to sue any of their customers using it without paying licenses ? I doubt it. And ASML is not going to loose any business over this I think, as it applies only to a restricted set of patterns.
  9. S

    World's biggest chipmaker TSMC to open second Japan factory with backing from Sony, Toyota

    Seen from this side of the pond the TSMC fabs in US and Japan are quite different and not comparable proposition. In US the claim is for an advanced fab fully TSMC for 5nm and below with a tinge of "national interest". In Japan it is a joint venture with local co-investors (mostly customers) for...
  10. S

    Semiconductor R&D spending by company

    When you compare you have to take into account that for IDMs you have both process and product development spending, fabless only product and foundries only process.
  11. S

    China hits back in the chip war, imposing export curbs on crucial raw materials

    Gallium is present in bauxite at 10g to 150g per metric ton. By comparison Al is about 250kg per metric ton of bauxite. The real problem is then the extraction process from the byproducts of Al mining. Very dirty process with a relatively low yield. Some are looking into it as it can be a way...
  12. S

    Primary contributors to wafer fab cycle time (which process steps?)

    A well run fab has no bottlenecks in front of litho, it is build to have uniform throughput and you do not buy one tool more or less than necessary to maximise overall use. Underinvesting and creating bottlnecks is very quickly anti-economic and you do not have more or less depo/etch/clean...
  13. S

    Samsung Planning Semiconductor Plant in Europe?

    STM is very much Franco-Italian. Minority blocking stakes are still in equal measure with the two Governments. And, depending on the market segment one focus in, it can be perceived more French or more Italian. A lot of "lost in translation" issues with the piece that makes a big confusion of...
  14. S

    Primary contributors to wafer fab cycle time (which process steps?)

    300mm wafers move from tool to tool in standardised FOUPs (Front Opening Unified Pod) usually of 25 wafers (may be 13). Production is really a batch process even if some tools are single wafer processing. So indeed you have time spent to serialise the process and then parallelise the transport...
  15. S

    Intel's Conflict of Interest? Can it overcome TSMC

    AMD to GF all over again, but without Mubadala money ? Who is going to pay for IFS while it gets customers, Intel? If so why spin off and why customers should believe they will be treated on an equal footing. If not, where is the money to keep going and stay in the development race until it...
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