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What gap? I have done a ton of modeling of Intel over the years and confirmed/correlated results to published and private numbers. If a fab has a capacity of 100K wpm and is running 50K that is called utilization and it varies for all fabs, it is fully factored into my modeling. And while Intel...
He said Intel has ~200k wpm starts, if that is correct their Fab utilization isn't good because they have a lot more capacity than that and they are adding more all the time.
With respect to wafer cost the only yield that matters at all is line yield in the fab and everyone is in the high ninety percentiles. If you talk about die cost then die yield comes in and that is where Intel struggled at 14nm, and 10nm. Reportedly i4/i3 die yields are pretty good.
I have actual numbers for 18A pitches, I can't publish them but I can say that 18A high density cell transistors per mm2 are slightly higher than TSMC 5nm but lower than TSMC 3nm. To even catch up to TSMC 2nm, Intel 14A would need a big density jump and this is during a time when density jumps...
When comparing wafer costs there are two components, one is process cost and the other is fab cost. Intel 10/7 processes are very expensive processes compared to TSMC 7nm even if run in the same fab. Intel fabs are generally in higher cost countries plus Intel has some Intel specific cost...
This is an interesting slide:
- Performance/watt - I agree with their ratings.
- Density - I don't agree with, TSMC is way ahead of 18A, maybe Intel could catch up at 14A but it would take a huge jump.
- Wafer cost - surprisingly, I was just looking at wafer cost and through 18A I think they are...
"The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple."
When 3nm was still in...
"As many on this forum are aware, maximum theoretical logic density is often calculated by taking the (M2 pitch) X (M2 tracks for a four transistor NAND gate) X (CPP). From there we try to use correction factors to account any boundary scaling (for example Scotten using 10% area reduction from...
The connection is from the side just like for the Power Via.
"As a side note why do you think that AMAT and intel have a different definition of what BPR is from IMEC? The engineers from both firms are far from dummies, and they both contribute to IMEC. The difference in opinion and definition...
My understanding is the process is:
1) Transistor formation and front side interconnect formation on the front of the device wafer.
2) A carrier wafer is bonded to the front of the device wafer.
3) The wafer pair is flipped over and most of the device wafer is removed from the back.
4) Through...
We are running 3nm now with 2nm (20A) due 2024 to 2026 depending on version and company. Samsung has talked about 1.4nm in 2027 based on a Horizontal Nanosheet with more sheets. My projections are 10A around 2029 based on a CFET, with 7A, 5A, and 3A CFETs to follow. Finally around 2037 we get...
Aluminum for what, are you talking Buried Power Rail (BPR) because Al won't survive the temperatures or meet the electromigration requirements. If you are talking Backside Power Delivery that is copper and it is done at the end of the process flow.
