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Compilers are focused procedural languages, not on Verilog(which is a kind of dataflow language at best). Verilog did not appeal to designers, but because Verilog could be simulated it appealed to management and Verilog was forced on designers. A major problem has always been that the "tool...
Why does Apple bother with Arm, when they could just create their own ISA optimized for their goals and products? Isn't that what Apple's M1 chip is?
"It's a bummer that Intel doesn't do something more innovative". They don't want to kill the X86 goose that is laying all those golden eggs...
Yes, CISC means Complex Instruction Set Computer. Probably any computer that does anything more than Add, Complement, Load, and Store.
Or maybe means does not do multiply or divide. Of course it is expected to do out of order execution and branch prediction because that complexity has so much...
https://www.dropbox.com/sh/snfn59cok9hn21u/AAB4ZufD8kGqHcinFFuvgj4ja?dl=0
I am a novice, but think this is a link to something that may be useful.
Meanwhile I will try to attach my .cs code that uses the SyntaxWalker
Hi! I am working on teaching an FPGA to play this game. It is a bit like using a JIT to compile CIL/intermediate code.
The C#/Roslyn Compiler API will compile C expressions and produce the operators and operands in sequence to evaluate using a simple stack. Also it will emit the statements...
Part of it is that RISC and CISC are just buzz words. The 801 architecture was an attempt to use the micro-programmed control of System360/370 as an ISA.
Well, that didn't fly so well mainly because the micro program control array had to run at clock speed and did not fetch "instructions"...
So he could also "see" into the future because the CISC/RISC concepts did not exist at that time.
It so happens that I began working in computer systems in 1957, installing, trouble shooting, modifying, and getting into the inside of computers to see exactly how things worked or didn't work...
I wish there was a way to get past "opinions" with some realistic analysis. Multi-core was sold as "pie in the sky" -- like double the performance for free. But no one could do the necessary parallel programming. Out of order execution and cache were invented for matrix inversion, but mainly...
So what can we expect for the next 10 years?
I think that RISC-V is doing the same thing again (load/store) and expecting different results(which is a symptom of insanity) just because it is "free". It is based on assembler level programming, but practically no one programs in assembler...
And it is a graceful way to move away from the multi-core, super scalar out of order execution overly complex x86 into heterogeneous computing just as Apple is doing. BUT Microsoft Research "Where's the Beef?" found that FPGAs were the way to go because there is no instruction fetch from...
@Q1:
"My thought is that the fixed logic blocks within an FPGA and routing through the switch matrices mean they will never be the same but I wonder if there's a way to get something close."
No, not even close. There are 2 HDLs, VHDL and SystemVerilog/Verilog totally different. FPGA logic is...
Q1: If by "looks the same" means the physical layout, then absolutely not. FPGAs are LUTs, flip-flops, embedded memory, and built in functional blocks. ASICs are built from the ground up, totally custom with none of the above.
If "looks the same" means that the functions are identical then...
Did I just see the words "path delay"? This is just another example of digging the hole deeper when it is already too deep.
It simply does not make sense to be designing at such a low level.
Micro-programming and LUT approaches are far better than synthesizing everything from cells. It is...
I was designing, debugging, trouble-shooting computers and control units 20 years before Verilog was invented. There was no timing analysis, and programming was done in assembler. ANFSQ7 and IBMSystem360 including IO devices, for reference.
First was the data-flow including registers, buses...
