More than a decade of extensive industry experience in Functional verification of ASIC, SOC, MFR and IPs.
- Expert in preparing project proposals, planning and managing execution of ASIC and IP verification programs spanning RTL verification, gate level simulation & vector generation.
- Experience in working with Systems, Architecture, Design, RF, Validation & marketing teams. All projects executed across multi-sites in different time zones.
- Successfully built multiple teams with varied experience. Hired ~100 verification engineers.
- Strong experience in mentoring engineers across all levels. Have developed focused training programs.
- Exposure to working with different customers from understanding the requirements to providing complete solution (product and design services) directly contributing to revenues of the organization.
- Worked with marketing teams for business development and branding for the organization.
- Lead verification efforts by contributing towards effective methodology development, architecting efficient test benches, planning, scheduling and tracking.
- Worked on multiple programs (ASIC/SOC/MFR/IP) from architecture to tape out. Lead & have been part of the teams delivering First Si success.
- Expert in test bench component coding, writing unit/system level test plans and test cases, test bench infrastructure development (scripting simulation/regression setup), coverage (code coverage & functional coverage), power aware verification and power estimation.
- Proficient with EDA tools and excellent analytical, programming skills (HVL, HDL & Scripting).
- Experience in new EDA tool evaluations and setup.
- Author of 3 patent pending technologies & published multiple papers & articles.
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