Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?members/f-c-chong.21790/recent-content
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Recent content by F C Chong

  1. F

    China, IP, Tech, Taiwan, Politics Forever Changed, Opportunity

    TSMC was made an offer it couldn't refuse. However, the money is in the leading fab, where Apple, AMD etc are willing to pay a premium to gain a competitive edge for their products. A 5nm fab coming on line in 2024 is not the leading edge. It is a good start and secures a local supply for the...
  2. F

    1.2 Trillion transistor chip? Yes - Cerebras

    That was what I thought in the beginning when I saw WSI, but in the assembly drawing, recticle dies were in the drawing to manage the TCE mismatch between silicon and PCB. There are multiple problems need to be solved at the same time, the presentation does not contain enough information to show...
  3. F

    1.2 Trillion transistor chip? Yes - Cerebras

    I am not sure this fits in the traditional definition of monolithic wafer scale integration (WSI). However, if one uses wafer scale interconnect to provide inter die connection, then this can be loosely called wafer scale integration. The following proposal could work: 1. The recticle dies are...
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