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Recent content by Eric Bouche

  1. E

    Fab manufacturing questions

    Could not resist adding few words: 1 - Lithography is always made to be the wafer fab capacity bottleneck because it is the most expensive - It just means that when rounding up and down, lithography may see more rounding down and other areas rounding up 2 - As soon as the fab starts running, the...
  2. E

    TSMC to reduce EUV layers for 3nm as part of CIP

    There has always been a large difference in lithography between tsmc foundry and Intel microprocessor. The number of EUV layers depends of the design rules.
  3. E

    Do wafer costs decline as a node matures?

    To go back to the original question: of course they do! And it is quite dramatic. The key reasons are yield improvements, productivity improvements and depreciation of the tools
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