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Recent content by Daniel Nenni

  1. Daniel Nenni

    Enflame leverages Mentor’s Tessent DFT solutions for innovative cloud AI chip targeting neural network training

    · Mentor’s Tessent design-for-test (DFT) technology helped Enflame dramatically speed design cycles and lower test costs · Enflame achieved AI chip bring-up in seven days with Tessent software Mentor, a Siemens business, today announced that leading artificial intelligence (AI)...
  2. Daniel Nenni

    Pulse Secure and Nozomi Networks Team Up to Deliver Secure IIoT Connectivity

    SAN JOSE, Calif., Dec. 12, 2019 (GLOBE NEWSWIRE) -- Today Pulse Secure, the leading provider of software defined Secure Access solutions and Nozomi Networks, the leader in OT and IoT security, announced an integration that extends the zero trust protection provided by the Pulse Secure Access...
  3. Daniel Nenni

    PLDA’s INSPECTOR diagnostic and debug tool for PCIe 4.0 technology passed all Gold and Interoperability tests for systems with CEM slots

    PLDA, the industry leader in PCI Express® (PCIe®) technology and high-speed interconnect solutions, today announced that their PCIe 4.0 INSPECTOR™ diagnostic and debug platform passed all Gold and Interoperability tests for the PCIe 4.0 root port systems performed by the PCI-SIG® during their...
  4. Daniel Nenni

    2020 VLSI-TSA and VLSI-DAT Symposia will Kick Off on April 20

    Focusing on 5G, AI, Robotics, Quantum Computing and Bioelectronic Medicine HSINCHU, Taiwan, Dec. 13, 2019 (GLOBE NEWSWIRE) -- AI, 5G, Robotics, Quantum Computing and Bioelectronic Medicine are bringing about changes in the semiconductor industry. To address these trends, the Industrial...
  5. Daniel Nenni

    Cobham Releases RISC-V Processor IP Core

    The NOEL- V processor will be RV64GC compliant, a 64-bit architecture, and is written in VHDL. The processor will be fully integrated with Cobham’s GRLIB VHDL IP core library. 11 DEC 2019 San Jose, California – Cobham Gaisler announced today at the RISC-V Summit in San Jose, California, that it...
  6. Daniel Nenni

    Hex Five Announces General Availability of MultiZone™ Security for Linux – The First Commercial Enclave for RISC-V processors

    DATE:DECEMBER 10, 2019 Enabling safety-critical applications in mixed-criticality systems where Linux and realtime come together in a single chip San Jose, California, Dec. 10, 2019, RISC-V Summit — Hardware consolidation requirements in automotive, aerospace & defense, and industrial...
  7. Daniel Nenni

    Antmicro and zGlue release rapid turnaround chiplet-based GEM ASIC

    SAN JOSE, CA – December 10th, 2019 – Today, edge AI technology expert company and RISC-V leader Antmicro, and zGlue, a Silicon Valley startup democratizing the procedure of custom chip creation using their innovative chiplet technology, have announced the release of Antmicro’s first...
  8. Daniel Nenni

    CODASIP TEAMS UP WITH WESTERN DIGITAL TO SUPPORT ADOPTION OF OPEN-SOURCE PROCESSORS

    Munich, Germany – December 10th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, announced today that it has joined forces with Western Digital Corp. (NASDAQ: WDC) to become the preferred provider of hardware implementation packages and expert technical...
  9. Daniel Nenni

    Tensorflow Lite in Zephyr on LiteX/VexRiscv

    While much of the focus for the recent developments in AI has been on cloud-centric implementations, there are many use cases where AI algorithms have to be run on small and resource constrained devices. Google’s TensorFlow Lite, a smaller brother of one of the world’s most popular Machine...
  10. Daniel Nenni

    Curated List of RISC-V Education Materials Now Available

    The RISC-V Foundation is committed to helping developers and members grow and expand their use of the RISC-V ISA, and access to training materials and educational materials is a fundamental part of empowering the ecosystem and driving innovation. That is why today the RISC-V Foundation is...
  11. Daniel Nenni

    RISC-V Foundation Seeks Technology Leader

    DATE:DECEMBER 9, 2019 The RISC-V Foundation is looking for a technology leader who can foster a successful technical ecosystem with deep member and community engagement and meaningful progress across technical imperatives in growing adoption of the RISC-V architecture. The technology leader...
  12. Daniel Nenni

    Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis

    Developed with SiFive to Address RISC-V System Integration Validation; Generates High-Impact SoC Verification Test Suite with Minimal Manual Effort SAN JOSE, CALIF. –– December 10, 2019 –– Breker Verification Systems, the leading provider of Test Suite Synthesis tools based on the Portable...
  13. Daniel Nenni

    SiFive Announces New Technologies for Mission-Critical and AI Markets

    New SiFive Apex cores for mission-critical markets and SiFive Intelligence cores for vector processing workloads create a comprehensive IP portfolio for high-growth markets SAN MATEO, Calif. - Dec 10, 2019 - SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon...
  14. Daniel Nenni

    Lattice and SiFive Announce Collaboration to Allow Lattice FPGA Developers Easy Access to RISC-V Processors

    Scalable Processor Core IP Running on Low Power, Small Form Factor FPGAs Could Power Millions of Smart Devices at the Edge SAN MATEO, Calif. – Dec. 11th, 2019 – SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, and Lattice Semiconductor Corporation...
  15. Daniel Nenni

    CEA-LETI AND PARTNERS DEMONSTRATE POTENTIALLY SCALABLE READOUT SYSTEM FOR LARGE ARRAYS OF QUANTUM DOTS

    Results Hold promise for Fast, Accurate Single-Shot Readout ‘Of Foundry-Compatible Si MOS Spin Qubits’ SAN FRANCISCO – Dec. 11, 2019 – Leti, a technology research institute of CEA Tech, and its research partners have demonstrated a potentially scalable readout technique that could be fast...
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