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TSMC Announces Updates for TSMC Arizona

The problem would be Samsung and Intel undercutting them. With the slowdown even if Intel and Samsung can’t catch up, the older stuff will be more competitive than you would otherwise guess given its age. Obviously this won’t sink TSMC. However it could and likely will hurt their margins.

Yes, that's where TSMC's bet to make 5nm, and 7nm on substantial US subsidies comes. The CHIPS act reads as if it was specifically worded for one company only.

By denying the depreciating <10nm space to nearest followers using subsidy, TSMC leaves scorched earth behind itself in mature nodes.

And Samsung is subsidising its logic with its memory, so Intel will be squeezed in between a rock, and a hard place: other contenders for mature nodes, and Samsung.

And this is all when AMD is eating their vital consumer products market share, and profit.
 
What do you even mean by this? 10nm is in about as good of a state as you could ask given it's inherent cost structure disadvantages. Per intel, intel 4 is already hitting yields for HVM (and Oregon has plenty of EUV tools for the task). Hopefully the design side is getting their execution on track.

Is Intel 10 is comparable on yields, and throughput to TSM?
 
Is Intel 10 is comparable on yields, and throughput to TSM?
Throughput is literally impossible. No matter what improvements intel makes that node will always be a relatively expensive and slow to produce. All the proof you need for this can be summed up with one plot:
1670369448634.png

Yields are obviously fine. Intel is spiting out big-died products at high clock speeds. Additionally they are spiting out low ASP parts. This is not something you would do until you are reasonably far down the yield learning curve. About two years ago intel said that 10nm wafer starts passed 14nm wafer starts. Finally all of intel's HVM fabs make 10nm now besides Ireland. Any claims that 10nm still has yield or performance issues are easily proven false by publicly available information.
 
... I think Intel needs a customer-first attitude that I've never seen or heard about to be successful as a foundry.

I asked my buddy who worked at Intel using the TSMC 28nm process if IFS will succeed against TSMC.
He asked "Did you try contacting IFS for their PDK"
I said "Yes, a year ago, but I still never received it"
He said "You have your answer"

IFS is receives US taxpayer funding. My company is composed of 100% US citizens. Intel doesn't respond to us, but TSMC/Imec gets back to us immediately. Mr. Blue, I see your point. TSMC, welcome to Arizona!
 
I asked my buddy who worked at Intel using the TSMC 28nm process if IFS will succeed against TSMC.
He asked "Did you try contacting IFS for their PDK"
I said "Yes, a year ago, but I still never received it"
He said "You have your answer"

IFS is receives US taxpayer funding. My company is composed of 100% US citizens. Intel doesn't respond to us, but TSMC/Imec gets back to us immediately. Mr. Blue, I see your point. TSMC, welcome to Arizona!
I wonder if they would be more forthcoming these days? As everyone and their mother knows, if intel wants to succeed in this space they should/need to be getting better (at being customer centric). It still seems odd they would decline; maybe the pdks weren't ready for the every-man at that time? Cliff did they give you any reasons, or did they just not get back to you.
 
I wonder too.

My situation was too complicated for them because they like to put companies and people into boxes, so I am told. We aren't the "every man". We are an EDA/IP/ASIC company. We don't need their whole PDK. Just their DRM and OA files, We make our own stdcells, liberty files, pcell, I/O, etc.

We cannot get the PDK as an EDA company because they will want to evaluate our tools. That ain't gonna happen. They have their own tools group, and I don't trust them.

Our ASIC customers are only interested in TSMC (I think I know why). We need to PDK to create the libraries, blocks (IP), and automation prior to getting ASIC customers. The VP referred me to the IP group

The IP group looked at our website and said that we are an EDA company, not an IP company, which is kinda true because we use our IP only for ASIC customers, since we don't want to be in the commodity business (note my Radio Shack comments). Apparently, I failed the litmus test.

Linked in messages were ignored.

It's OK. We will stick to TSMC. Our automation with TSMC vs Intel/Tower. I love the smell of napalm in the morning.

On a very related topic, they don't care about their own internal groups embarrassing their own company by using TSMC? This is a disgrace IMO. A total lack of pride. Perhaps Mr. Gunslinger will change the culture. I hope he does.
 
Paul, please explain this a bit more in detail. "They had to use off-the shelf IP, since they didn't want to spend their Core X design team time dealing with grunt work reinveting the bicycle for an insignificant SKU. And the only decent IP, and capacity was at TSMC. The rest is history."

Any digital IP is in the form of RTL. That is not foundry specific.

Analog can be retargeted. It takes more time, but very doable. Hopefully they saved their TBs with the DUTs. Their Fujitsu/Freescale cellphone group they acquired were top notch doing 28nm. I am told there was a major culture clash. IP didn't come out of that?

How can this enormous company not have the basic building blocks?

What is a SKU?
 
I wonder too.

My situation was too complicated for them because they like to put companies and people into boxes, so I am told. We aren't the "every man". We are an EDA/IP/ASIC company. We don't need their whole PDK. Just their DRM and OA files, We make our own stdcells, liberty files, pcell, I/O, etc.

We cannot get the PDK as an EDA company because they will want to evaluate our tools. That ain't gonna happen. They have their own tools group, and I don't trust them.

Our ASIC customers are only interested in TSMC (I think I know why). We need to PDK to create the libraries, blocks (IP), and automation prior to getting ASIC customers. The VP referred me to the IP group

The IP group looked at our website and said that we are an EDA company, not an IP company, which is kinda true because we use our IP only for ASIC customers, since we don't want to be in the commodity business (note my Radio Shack comments). Apparently, I failed the litmus test.

Linked in messages were ignored.

It's OK. We will stick to TSMC. Our automation with TSMC vs Intel/Tower. I love the smell of napalm in the morning.

On a very related topic, they don't care about their own internal groups embarrassing their own company by using TSMC? This is a disgrace IMO. A total lack of pride. Perhaps Mr. Gunslinger will change the culture. I hope he does.
Yikes that’s a less then ideal experience. I do wonder how one person can really hope to change the culture of such a large company though. It is hard to believe that everything is all of a sudden going to go right for Intel as soon as the Pat regime started. Intel 4 is going up against N3 right? I guess we’ll see how that goes. Everything I’ve heard indicates N3E will be a very successful node so Intel will really need to execute Intel 4 flawlessly to keep up. I do wonder if it will matter though, because if AMD continues to take market share in the many years it will take to get IFS to anything that contributes meaningfully to Intel’s financial health, how will Intel pay to play the foundry game if they are already stumbling financially?
 
Remove dead wood. Remove non techies. Remove marketing. Remove middle management. 50% of the work is done by the square root of the number of the number of people. Well known formula.

Management by walking around.
No preschedules meetings.
Meetings should be 2 people. Sometimes 3.
 
Great PR for TSMC:

"We work with TSMC to manufacture the chips that help power our products all over the world. And we look forward to expanding this work in the years to come as TSMC forms new and deeper roots in America," said Apple CEO Tim Cook.
Advertisement · Scroll to continue

"AMD expects to be a big customer, of both fabs and we're committed to working closely with TSMC and the entire ecosystem," said AMD CEO Lisa Su.

Against the background of the new factory draped with an American flag and a banner reading "A Future Made in America Phoenix, AZ," top executives led by TSMC founder Morris Chang, 91, toasted the factory opening with sparkling wine. Nearly 600 engineers hired in Arizona have been sent to Taiwan for training, Chang said. "This is a very good sign that my dream of 25 years ago will now be fulfilled," he said of his wish to build fabs in the United States.

 
Yikes that’s a less then ideal experience. I do wonder how one person can really hope to change the culture of such a large company though. It is hard to believe that everything is all of a sudden going to go right for Intel as soon as the Pat regime started. Intel 4 is going up against N3 right? I guess we’ll see how that goes. Everything I’ve heard indicates N3E will be a very successful node so Intel will really need to execute Intel 4 flawlessly to keep up. I do wonder if it will matter though, because if AMD continues to take market share in the many years it will take to get IFS to anything that contributes meaningfully to Intel’s financial health, how will Intel pay to play the foundry game if they are already stumbling financially?
Worth pointing out is that i4 and N3E succeeding are not mutually exclusive. I4 is only for cpu core dies, while N3E is a general foundry node (and doesn't come out until when i3 is scheduled to). Due to the tight capacity that intel will likely face until at least 2024, I can't imagine that intel was planning for i3 foundry to really be "a thing" before 18A enters HVM. My intuition and the public announcements say this will be intel's the first real foray into foundry. Another thing to chew on is that it takes years to design a chip, therefor 18A is about as soon as someone could even try an IFS node. Proof of this can be seen with MediaTek's announcement that their i16 stuff was going into HVM at Ireland in 2024. In the meantime if i4/3 allow intel to have an equal or superior node to AMD this will help stem their bleeding and be a massive win for the fabs. Success with these nodes also builds trust and confidence that IFS can and will meet it's roadmap.
 
Mr. Ng, is there a cheat sheet I can look at to decipher through the jargon? 18A: DUV or EUV or combo. How many patterned layers? What cut layers? Are contact layers routable? What gate length? Same for the others.

I assume i16 similar to TSMC 16nm? Don't give me the numbers. Just whatever was published.

My interest is on Intel as a second source for ASICs. There is no way they will be my primary. It has nothing to do with the foundry technology nor the foundry recurring costs. It is everything else.

Thank you
 
Mr. Ng, is there a cheat sheet I can look at to decipher through the jargon? 18A: DUV or EUV or combo. How many patterned layers? What cut layers? Are contact layers routable? What gate length? Same for the others.

I assume i16 similar to TSMC 16nm? Don't give me the numbers. Just whatever was published.

My interest is on Intel as a second source for ASICs. There is no way they will be my primary. It has nothing to do with the foundry technology nor the foundry recurring costs. It is everything else.

Thank you
Define routable M0? Depending on what that means intel's recent paper might answer that question. As for the rest I haven't seen any papers floating around that give the answer to that. All we can do is wait I suppose. Next year we will probably get the full story for 20A, and that should be mostly the same as 18A.
 
No clue why Sanjay Mehrotra is going there but sure. More logic is only good for the memory folks.

Here is what Sanjay Mehrotra said in the TSMC's press release:

"TSMC's Fab 21 expansion is an important step toward securing U.S. supply of advanced semiconductor technology. TSMC is a long-standing Micron partner, and their commitment to high-quality, innovative logic foundry services helps enable Micron to deliver industry-leading memory and storage solutions."

Sanjay Mehrotra, President and CEO of Micron

 
Here is what Sanjay Mehrotra said in the TSMC's press release:

"TSMC's Fab 21 expansion is an important step toward securing U.S. supply of advanced semiconductor technology. TSMC is a long-standing Micron partner, and their commitment to high-quality, innovative logic foundry services helps enable Micron to deliver industry-leading memory and storage solutions."

Sanjay Mehrotra, President and CEO of Micron

How exactly does the micron-TSMC partnership work? Forgive my ignorance but what does each offer each other. How much crossover is there in IP from memory to logic? I definitely know far less about the memory side so my apologies if this is an inane question.
 
How exactly does the micron-TSMC partnership work? Forgive my ignorance but what does each offer each other. How much crossover is there in IP from memory to logic? I definitely know far less about the memory side so my apologies if this is an inane question.
Make sure their stacked DRAM solutions work well with TSMC's packaging solutions.
 
How exactly does the micron-TSMC partnership work? Forgive my ignorance but what does each offer each other. How much crossover is there in IP from memory to logic? I definitely know far less about the memory side so my apologies if this is an inane question.

1. Tighter memory and logic chips packaging/integration.

2. In memory computing.

3. Close collobration to beat their common enemy, Samsung.
 
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Will IFS offer 2.5D (logic chip + HBM) solution to ASIC customers? Is their advanced packaging only for Goliaths?
 
Will IFS offer 2.5D (logic chip + HBM) solution to ASIC customers? Is their advanced packaging only for Goliaths?
That would be a question for ifs folks. I would assume they aren’t picky since they do packaging for Graviton 3. And my understanding is that the hyperscaler custom silicon stuff is low volume (for now).
 
That would be a question for ifs folks. I would assume they aren’t picky since they do packaging for Graviton 3. And my understanding is that the hyperscaler custom silicon stuff is low volume (for now).
Interesting that Intel does packaging for Graviton. I was under the impression Graviton is fabbed at TSMC. So they fab at TSMC and then package at Intel? Interesting
 
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