Guys, back to the basics please.
Device engineers knew all along that Dennard scaling was ending, it was designers that wouldn't listen.
Dennard formula, based on the physics of the basic CMOS structure, was indicating clearly what was being gained by reducing the size of the devices. Its beauty is that the physical factors limiting the scaling were always there to be seen: 1) below a certain thickness the gate insulator gets conductive (partially solved by moving from silicon dioxide to Hf based oxides but still a wall is there); 2) there is a limit on the necessary increasing doping when reducing transistor size leading to issues in channel control; 3) the unit power dissipated per unit area is a constant.
To compensate other phenomena in the device, strain was introduced. FinFET also relaxed the condition that increasing the width of the transistor to increase the current was impacting the area of the device. These are all related to the physics of the device and its materials. At that point the factors indicated by robbi165 started to play.
The solution overall was to move to metal gates/high-k gate structures, confined structures like FinFET and SOI and now nanowires/nanosheets. That was the point, somewhere between 65nm and 45nm, where true Dennard scaling ended. The structures since thern are not anymore the basic CMOS and so the performance gain factor stopped to be constant and started reducing from the 100% at each node to the current 20-25%.
Then you have the processing challenges, but they have nothing to do with Dennard scaling issues. For example for a while there seemed to be a barrier at 1 micron, well before the limits of Dennard scaling. The topography of the structures were conflicting with the depth of focus of the litho but the introduction of chemiomechanical polishing (CMP) saved the day.
Someone of the oldies around this forum should get together and write the in depth device and processing history complementing Daniel book