I laugh out loud when Gartner or IBIS tell us what wafers cost or how much it costs to tape out a leading edge design. The estimates are always high to get the chicken little sky is falling thing going so they can sell reports.
For fabless companies you can put them in three buckets: Fabless chip companies (QCOM, BCRM, MVL, etc...) Fabless ASIC companies (Alchip, Sondrel, OPenFive, etc...), and fabless systems companies (Apple, Google, Tesla, etc...).
ASIC companies do design on the cheap since they are very margin constrained.
Fabless companies also do design on the cheap but not as cheap as the ASIC companies.
System companies blow out the design cost curve and spend huge amounts of money in comparison.
For an SoC, let's say it's $100M for ASIC, $200M for Fabless, and $300M for Systems. I guess you can take the average and say it costs $200M for a 7nm design but would that sell reports? No, but if you add them together and say $600M that will sell reports!
The question I have is how many chances does a Chicken Little or the Boy Who Cried Wolf get before they tarred and feathered?