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What going on with the obvious drop in "Others" - you would have assumed that these numbers would only increase over the years ? Was that Intel disposing of some early EUV machines ? Or someone else ?
What going on with the obvious drop in "Others" - you would have assumed that these numbers would only increase over the years ? Was that Intel disposing of some early EUV machines ? Or someone else ?
What going on with the obvious drop in "Others" - you would have assumed that these numbers would only increase over the years ? Was that Intel disposing of some early EUV machines ? Or someone else ?
These are tool production per year, not aggregate # of EUV tools. So "Others" going down from '18 -> '19 or '19 -> 20 depending on which chart, just signifies that of what ASML was able to produce that year, the majority went to T / S. For Samsung, also not entirely clear if that volume of tools is just for logic or also logic + DRAM. TSMC and Samsung both started mass production of technologies (N7+ and S7LPP) in 2019, but the demands for N5 in terms of # of EUV layers is higher than for S5, and TSMC now produces both N7+ and N6 nodes, concurrent to N5 at different factories, all of which consume many EUV layers and thus tools. Samsung OTOH only produced maybe 2-3 designs on S7LPP before introducing S5LPE, and these are effectively the same node / same factory, just different std cell library used in the latter.
Samsung's allocation between DRAM and foundry is still unknown; perhaps that is undercounted. TSMC's portion is still expected to be the majority, based on the number of fabs and layers where EUV is allocated. With the total known, and a reasonable range of estimates for TSMC, Samsung, and even Intel, very few are left. SK Hynix was mentioned to have two by end of this year: https://english.etnews.com/20210629200001
Samsung's new five-layer EUV process enables the industry’s highest DRAM bit density, enhancing productivity by approximately 20% Based on the latest DDR5 standard, Samsung’s 14nm DRAM will be ideal for handling ever-growing AI and 5G workloads
news.samsung.com
This was announced Oct 2021, “begun mass producing”. Samsung Foundry fabs also produce DRAM.
Samsung's new five-layer EUV process enables the industry’s highest DRAM bit density, enhancing productivity by approximately 20% Based on the latest DDR5 standard, Samsung’s 14nm DRAM will be ideal for handling ever-growing AI and 5G workloads
news.samsung.com
This was announced Oct 2021, “begun mass producing”. Samsung Foundry fabs also produce DRAM.
This ebook examines the various lithography techniques currently in use in consumer electronics, they key players in lithography R&D and development through their patents, and China’s response to EUV restrictions.
www.techinsights.com
Samsung 5nm (5LPE) analyzed by TechInsights to have 8 EUV layers: CT, M0-3,V0-2
TSMC would have extra mask exposures for cuts as well as some double patterning (just for 5nm). So they could easily demand at least 2x however many Samsung uses.
Samsung could be using double patterning as well for 4nm, so their mask exposures would also go up.
For 150000 wpm, 3 fab phases, this amounts to <70 wph (yield, throughput, utilization). So it does look like low yield at advertised throughput.