BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//SemiWiki - ECPv6.16.3//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://semiwiki.com
X-WR-CALDESC:Events for SemiWiki
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20260308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20261101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20270314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20271107T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260506T080000
DTEND;TZID=America/Los_Angeles:20260506T090000
DTSTAMP:20260614T075945
CREATED:20260420T073725Z
LAST-MODIFIED:20260420T073725Z
UID:368582-1778054400-1778058000@semiwiki.com
SUMMARY:Webinar: All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die
DESCRIPTION:Abstract\n\nDive into the future of Bluetooth audio with Ceva and Dolphin Semiconductor’s breakthrough 12nm Smart Edge AIoT SoC solution. \nThis webinar shows how advanced wireless connectivity\, integrated AI processing\, and premium audio technologies and power management come together to deliver superior performance\, lower power\, and faster time to market. \nLearn how a combined Ceva and Dolphin Semiconductor’s solution turnkey platform enables low power and high performance next generation features: Bluetooth High Data Throughput\, Channel Sounding\, spatial audio\, voice commands\, sensor fusion\, and more. \nIdeal for cutting edge earbuds\, headsets\, smartwatches\, and smart glasses. \nDon’t miss this opportunity to enhance your next audio product with industry leading innovation. \nWhat you will learn in this session:\n\nMap and understand audio peripheral product challenges\, particularly for TWS/OTC\nEvaluate the pros and cons of existing design level solutions\nCeva’s and Dolphin Semiconductor’s solution for overcoming TWS/OTC device challenges\n\n\nTarget Audience\nChip architects & SoC designers\, audio and DSP engineers\, embedded software engineers\, and product managers for hearables & wearables \n\nSpeakers\n\n\n\n\n\n\n\nFranz Dugand \nSr. Director\, Product Marketing\, Ceva \n\n\n\n\n\n\nEtienne Faucher \nProduct line Portfolio Manager – Audio\, Dolphin Semiconductor \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-all-in-one-bluetooth-audio-a-complete-solution-on-a-tsmc-12nm-single-die/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/04/CEVA-Dolphin-Weninar-SemiWiki_400x400-v2_260419.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260506T100000
DTEND;TZID=America/Los_Angeles:20260506T110000
DTSTAMP:20260614T075945
CREATED:20260424T093814Z
LAST-MODIFIED:20260424T093859Z
UID:368769-1778061600-1778065200@semiwiki.com
SUMMARY:Webinar: RedHawk-SC: From EMIR Signoff to IR-Aware Design Closure
DESCRIPTION:As power integrity challenges increase with advanced nodes and multi-die architectures\, EMIR analysis must evolve beyond traditional signoff. In this Synopsys webinar\, we will show how RedHawk-SC is expanding its capabilities not only to enhance EMIR analysis\, but also to enable IR-aware Static Timing Analysis (IR-STA) and IR-driven ECO (IR-ECO) flows. \nJoin us to learn how tighter integration between power integrity and timing analysis\, across both single-die and multi-die designs\, helps engineers better understand IR-drop impact\, accelerate debug\, and achieve faster\, more reliable design closure. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-redhawk-sc-from-emir-signoff-to-ir-aware-design-closure/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/04/Synopsys-RedHawk-sc-webinar-1200x1200-1.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260508T100000
DTEND;TZID=America/Los_Angeles:20260508T110000
DTSTAMP:20260614T075945
CREATED:20260414T062754Z
LAST-MODIFIED:20260414T062754Z
UID:368403-1778234400-1778238000@semiwiki.com
SUMMARY:Webinar: How Data Rates Doubled\, and Where Validation Reaches Its Limit
DESCRIPTION:Data rates have doubled\, but validation methods have not kept pace. As PCIe\, DDR\, and multi-terabit optical interconnects evolve\, engineers are encountering signal integrity challenges much earlier in the design process. \nJoin Niels Fache\, Senior Vice President and General Manager of Design Engineering Software at Keysight\, to explore where validation becomes more challenging as speeds increase\, and how engineering teams are adapting. You’ll learn how simulation\, architecture modeling\, and high-fidelity measurement help validate designs before silicon exists and reduce downstream risk. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-data-rates-doubled-and-where-validation-reaches-its-limit/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260515T100000
DTEND;TZID=America/Los_Angeles:20260515T110000
DTSTAMP:20260614T075945
CREATED:20260414T062904Z
LAST-MODIFIED:20260414T062904Z
UID:368405-1778839200-1778842800@semiwiki.com
SUMMARY:Webinar: How Frequency Ranges Expanded\, and Why Measurement Fidelity Became Critical
DESCRIPTION:As systems move into higher frequencies and wider bandwidths\, small measurement errors can lead to costly design decisions. Engineers working in wireless\, radar\, satellite\, and optical domains must now validate signals that push existing tools to their limits. \nJoin Jun Chie\, Vice President of Product Management at Keysight\, to explore where measurement fidelity begins to break down\, and how engineers are adapting. You’ll see how next-generation instrumentation helps improve signal accuracy\, reduce uncertainty\, and increase confidence in design decisions. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-frequency-ranges-expanded-and-why-measurement-fidelity-became-critical/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260519T090000
DTEND;TZID=America/Los_Angeles:20260519T100000
DTSTAMP:20260614T075945
CREATED:20260505T081403Z
LAST-MODIFIED:20260505T081403Z
UID:369064-1779181200-1779184800@semiwiki.com
SUMMARY:Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
DESCRIPTION:Featured Speaker: \n\nVictoria Kolesov\, Principal Engineer\, Intel\n\nIn this Synopsys webinar\, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and 3D layout verification in both passive and active interposer designs. The session highlights how increasing accuracy requirements have shaped 3D construction practices\, standards\, and collateral\, enabling consistent\, correct‑by‑construction signoff across process nodes\, TSVs\, and complex die‑to‑die interconnects. \nWhat you’ll learn: \n\nHow Intel approaches 3DIC construction for disaggregated designs\nKey requirements for static timing and layout signoff in 3DIC flows\nDifferences between passive and active interposer signoff considerations\nHow accuracy requirements influence 3D construction methodologies\nBest practices for achieving correct‑by‑construction 3DIC signoff\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVictoria Kolesov \nPrincipal Engineer\, Intel \nVictoria Kolesov joined Intel in 2001 and has held a variety of responsibilities including RTL development\, design completion\, and design automation. Her current focus is interconnect implementation and 3D design integration. Victoria obtained her MS in Computer Science from St.Petersburg Technical University\, Russia. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intel-from-construction-to-signoff-3dic-methodology-for-disaggregated-designs/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/05/victoria-kolesov-headshotqlt82ampts1777480285645ampresponsiveampfitconstrainampdproff.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260522T100000
DTEND;TZID=America/Los_Angeles:20260522T110000
DTSTAMP:20260614T075945
CREATED:20260414T063003Z
LAST-MODIFIED:20260414T063003Z
UID:368408-1779444000-1779447600@semiwiki.com
SUMMARY:Webinar: How System Scale Expanded\, and Why Network Traffic Validation Became Essential
DESCRIPTION:AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions\, not just in isolated tests. \nJoin Ram Periakaruppan\, vice president and general manager of network applications and security at Keysight\, to learn how large-scale traffic emulation reveals congestion\, latency issues\, and performance limits. You’ll see how to validate AI infrastructure under real workloads and ensure it performs reliably at scale. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-system-scale-expanded-and-why-network-traffic-validation-became-essential/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260528T080000
DTEND;TZID=America/Los_Angeles:20260528T090000
DTSTAMP:20260614T075945
CREATED:20260512T083619Z
LAST-MODIFIED:20260512T083619Z
UID:369183-1779955200-1779958800@semiwiki.com
SUMMARY:Webinar - From Acoustic Wave Filters to RF Front-End Modules: Patent Trends Shaping 5G/6G Connectivity
DESCRIPTION:As 5G and future 6G networks increase RF front-end complexity\, acoustic wave filters and RF front-end modules are facing growing demands for higher frequency operation\, wider bandwidth\, lower losses\, better thermal stability and deeper integration. Based on KnowMade’s latest analyses of RF Acoustic Wave Filters and RF Front-End Modules & Components\, this seminar will explore how patent activity up to 2026 reflects the evolution of competition from discrete acoustic devices to integrated RF front-end architectures. Key topics include SAW\, BAW\, FBAR\, TFSAW\, XBAR\, temperature-compensated filters\, multiplexers\, packaging and module-level integration. \nParticular attention will be given to the evolution of IP leadership between established Japanese and US RF players and fast-rising Chinese entities. While Murata remains the dominant IP leader in RF acoustic wave filters\, companies such as Qualcomm\, Skyworks\, Qorvo\, Taiyo Yuden\, Huawei\, MEMSonics\, Newsonic\, Sanan IC\, RadRock\, ROFS Microsystem and others are shaping a more multipolar competitive landscape. The webinar will also highlight recent patenting activity in 2025 across RF FE segments\, including PA\, LNA\, SAW\, BAW\, RF switches\, tuners\, multiplexers and packaging. \nBy combining patent landscape analysis with annual monitoring insights\, this session will provide a strategic view of where RF front-end innovation is heading\, which players are strengthening their IP positions\, and how emerging technologies may shape the next phase of 5G-Advanced and 6G connectivity. \nPlease log in 15 minutes before the indicated time so as not to miss the beginning of the webinar. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-from-acoustic-wave-filters-to-rf-front-end-modules-patent-trends-shaping-5g-6g-connectivity/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-12-013543.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260528T100000
DTEND;TZID=America/Los_Angeles:20260528T110000
DTSTAMP:20260614T075945
CREATED:20260425T081459Z
LAST-MODIFIED:20260425T081459Z
UID:368795-1779962400-1779966000@semiwiki.com
SUMMARY:Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI
DESCRIPTION:*Company Email Required for Registration* \nFull-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms\, logs\, and across hundreds of thousands of lines of code. \nIn this webinar\, we will demonstrate how the Bronco AI Debug Agent performs root-cause analysis (RCA) on real production issues in under 15 minutes\, with a 70% success rate on customer regressions. You will see the agent operate end-to-end on a representative full-chip SoC\, from a failing regression to an annotated root cause\, while interoperating with customer’s standard commercial EDA flows. \nWhat we will cover: \n– Live demonstration of the Debug Agent on a full-chip SoC regression failure\n– How the agent navigates massive codebases\, logs\, and waveforms to isolate failure mechanisms\n– Deployment patterns at large public chip companies and as well as fast-moving startups\n– How bring-your-own-model and on-prem deployment keep customer IP inside your environment.\n– How Bronco gets better without ever training on customer data. \nWho should attend: \n– DV engineers and managers responsible for regression triage and production debug\n– SoC verification leads evaluating AI-native tooling for their flows\n– VPs of Engineering and Silicon leaders tracking DV cycle time and engineering ROI\n– Security and infrastructure owners assessing on-prem AI deployment for chip design \nSpeaker: \nDavid Zhi LuoZhang\, Co-Founder and CEO of Bronco AI\, will walk through the live demonstration on a real design and take questions how customers deploy\, evaluate\, and scale Bronco within their silicon projects. David works tightly with customers to deploy Bronco and coordinates between the core R&D\, customer\, and industry-relations teams at Bronco. \n*This webinar is in partnership with SemiWiki and Bronco AI* \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-cutting-full-chip-soc-debug-from-days-to-minutes-with-ai/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-25-011434.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260529T100000
DTEND;TZID=America/Los_Angeles:20260529T110000
DTSTAMP:20260614T075945
CREATED:20260414T063056Z
LAST-MODIFIED:20260414T063056Z
UID:368410-1780048800-1780052400@semiwiki.com
SUMMARY:Webinar: How Manufacturing Complexity Increased\, and Why Validation Had to Evolve
DESCRIPTION:As semiconductor complexity increases and board designs become denser\, manufacturing teams face tighter tolerances\, reduced test access\, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address. \nJoin Jason Kary\, Senior Vice President and President of Keysight’s Electronic Industrial Solutions Group\, to explore how manufacturing validation is evolving. You’ll learn how wafer-level and in-circuit test strategies improve coverage\, detect defects earlier\, and enable consistent\, high-volume production at scale without compromising quality. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-manufacturing-complexity-increased-and-why-validation-had-to-evolve/
LOCATION:Online
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