BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//SemiWiki - ECPv6.15.18//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://semiwiki.com
X-WR-CALDESC:Events for SemiWiki
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20260308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20261101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20270314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20271107T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260303T100000
DTEND;TZID=America/Los_Angeles:20260303T110000
DTSTAMP:20260411T224324
CREATED:20260210T181806Z
LAST-MODIFIED:20260212T175607Z
UID:366569-1772532000-1772535600@semiwiki.com
SUMMARY:Webinar: Intelligent Networks: Power\, Reliability & Maintenance in Telecom
DESCRIPTION:About\nAs global connectivity demands surge\, network infrastructure hardware is under unprecedented pressure to deliver higher performance\, lower latency\, and greater energy efficiency\, while remaining cost-effective and reliable. This challenge is compounded with the explosive growth of AI applications\, emerging 5G and 6G architectures\, virtualization and open interfaces\, adding further strain on legacy systems and supply chains that were never built for this pace of evolution. As reliability remains the primary KPI\, providers must shift from a reactive replacement model to a predictive maintenance model. \nJoin our panel of industry experts as they explore the multidimensional challenges of designing\, deploying\, and maintaining network infrastructure in this new era\, focusing on: \n• Power efficiency and thermal optimization across silicon\, networks\, and data centers\n• Proactive monitoring and predictive analytics\n• Requirements for HW and SW co design in next generation architectures\n• Balancing sustainability goals with total cost of ownership \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intelligent-networks-power-reliability-maintenance-in-telecom/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/1770674564867.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260311T080000
DTEND;TZID=America/Los_Angeles:20260311T090000
DTSTAMP:20260411T224324
CREATED:20260309T224642Z
LAST-MODIFIED:20260309T224642Z
UID:367313-1773216000-1773219600@semiwiki.com
SUMMARY:Webinar: Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP
DESCRIPTION:Wednesday\, March 11 – 8:00 AM Pacific \nDesign and verification teams consistently tell us that compute subsystems require software bring up much earlier than ever before. They need UEFI and Linux to run in simulation\, they need protocol accuracy from day one\, and they need a predictable path to signoff while integration risks rise every quarter. This struggle has become a shared industry reality. \nIn this session we present a scalable methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs\, with a shift-left in simulation and signoff using Avery Protocol VIP\, CSS VIP\, Software Aware VIP\, Arm Fast Models and QEMU models. \nThis methodology helps teams reduce integration risks\, shorten turnaround time\, and gain system level confidence long before moving to emulation or prototypes. If you are a design or verification engineer\, a firmware engineer or if you manage a team building next generation compute platforms\, this is an event that will strengthen your technical path forward. \nWhat You Will Learn:  \n\nSoftware Aware Verification IP and applications.\nBlock level / Subsystem Compliance Testing with Software Aware VIP.\nFull CSS HW/FW/SW bring up and UEFI Bootup.\nAdvanced debug of Hardware/Firmware/Software.\n\nWho Should Attend: \n\nVerification Managers and Directors.\nDesign and Verification Engineers.\nFirmware/Software Engineers.\n\nProducts Covered: \n\nAvery Verification IP.\nSoftware Aware VIP.\nSystem VIP (CSS).\n\nSpeakers:\n\n\n\n\n\nLuis E. Rodriguez \nTechnical Product Manager\, Siemens EDA \n\n\n\nLuis E. Rodriguez is a Technical Product Manager at Siemens EDA. \nLuis has 17+ years of experience in SoC and IP functional verification\, specializing in developing market‑leading Verification IP. \nHe has contributed to protocol workgroups including PCIe\, CCIX\, Gen‑Z\, and CXL\, where he helped define CXL 2.0 compliance testing. \nAt Siemens\, he focuses on partnerships and solutions for Software‑Aware VIP and supports cross‑functional integration of Verification IP with Siemens EDA tools and emerging Agentic AI. \nHe holds his master’s degree in computer science from National Taiwan University. \n\n\n\n\n\n\nAmit Tanwar \nSoftware Architect\, Siemens EDA \n\n\n\nAmit Tanwar is a Software Architect at Siemens EDA. \nAmit has 18 years of experience in PCI Express and UVM/SystemVerilog‑based Verification IP development. \nHe specializes in building high‑performance\, scalable\, and software‑aware VIP solutions\, and has contributed to multiple generations of advanced verification architectures across the semiconductor industry. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-shift-left-compute-subsystem-rtl-sign-off-with-software-aware-vip/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-09-154557.png
END:VEVENT
END:VCALENDAR