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DTSTART;TZID=America/Los_Angeles:20260113T080000
DTEND;TZID=America/Los_Angeles:20260113T170000
DTSTAMP:20260412T014625
CREATED:20251211T211727Z
LAST-MODIFIED:20251211T211727Z
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SUMMARY:Terascale AI\, 1.6T and Beyond Seminar: Santa Clara
DESCRIPTION:About this event\nNext-generation AI systems are pushing electrical\, optical\, and packaging technologies to their limits. Join Keysight experts as they share insights on validating 224G / 448G SerDes\, preparing for emerging IEEE 1.6T optical standards\, advancing silicon photonics\, and strengthening die-to-die interconnects for chiplet-based architectures. \nThis is your chance to learn directly from the engineers shaping the future of high-speed I / O design — all in one room. Sign up today. \n\n\n\n\n\n\n\nWho should attend this event?\nThis seminar is ideal for engineers working on next-generation connectivity and AI infrastructure\, including optical design\, silicon photonics\, high-speed digital\, validation\, test & measurement\, signal integrity\, compliance\, and chiplet / die-to-die interconnect architectures. \n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/terascale-ai-1-6t-and-beyond-seminar-santa-clara/
LOCATION:Santa Clara\, CA\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-11-131707.png
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DTSTART;TZID=America/Los_Angeles:20260113T090000
DTEND;TZID=America/Los_Angeles:20260113T100000
DTSTAMP:20260412T014625
CREATED:20251211T205651Z
LAST-MODIFIED:20251211T205651Z
UID:364602-1768294800-1768298400@semiwiki.com
SUMMARY:Webinar: PQShield with Microchip’s PolarFire® SoC FPGAs: Securing the Future of Embedded Systems in the Post-Quantum Era
DESCRIPTION:As the quantum threat moves from theory to reality\, attacks put all long-lifecycle designs at risk. In this early PQC era\, simply implementing the new NIST algorithms isn’t enough. Implementations will evolve\, and new physical attacks like side-channel analysis present a major threat to the security of these complex new algorithms. \nThe solution requires both crypto-agility and deep hardware security. This webinar showcases PQShield’s hardware/software co-design as a side-channel secure PQC solution for Microchip’s PolarFire ® Series of products. \n\n\n\nSpeaker: \n\n\n\n\n\nSebastien Riou \nFellow\, Product Security Architecture\, PQShield \n\n\n\nSebastien has 15+ years experience in the semiconductor industry\, focusing on achieving “banking grade security” on resource constrained ICs such as smart cards and mobile secure elements. Formerly of Tiempo-Secure\, he helped create the world first integrated secure element IP achieving CC EAL5+ certification. He is the author of a semi-finalist algorithm at the Lightweight Cryptography NIST Standardisation process. He holds Master degrees in Computer Science and Cognitive Science from INPG. \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-pqshield-with-microchips-polarfire-soc-fpgas-securing-the-future-of-embedded-systems-in-the-post-quantum-era/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-11-125606.png
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DTSTART;TZID=America/Los_Angeles:20260114T080000
DTEND;TZID=America/Los_Angeles:20260114T090000
DTSTAMP:20260412T014625
CREATED:20260107T111051Z
LAST-MODIFIED:20260107T111051Z
UID:365416-1768377600-1768381200@semiwiki.com
SUMMARY:Webinar: Physics-Based Foundations for Power Supply Design
DESCRIPTION:Overview:\n\nThis webinar provides engineers with a science-driven framework for power supply design\, rooted in the physics of electromagnetic energy flow. Inspired by Ralph Morrison’s pioneering approach\, the session begins with core principles of energy behavior\, then explores how current\, fields\, and waves interact inside real circuits. \nAttendees will gain practical insight into:\n\nHow electromagnetic interactions shape power integrity\nWhy grounding\, return paths\, inductance\, capacitance\, and loop control are critical to reliable design\nHow to apply field-based thinking to achieve predictable\, first-time success\nHow to apply field-based thinking to achieve predictable\, first-time success\n\nBy the end of the session\, participants will walk away with a clear\, concise\, and powerful engineering perspective—one that replaces “black magic” with confidence and clarity in designing robust power systems. \n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-physics-based-foundations-for-power-supply-design/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-030839.png
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DTSTART;TZID=America/Los_Angeles:20260114T100000
DTEND;TZID=America/Los_Angeles:20260114T110000
DTSTAMP:20260412T014626
CREATED:20251219T204133Z
LAST-MODIFIED:20251219T204814Z
UID:364917-1768384800-1768388400@semiwiki.com
SUMMARY:Webinar: Advances in ATPG: From Power and Timing Awareness to Intelligent Pattern Search with AI
DESCRIPTION:Date: Jan 14\, 2026 | 10:00 AM PST \n\n\nFeatured Speakers: \n\nSrikanth Venkat Raman\, Product Management Director\, Synopsys\nKhader Abdel-Hafez\, Scientist\, Synopsys\nTheo Toulas\, R&D Principal Engineer\, Synopsys\nBruce Xue\, Staff Engineer\, Synopsys\n\nAs System-on-Chip (SoC) designs become increasingly complex\, meeting test quality and cost goals requires advances in automatic test pattern generation (ATPG). Synopsys TestMAX™ ATPG is Synopsys’ state-of-the-art pattern generation solution. In this Synopsys webinar\, we will showcase the latest ATPG advancements\, from power- and timing-aware capabilities to leveraging AI for reducing test costs. Discover how you can meet the power constraints of your SoC tests with power-efficient ATPG patterns. Learn how timing-aware ATPG can enhance test quality. We will also explore Synopsys TSO.ai™ (Test Space Optimization AI)\, the industry’s first autonomous AI application for semiconductor testing\, designed to minimize test cost and time-to-market for today’s complex designs. \nWhy You Should Attend: \n\nDiscover best practices for limiting power consumption during shift and capture operations.\nSee practical demonstrations of how you manage test power at the top-level of your SoC through a top-level budget and partition-level budgets.\nLearn how advanced fault models (slack-based transition\, path delay\, and hold-time) can improve the quality of your tests from a timing standpoint.\nGain insights from Synopsys experts on how TestMAX™ ATPG leverages tighter connection with PrimeTime® to better handle timing exceptions (SDC) during test generation. See how ATPG can handle Muti-cycle paths (MCPs).\nLearn how TSO.ai automatically searches for an optimal solution in a large test search space to minimize pattern count and ATPG turn-around time reducing test costs dramatically.\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-advances-in-atpg-from-power-and-timing-awareness-to-intelligent-pattern-search-with-ai/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/12/synopsys-advances-in-atpg-1200x1200-px.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260114T110000
DTEND;TZID=America/Los_Angeles:20260114T120000
DTSTAMP:20260412T014626
CREATED:20250930T070232Z
LAST-MODIFIED:20250930T070232Z
UID:362252-1768388400-1768392000@semiwiki.com
SUMMARY:Webinar: 5 Expectations for the Manufacturing Market in 2026
DESCRIPTION:Discover the 5 Critical Manufacturing Market Trends Reshaping Semiconductors in 2026\nAI-driven investments\, sustainability\, and advanced materials—what’s next for semiconductor manufacturing. \nThe semiconductor manufacturing industry is undergoing a transformative period as AI-driven investments accelerate\, sustainability pressures mount\, and foundries navigate capacity expansion amid weak consumer demand. \nIn this live TechInsights webinar\, our manufacturing experts will highlight five critical developments shaping semiconductor fabrication and equipment markets in 2026\, offering actionable insights for strategists\, foundry operators\, and equipment suppliers. \nKey Topics You’ll Learn \n\nTSMC’s 2nm Mass Production Leadership – Achieving 7% of total capacity by 2026 while foundry/logic CAPEX rises for the first time since 2022.\nChina’s Role in Equipment Sales – Export control uncertainties and slower recovery extending into 2027\, with fabrication emissions projected to reach 200M metric tons CO₂e.\nInventory Optimization & AI Growth – Leveraging oversupply in consumer\, industrial\, and automotive segments to focus on AI-driven production.\nGlass Substrates Challenge Traditional Materials – Superior flatness\, signal integrity\, and sub-2-micron via capabilities for AI accelerators and HBM applications.\nWafer Fab Equipment Growth Focus – Concentration in microlithography for cutting-edge AI chips\, with subsystem suppliers benefiting from Asian capacity expansions.\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-5-expectations-for-the-manufacturing-market-in-2026/
LOCATION:This course will be held Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/09/Screenshot-2025-09-30-000153.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260115T100000
DTEND;TZID=America/Los_Angeles:20260115T120000
DTSTAMP:20260412T014626
CREATED:20251219T204521Z
LAST-MODIFIED:20251219T204742Z
UID:364919-1768471200-1768478400@semiwiki.com
SUMMARY:Webinar: Accelerate IC Layout Parasitic Analysis with ParagonX
DESCRIPTION:We are pleased to offer two webinar sessions for your convenience. Please choose the time that best fits your schedule: \n10:00AM – 12:00PM CET (session #1 for EMEA/APAC)\n10:00AM – 12:00PM PST (session #2 for NA) \nFeatured Speakers: \n\nKopal Kulshreshtha\, Principal Product Specialist\, Synopsys\nRob Dohanyos\, Principal Product Specialist\, Synopsys\n\nIntroducing ParagonX\, a powerful tool for intelligent analysis\, debugging\, simulation\, and visualization of IC layout parasitics. It is perfect for root-cause analysis in top-level analog\, custom digital\, and mixed-signal designs. \nWhy You Should Attend: \n\nAssess and quantify the effects of layout parasitics early in the design process.\nElevate your productivity with rapid iterations that guide layout optimizations.\nSeamlessly integrate ParagonX into your analog and custom design workflow.\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-accelerate-ic-layout-parasitic-analysis-with-paragonx/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/12/SNPS4324872076-ParagonX-Banners-400x400px.jpg
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260121
DTEND;VALUE=DATE:20260122
DTSTAMP:20260412T014626
CREATED:20260107T111253Z
LAST-MODIFIED:20260107T111253Z
UID:365420-1768953600-1769039999@semiwiki.com
SUMMARY:Webinar: Turning Compliance Into Competitive Credibility: Exclusive Launch of New CMMC Readiness Research
DESCRIPTION:About this event\nBe the first to see brand new\, Keysight-commissioned research on Cybersecurity Maturity Model Certification (CMMC) readiness across the U.S. Defense Industrial Base. In this live webinar\, we’ll unveil findings from hundreds of security\, IT\, and compliance leaders and show where organizations really stand. \nPlus\, attendees will be the first to get the full research paper\, The Power of Proof: Turning CMMC Compliance into Competitive Credibility. \n\n\n\n\n\n\nWho should attend this event?\nDesigned for professionals in governance\, risk\, compliance\, security validation\, and program management\, this webinar offers actionable intelligence for any organization preparing for CMMC certification. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-turning-compliance-into-competitive-credibility-exclusive-launch-of-new-cmmc-readiness-research/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-031208.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260127T090000
DTEND;TZID=America/Los_Angeles:20260127T100000
DTSTAMP:20260412T014626
CREATED:20251217T021629Z
LAST-MODIFIED:20251217T021629Z
UID:364770-1769504400-1769508000@semiwiki.com
SUMMARY:Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)
DESCRIPTION:Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process\, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process. \nWhat you will learn \n\nThe breadth of the entire Gencellicon portfolio\nHow timing closure solutions can alleviate your design process using Siemens tools\n\nWho should attend \n\nImplementation engineers\nSoC architects\nDesign Verification teams\nTest engineers\nPower architects\nPhysical designers\n\n\n\n\nSpeaker: \n\n\n\n\nHimanshu Bhatnagar \nSenior Director\, Siemens EDA \n\n\n\nHimanshu brings over 20 years of expertise in chip design\, having developed complex SoCs across networking\, communications\, imaging\, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis\, a practical guide to synthesis and static timing analysis. Before founding Excellicon\, now Gencellicon\, Himanshu held key positions at leading semiconductor companies\, including Mindspeed Technologies\, Conexant Systems\, and ST Microelectronics. At Conexant Systems\, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally\, Himanshu has served as an advisor to various EDA companies. \n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-solving-timing-closure-challenges-using-gencellicon-previously-excellicon/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-16-181547.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260128
DTEND;VALUE=DATE:20260129
DTSTAMP:20260412T014626
CREATED:20260113T043124Z
LAST-MODIFIED:20260113T043124Z
UID:365664-1769558400-1769644799@semiwiki.com
SUMMARY:Webinar: Powering the Future: Megawatt Charging Solutions for Heavy-Duty Electrification
DESCRIPTION:About this event\nJoin our upcoming webinar to discover how Keysight is powering the future of heavy-duty electric transportation with advanced megawatt-charging test solutions. \nLearn how to validate ultra-high-power delivery beyond 3 MW\, ensure compliance with MCS and ISO 15118-20\, and streamline interoperability testing\, all within a single\, fully controllable platform designed for both compliance and development debugging. \nWe’ll explore how seamless integration of software\, hardware\, and project services accelerates the deployment of safe\, scalable\, and standards-driven charging infrastructure for trucks\, ships\, and heavy machinery. \n\n\n\n\n\n\n\nWho should attend this event?\nThose involved in the shift towards a future-proven transportation\, logistics\, and construction ecosystem. Specific titles: OEM Electrification Leaders; EVSE Manufacturers & Charging Infrastructure Developers; Compliance & Standards Specialists; Fleet Electrification Managers: Grid Integration & Energy Management Specialists. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-powering-the-future-megawatt-charging-solutions-for-heavy-duty-electrification/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203022.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260128T100000
DTEND;TZID=America/Los_Angeles:20260128T110000
DTSTAMP:20260412T014626
CREATED:20251211T205410Z
LAST-MODIFIED:20251211T205410Z
UID:364596-1769594400-1769598000@semiwiki.com
SUMMARY:Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
DESCRIPTION:In this webinar\, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks. \nWe will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout. \nWe will show you how these tools work on real designs as well. \nWHO SHOULD ATTEND THIS WEBINAR?\nIf you are designing chips to deploy in networked environments\, you need to understand the risks ahead and how to minimize them. \nIf you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions. \nSPEAKERS\nBeau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies \nDr. Paul Calzada will take you through a live demonstration of CODAx\, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions. \n* This webinar is in partnership with SemiWiki and Caspia Technologies \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-why-ai-assisted-security-verification-for-chip-design-is-so-important/
LOCATION:Online
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