BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//SemiWiki - ECPv6.16.3//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:SemiWiki
X-ORIGINAL-URL:https://semiwiki.com
X-WR-CALDESC:Events for SemiWiki
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20250309T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20251102T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20260308T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20261101T090000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:20270314T100000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:20271107T090000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260624T090000
DTEND;TZID=America/Los_Angeles:20260624T120000
DTSTAMP:20260617T090250
CREATED:20260518T213746Z
LAST-MODIFIED:20260518T213746Z
UID:369367-1782291600-1782302400@semiwiki.com
SUMMARY:Synopsys Virtual Prototyping Day
DESCRIPTION:Join us for our 6th Annual Virtual Prototyping Day and learn how you can “shift left” your development cycle with virtual prototypes. \nHighly complex SoC and muti-die designs are putting pressure on silicon and software development teams to meet time-to-market demands. Virtual prototypes are the answer to begin development earlier\, reduce costs\, collaborate across teams\, and get your design to market faster. \nThis popular series features customers and partners who will present how they solve their design challenges using virtual prototypes. \nThis is an on-line event where you can attend from the convenience of your office\, home\, or anywhere you happen to be! \nWe have 2 specialized tracks designed to cater to the diverse interests and needs of our community: \nTrack 1 – System Architecture Design & Exploration \nOptimize the efficiency and performance of complex systems by enabling early architecture design exploration and optimization. This approach helps in identifying potential issues and opportunities for improvement\, ultimately leading to reduced development costs and faster time-to-market. \nTrack 2 – Software Development & Test \nEnhance software development and testing with a virtual environment\, where developers can simulate and validate system behavior without the need for physical hardware. This accelerates the development process\, improves early detection of issues\, and reduces costs associated with hardware dependencies and testing infrastructure. \nREGISTER HERE
URL:https://semiwiki.com/event/synopsys-virtual-prototyping-day/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-18-143657.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260625T090000
DTEND;TZID=America/Los_Angeles:20260625T100000
DTSTAMP:20260617T090250
CREATED:20260602T201039Z
LAST-MODIFIED:20260604T000532Z
UID:369891-1782378000-1782381600@semiwiki.com
SUMMARY:Webinar: Intel: Pushing EMIB Forward Design Methodology Insights with Synopsys Tools - SemiWiki
DESCRIPTION:Date: Jun 25\, 2026 | 9:00 AM PST \n\n\nIn this webinar\, Intel will present how EMIB (Embedded Multi‑die Interconnect Bridge) enables compact\, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share an EMIB reference methodology built on Synopsys 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump planning\, automated die-to‑die routing for HBM and UCIe\, and a unified exploration‑to-signoff data model help Intel manage system‑level co-design complexity while maintaining closure on timing\, power\, thermal\, and SIPI. Intel will also discuss SIPI methodology using Synopsys Tools and EMIB’s ability to support dense\, high‑speed HBM interfaces. \nWhat you’ll learn \n\nHow EMIB addresses key multi-die design challenges\nWhy early bump planning is critical for EMIB success\nHow automated die-to-die routing accelerates convergence\nHow a unified flow supports scalable timing\, power\, thermal\, and SIPI signoff\nHow EMIB enables high-speed HBM integration with confidence\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSadha Parasuraman \nDesign Methodology Architect and EDA Enablement Manager\, Intel\n \nSadha Parasuraman is an EDA Enablement Manager and Design Methodology Architect for advanced design and customer enablement at Intel Foundry. Sadha’s Extensive experience in design flows and methodology stacks across semiconductor technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intel-pushing-emib-forward-design-methodology-insights-with-synopsys-tools/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/06/synopsys-intel-linkedin-update-1200x1200-v3.jpg
END:VEVENT
END:VCALENDAR