All the Solutions for Developing Chiplets 2025 Keynote Addresses from Industry Leaders: Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne 2025’s Main Topics Included: AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries signup to be a 2026 SPONSOR / Exhibitor REGISTER HERE
For more than three decades, SNUG Silicon Valley has connected engineers, designers, and thought leaders with technical experts to network and share best practices for tackling design and verification challenges using Synopsys technologies. The Call for Content invites you to showcase how you are developing tomorrow’s products today with Synopsys solutions. This year, in addition …
As AI workloads scale into the thousands of accelerators and hundreds of terabytes of distributed memory, traditional interconnects cannot deliver the deterministic latency, bandwidth efficiency, or memory semantic operations required for modern training clusters. UALink provides a purpose built accelerator fabric leveraging 224G SerDes, fixed 64 byte flits, compressed transaction formats, and high efficiency TL/DLL …
Continue reading "Webinar: Understanding UALink Architecture: A Protocol Deep Dive"
In this webinar, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated, compute intensive 3D FEM cycles during development, Marvell uses a Method of Moments (MoM) early SI check available within …
Physical AI is increasingly popular in applications requiring real-time decision making and autonomous operation. Different from NPUs for cloud platforms, Physical AI processors can be made application-specific. By jointly tuning their ISA and memory architecture to the network models required by the application, power consumption and silicon area are drastically reduced. Synopsys ASIP Designer is …
Continue reading "Webinar: Application-Specific Processors (ASIPs) for Physical AI"
As semiconductors continue to scale, designers are turning to 3DIC architectures to meet increasing demands for performance, energy efficiency, and functional density in data centers and edge AI applications. However, stacking multiple dies introduces new multiphysics challenges including electrical, structural, and thermal issues. Join this webinar to learn how RedHawk-SC Electrothermal enables designers to analyze …
Continue reading "Webinar: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal"
As power integrity challenges increase with advanced nodes and multi-die architectures, EMIR analysis must evolve beyond traditional signoff. In this Synopsys webinar, we will show how RedHawk-SC is expanding its capabilities not only to enhance EMIR analysis, but also to enable IR-aware Static Timing Analysis (IR-STA) and IR-driven ECO (IR-ECO) flows. Join us to learn how tighter integration …
Continue reading "Webinar: RedHawk-SC: From EMIR Signoff to IR-Aware Design Closure"
In this webinar, Intel will present how EMIB-T (Embedded Multi-die Interconnect Bridge with TSVs) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share a production-oriented EMIB-T reference methodology built on Synopsys' 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump …
