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SUMMARY:Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI
DESCRIPTION:*Company Email Required for Registration* \nFull-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms\, logs\, and across hundreds of thousands of lines of code. \nIn this webinar\, we will demonstrate how the Bronco AI Debug Agent performs root-cause analysis (RCA) on real production issues in under 15 minutes\, with a 70% success rate on customer regressions. You will see the agent operate end-to-end on a representative full-chip SoC\, from a failing regression to an annotated root cause\, while interoperating with customer’s standard commercial EDA flows. \nWhat we will cover: \n– Live demonstration of the Debug Agent on a full-chip SoC regression failure\n– How the agent navigates massive codebases\, logs\, and waveforms to isolate failure mechanisms\n– Deployment patterns at large public chip companies and as well as fast-moving startups\n– How bring-your-own-model and on-prem deployment keep customer IP inside your environment.\n– How Bronco gets better without ever training on customer data. \nWho should attend: \n– DV engineers and managers responsible for regression triage and production debug\n– SoC verification leads evaluating AI-native tooling for their flows\n– VPs of Engineering and Silicon leaders tracking DV cycle time and engineering ROI\n– Security and infrastructure owners assessing on-prem AI deployment for chip design \nSpeaker: \nDavid Zhi LuoZhang\, Co-Founder and CEO of Bronco AI\, will walk through the live demonstration on a real design and take questions how customers deploy\, evaluate\, and scale Bronco within their silicon projects. David works tightly with customers to deploy Bronco and coordinates between the core R&D\, customer\, and industry-relations teams at Bronco. \n*This webinar is in partnership with SemiWiki and Bronco AI* \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-cutting-full-chip-soc-debug-from-days-to-minutes-with-ai/
LOCATION:Online
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DTSTART;VALUE=DATE:20260623
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SUMMARY:Verification Futures Conference 2026 UK
DESCRIPTION:Verification Futures UK 2026\, co-located with Semiconductors Futures 2026 organised by Tessolve and co-organised this year with Alpinum. The conference continues its strong tradition of delivering a unique blend of conference presentations\, exhibitions\, training\, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers\, researchers\, and vendors to shape practical solutions. In 2026\, Verification Futures continues to strengthen its core emphasis on verification methodologies\, DV tools\, and engineering workflows\, including areas such as formal methods for complex SoCs\, CPU & RISC-V verification\, open-source and licence-free verification tools\, AI in design verification (AI in DV)\, verification planning and coverage\, and HW/SW co-verification. \nSemiconductors Futures 2026 brings together the semiconductor community\, covering AI/ML in IP & SoC design\, AI’s impact on EDA and workflows\, FPGA & mixed-signal\, with a focus on the automotive\, data centre\, and AI products. New tracks consider emerging technologies such as quantum computing\, photonics\, and chiplets\, as well as startups and investments. We expect 50+ engineering students to attend a separate session. \nCALL FOR PAPERS \nREGISTER HERE
URL:https://semiwiki.com/event/verification-futures-conference-2026-uk/
LOCATION:Hybrid: In-Person and Virtual Conference\, Reading\, United Kingdom
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