An infrastructure to enable debug and trace for your RISC-V systems is essential to identifying root-causing bugs. In this presentation, we will give an overview of Tessent UltraSight-V, an end-to-end …
As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be …
As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be …
Software Defines Everything For today’s SoC and system designs, hardware is designed and optimized for the software workload. Workloads can include firmware, multi-OS architectures, AI/ML and complex graphics. These combined …
Continue reading "Webinar: Using Veloce PCD to implement an Arm CSS with confidence"
Join us in Munich where peer-delivered technical sessions will be shared across a breadth of topics so you can explore new concepts or dive deep in your core area of …
Join us for the User2User North America event, which is a dedicated environment for exchanging ideas, information, and best practices that enable you to lead in your role and achieve …
Wednesday, May 21 - 8:00 AM Pacific The semiconductor industry faces a critical Verification Productivity Gap 2.0, driven by increasingly complex technologies including 3DICs, chiplet-based designs, and software-defined architectures. This …
Wednesday, May 28 - 8:00 AM Pacific Managing traceability across multiple disconnected tools and data is a challenge that often leads to inefficiencies, missed coverage, and increased risk in safety-critical …
Join our community of thinkers and doers in design, manufacturing, and lifecycle management to accelerate your digital transformation. Detroit, Michigan | June 2-5, 2025 Registration opens Jan. 14, 2025. Where …
Wednesday, June 4 - 8:00 AM Pacific In today's automotive electronics, ensuring functional safety is paramount for meeting stringent industry standards. This webinar introduces Questa One Sim FX, a cutting-edge …
Continue reading "Webinar: Enhancing Automotive Safety Verification Using Questa One Sim FX"
Rising semiconductor complexity—driven by multi-die architectures, the move towards more advanced technology nodes, and more stringent reliability targets, is dramatically increasing the volume of verification required to achieve DFT verification …
Continue reading "Webinar: Tackling Emerging DFT Verification Challenges with Questa One"
This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes SystemVerilog UVM verification workflows. Traditional coverage closure methods, relying on constrained-random stimulus generation and iterative manual …
Continue reading "Webinar: Accelerating Functional Coverage with Questa One Sim CX"
