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DTSTART;TZID=America/Los_Angeles:20260519T090000
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SUMMARY:Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
DESCRIPTION:Featured Speaker: \n\nVictoria Kolesov\, Principal Engineer\, Intel\n\nIn this Synopsys webinar\, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and 3D layout verification in both passive and active interposer designs. The session highlights how increasing accuracy requirements have shaped 3D construction practices\, standards\, and collateral\, enabling consistent\, correct‑by‑construction signoff across process nodes\, TSVs\, and complex die‑to‑die interconnects. \nWhat you’ll learn: \n\nHow Intel approaches 3DIC construction for disaggregated designs\nKey requirements for static timing and layout signoff in 3DIC flows\nDifferences between passive and active interposer signoff considerations\nHow accuracy requirements influence 3D construction methodologies\nBest practices for achieving correct‑by‑construction 3DIC signoff\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVictoria Kolesov \nPrincipal Engineer\, Intel \nVictoria Kolesov joined Intel in 2001 and has held a variety of responsibilities including RTL development\, design completion\, and design automation. Her current focus is interconnect implementation and 3D design integration. Victoria obtained her MS in Computer Science from St.Petersburg Technical University\, Russia. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intel-from-construction-to-signoff-3dic-methodology-for-disaggregated-designs/
LOCATION:Online
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