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SUMMARY:Webinar: Intel: Pushing EMIB Forward Design Methodology Insights with Synopsys Tools
DESCRIPTION:Date: Jun 25\, 2026 | 9:00 AM PST \n\n\nIn this webinar\, Intel will present how EMIB (Embedded Multi‑die Interconnect Bridge) enables compact\, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share an EMIB reference methodology built on Synopsys 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump planning\, automated die-to‑die routing for HBM and UCIe\, and a unified exploration‑to-signoff data model help Intel manage system‑level co-design complexity while maintaining closure on timing\, power\, thermal\, and SIPI. Intel will also discuss SIPI methodology using Synopsys Tools and EMIB’s ability to support dense\, high‑speed HBM interfaces. \nWhat you’ll learn \n\nHow EMIB addresses key multi-die design challenges\nWhy early bump planning is critical for EMIB success\nHow automated die-to-die routing accelerates convergence\nHow a unified flow supports scalable timing\, power\, thermal\, and SIPI signoff\nHow EMIB enables high-speed HBM integration with confidence\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSadha Parasuraman \nDesign Methodology Architect and EDA Enablement Manager\, Intel\n \nSadha Parasuraman is an EDA Enablement Manager and Design Methodology Architect for advanced design and customer enablement at Intel Foundry. Sadha’s Extensive experience in design flows and methodology stacks across semiconductor technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intel-pushing-emib-forward-design-methodology-insights-with-synopsys-tools/
LOCATION:Online
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