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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260419
DTEND;VALUE=DATE:20260424
DTSTAMP:20260420T055924
CREATED:20260107T100748Z
LAST-MODIFIED:20260107T100748Z
UID:365363-1776556800-1776988799@semiwiki.com
SUMMARY:2026 IEEE Custom Integrated Circuits Conference (CICC)
DESCRIPTION:Join us for CICC 2026\, the world’s premier conference devoted to IC development. \n\n\n\n\n\n\nApril 19 – 22\, 2026 Seattle\, WA\, USA \n\n\n\n\n\n\nApril 22 – 23\, 2026 – CHISIC Workshop \nAbout CICC\n\n\nThe IEEE Custom Integrated Circuits Conference is a premier conference devoted to IC development. The conference program is a blend of oral presentations\, exhibits\, panels and forums. The conference sessions present original first published technical work and innovative circuit techniques that tackle practical problems. CICC is the conference to find out how to solve design problems\, improve circuit design techniques\, get exposure to new technology areas\, and network with peers\, authors and industry experts. \nThere are 3 days of Technical Sessions that include lecture presentations addressing state of the art developments in integrated circuit design. The Educational Sessions are a full day of tutorials instructed by recognized invited speakers. The Panels\, and Forums are presented throughout the conference to enrich the learning experience of the attendees. The Panel Discussions and Forums are presented by leaders from the IC industry. CICC includes an Exhibits Hall that is open in the evenings where Semiconductor manufacturers\, software tool suppliers\, silicon IP providers\, design-service houses\, and technical book publishers offer displays and demonstrations of their products. CICC is sponsored by the IEEE Solid-State Circuits Society and technically co-sponsored by the IEEE Circuits and Systems Society. \n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/2026-ieee-custom-integrated-circuits-conference-cicc/
LOCATION:Seattle\, Washington\, Seattle\, WA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-020639.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260420
DTEND;VALUE=DATE:20260423
DTSTAMP:20260420T055924
CREATED:20250828T055712Z
LAST-MODIFIED:20250828T055712Z
UID:361084-1776643200-1776902399@semiwiki.com
SUMMARY:DATE 2026
DESCRIPTION:Design\, Automation and Test in Europe Conference |\nThe European Event for Electronic System Design & Test\nCall for Papers\n\n\nThe DATE conference is the main European event bringing together designers and design automation users\, researchers and vendors\, as well as specialists in hardware and software design\, test\, and manufacturing of electronic circuits and systems. DATE places a strong emphasis on both technology and systems\, covering ICs/SoCs\, reconfigurable hardware\, and embedded systems\, as well as embedded software. \nThe three-day event consists of a conference with regular papers\, extended abstracts\, and late breaking results\, complemented by timely keynotes\, special days\, focus sessions\, embedded tutorials\, half-day workshops\, and multi-partner project sessions. The event will also host the Young People Programme fostering networking and exchanges of information on relevant issues\, recent research outcomes\, and career opportunities for junior researchers. Poster-supported live interactions and pre-recorded videos are available to complement all research paper presentations before\, during\, and after the conference. \nDATE 2026 is the 29th edition of an event that has always been the place for researchers\, young professionals\, and industrial partners to meet\, present their research\, and discuss current developments and upcoming trends\, with high emphasis on social interaction. \nConference Scope\nThe conference addresses all aspects of research into technologies for electronic and systems engineering. It covers the design process\, test\, and tools for design automation of electronic products\, ranging from integrated circuits to distributed large-scale systems. This domain includes both hardware and embedded software design issues. The conference scope also includes the specification of design requirements and new architectures for challenging application fields such as sustainable computing\, smart societies and digital wellness\, secure systems\, autonomous systems and smart industry\, and state-of-the-art applications of artificial intelligence. Engineers\, scientists\, and researchers involved in innovative industrial designs are particularly encouraged to submit papers to foster feedback ranging from design to research aspects. \nConference Sponsors\nThe event is sponsored by the European Design and Automation Association (EDAA)\, the Electronic System Design Alliance (ESDA)\, the IEEE Council on Electronic Design Automation (IEEE CEDA) and the ACM Special Interest Group on Design Automation (ACM SIGDA). \nIn cooperation with IEEE Computer Society Test Technology Technical Community (TTTC)\, IEEE Solid-State Circuits Society (SSCS) and IEEE Computer Society (IEEE CS). \nConference Committees\nThe conference leverages the support of multiple committees to support its organisation. The DATE Sponsors Committee supervises the overall structure and operations of the conference; the Executive Committee designs and implement the yearly programme of the conference\, and the Technical Programme Committee is dedicated to develop reviews and select the research manuscripts to be published at the conference. \n\nDATE Sponsors Committee (DSC)\nDATE Executive Committee (DEC)\nTechnical Programme Committee (TPC)\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/date-2026/
LOCATION:Palazzo della Gran Guardia\, Palazzo della Gran Guardia\, Piazza Brà\, Verona\, 37121\, Italy
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-225522.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260420
DTEND;VALUE=DATE:20260424
DTSTAMP:20260420T055924
CREATED:20260320T201032Z
LAST-MODIFIED:20260320T201032Z
UID:367720-1776643200-1776988799@semiwiki.com
SUMMARY:Semiconductor Reliability and Product Qualification
DESCRIPTION:Product reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past\, reliability meant discovering\, characterizing and modeling failure mechanisms\, and determining their impact on the reliability of the circuit. Today\, reliability can involve tradeoffs between performance and reliability; assessing the impact of new materials; dealing with limited margins\, and other factors. This requires information on subjects like: statistics\, testing\, technology\, processing\, materials science\, chemistry\, and customer expectations. While customers expect high reliability levels\, incorrect testing\, calculations\, and qualification procedures can severely impact reliability. Semiconductor Reliability and Product Qualification is a 4-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and qualification. This course is designed for every manager\, engineer\, and technician concerned with reliability in the semiconductor field\, qualifying semiconductor components\, or supplying tools to the industry. \nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what failure mechanisms might occur\, and how to test for them\, develop models for them\, and eliminate them from the product. This skill building series is divided into four segments: \n\nOverview of Reliability and Statistics. Participants will learn the fundamentals of statistics\, sample sizes\, distributions and their parameters.\nFailure Mechanisms. Participants will learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die and at the package level. These include: time-dependent dielectric breakdown\, hot carrier degradation\, electromigration\, stress-induced voiding\, moisture\, corrosion\, contamination\, thermomechanical effects\, interfacial fatigue\, and others.\nQualification Principles. Participants will learn how test structures can be designed to help test for a particular failure mechanism.\nTest Strategies. Participants will learn about the JEDEC test standards\, how to design screening tests\, and how to perform burn-in testing effectively.\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the failure mechanisms\, test structures\, equipment\, and testing methods used to achieve today’s high reliability components.\nParticipants will be able to gather data\, determine how best to plot the data and make inferences from that data.\nThis course will identify the major failure mechanisms\, explain how they are observed\, how they are modeled\, and how they are eliminated.\nThis course will offer a variety of video demonstrations of analysis techniques\, so the participants can get an understanding of the types of results they might expect to see with their equipment.\nParticipants will be able to identify the steps and create a basic qualification process for semiconductor devices.\nParticipants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.\nParticipants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.\n\nREGISTER HERE
URL:https://semiwiki.com/event/semiconductor-reliability-and-product-qualification/
LOCATION:San Jose\, CA
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-20-130723.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260421T090000
DTEND;TZID=America/Los_Angeles:20260421T100000
DTSTAMP:20260420T055924
CREATED:20260401T065505Z
LAST-MODIFIED:20260401T065640Z
UID:368025-1776762000-1776765600@semiwiki.com
SUMMARY:Webinar: Understanding UALink Architecture: A Protocol Deep Dive
DESCRIPTION:As AI workloads scale into the thousands of accelerators and hundreds of terabytes of distributed memory\, traditional interconnects cannot deliver the deterministic latency\, bandwidth efficiency\, or memory semantic operations required for modern training clusters. UALink provides a purpose built accelerator fabric leveraging 224G SerDes\, fixed 64 byte flits\, compressed transaction formats\, and high efficiency TL/DLL aggregation to achieve predictable\, low overhead load/store communication across large GPU pools. With multi virtual channel flow control\, source ordered routing\, and integrated AES GCM encryption via UALinkSec\, the architecture is engineered for high performance\, secure AI fabrics. \nThis session will review a breakdown of how UALink enables scalable memory pooling\, reduces communication overhead\, and supports pod  and rack scale GPU integration. We will examine the behavior of the UPLI\, Transaction Layer\, and Data Link Layer and discuss silicon level implementation considerations for accelerators and switches. \nWhat you’ll learn: \n\nHow UALink implements low latency\, memory semantic GPU to GPU communication\nInternal structure of 64 byte flits\, compressed request/response formats\, and TL/DLL packing\nHow multi VC flow control\, link level retry\, and RS FEC ensure deterministic\, lossless throughput\nThe role of UALinkSec in enforcing end to end AES GCM encryption and authentication\nHow UALink enables scalable memory pooling and GPU clustering across pods and racks\nSystem level design considerations for integrating UALink controllers\, PHYs\, and switches\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDiwakar Kumaraswamy \nSr. Staff Technical Product Manager \nWith over 15 years of experience in Application Engineering and SoC design\, Diwakar has built a career spanning FPGA development\, global IP support\, and technical leadership. Beginning at CoreEL Technologies with Xilinx FPGA implementations and corporate training\, he went on to lead customer success for PCIe\, CXL\, AMBA\, and other interface IP at Synopsys\, followed by NoC architecture work at Intel. Now a Technical Product Manager at Synopsys\, he drives high-speed interconnect solutions—such as Ethernet\, PCIe\, and UALink—for next-generation AI infrastructure. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-understanding-ualink-architecture-a-protocol-deep-dive/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/03/Synopsys-understanding-ualink-architecture-webinar-1200x628-1.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260422T080000
DTEND;TZID=America/Los_Angeles:20260422T090000
DTSTAMP:20260420T055924
CREATED:20260414T062544Z
LAST-MODIFIED:20260414T062544Z
UID:368400-1776844800-1776848400@semiwiki.com
SUMMARY:Webinar: HDI Design Workflow: From Decisions to Fabrication
DESCRIPTION:Ensure fabrication success with proven HDI design techniques and real-world tools.\nOverview:\n\nAs AI accelerators and edge compute modules push PCB densities to their physical limits\, HDI design has become the defining skill separating production-ready boards from layouts that fail at fabrication. This webinar walks through the complete HDI workflow inside Allegro X using a NVIDIA Jetson-based carrier board. \nYou will learn how to:\n\nArchitect the layer stackup and define blind\, buried and microvia structures\nNavigate fine-pitch BGA breakout routing\nConduct in-design DFM validation to ensure fabrication success\n\nAttendees will leave with a clear\, process-driven understanding of how HDI design decisions are made in real tools on real hardware and learn how to validate those decisions before a board ever reaches a fabrication house. \n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-hdi-design-workflow-from-decisions-to-fabrication/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-232509.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260422T083000
DTEND;TZID=America/Los_Angeles:20260422T173000
DTSTAMP:20260420T055924
CREATED:20260326T212327Z
LAST-MODIFIED:20260326T212327Z
UID:367920-1776846600-1776879000@semiwiki.com
SUMMARY:TSMC 2026 North America Technology Symposium
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-2026-north-america-technology-symposium/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-26-142210.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260426
DTEND;VALUE=DATE:20260502
DTSTAMP:20260420T055924
CREATED:20260107T101053Z
LAST-MODIFIED:20260107T101053Z
UID:365366-1777161600-1777679999@semiwiki.com
SUMMARY:2026 MRS Spring Meeting & Exhibit
DESCRIPTION:The 2026 MRS Spring Meeting & Exhibit\, taking place April 26–May 1 in Honolulu\, Hawai‘i\, will convene materials researchers from academia\, industry\, government and national laboratories together for a week of cross-disciplinary collaboration and scientific exchange. Set against the backdrop of one of MRS’s most inspiring locations\, the Meeting & Exhibit will feature breakthroughs in areas such as sustainable manufacturing\, advanced characterization and energy materials—driving forward innovation on a global scale. \nBuilding on this inspiring setting\, the Meeting will span four official venues in Honolulu. Technical programming\, events and accommodations will be distributed within the city’s walkable\, picturesque layout\, creating a dynamic\, interconnected format that will support active engagement and collaboration while maintaining a focused environment for research and application dialogue throughout the Meeting week. \nWhether you’re looking to present new research\, explore emerging technologies\, or engage with peers across disciplines\, the 2026 MRS Spring Meeting will provide an unforgettable experience in an extraordinary location. \nREGISTER HERE
URL:https://semiwiki.com/event/2026-mrs-spring-meeting-exhibit/
LOCATION:Honolulu\, Hawaii\, Honolulu\, HI\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/1758156481328.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260428
DTEND;VALUE=DATE:20260429
DTSTAMP:20260420T055924
CREATED:20260107T101352Z
LAST-MODIFIED:20260107T101352Z
UID:365369-1777334400-1777420799@semiwiki.com
SUMMARY:User2User North America 2026
DESCRIPTION:Join us for the User2User North America event\, which is a dedicated environment for exchanging ideas\, information and best practices that enable you to lead in your role and achieve success with your customers. \nBecome a Speaker\nAbout User2User\nUser2User is your opportunity to learn\, grow and connect with fellow technical experts who design leading-edge products using Siemens electronic design automation (EDA) tools. \nWhat to expect?\nA dedicated environment for exchanging ideas\, information\, and best practices that enable you to lead in your role and achieve success with your customers. \n\nTechnical agenda concentrated on the digital future\nIndustry leaders exploring macro trends and innovation\nSuper users sharing business challenges and roadblocks\nCase studies demonstrating business results\nNetworking with like-minded peers in EDA\n\nREGISTER HERE
URL:https://semiwiki.com/event/user2user-north-america-2026/
LOCATION:Santa Clara Marriott\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-021240.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260428T090000
DTEND;TZID=America/Los_Angeles:20260428T100000
DTSTAMP:20260420T055924
CREATED:20260410T023253Z
LAST-MODIFIED:20260410T023253Z
UID:368275-1777366800-1777370400@semiwiki.com
SUMMARY:Webinar: Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis
DESCRIPTION:In this webinar\, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early\, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated\, compute intensive 3D FEM cycles during development\, Marvell uses a Method of Moments (MoM) early SI check available within Synopsys 3DIC Compiler to evaluate routing with real parasitics and simulation data\, fast enough to support rapid iteration and safer exploration of auto routing strategies.  Marvell will also share practical correlation takeaways\, where MoM tracks FEM strongly and where additional margin and correlation work may be needed ahead of final signoff. \nWhat you’ll learn \n\nWhy traditional interposer SI signoff can become a major schedule bottleneck\nHow early SI analysis with MoM differs from FEM and where it fits best\nHow to use physics-based SI feedback during interposer routing iterations\nWhen and how to correlate early SI results with FEM for confidence and margin\nHow early SI enables faster convergence and broader design space exploration\n\n\n\n\n\nFeatured Speakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nNitin Navale \nSenior Principal CAD Engineer\, Marvell \nNitin Navale currently serves as 3DIC Methodology Lead at Marvell Semiconductor. He previously worked at AMD & Xilinx for nearly 20 years\, where he contributed to CAD & Methodology across a wide range of disciplines spanning 3DIC\, Signoff\, RTL/Netlisting\, and Physical Verification. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois\, Urbana-Champaign. Outside work\, he is consumed by his devotion to gaming\, strategy\, and music. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nAdish Mehta \nSenior Staff Engineer\, Marvell \nAdish Mehta is a seasoned semiconductor professional specializing in EM/IR signoff\, power integrity\, and signal electromigration analysis for advanced SoC and multi-die designs. He has led the development of scalable\, hierarchical\, and in-context signoff methodologies that improve reliability and design efficiency across bleeding-edge technology nodes. Adish frequently collaborates with global design teams\, foundries\, and EDA vendors to drive innovation in power and reliability analysis\, helping deliver robust\, production-ready silicon across a variety of platforms. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-marvell-accelerating-interposer-design-with-early-signal-integrity-analysis/
LOCATION:Online
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2026/03/Synopsys-Reports-Record-Quarterly-Revenue-for-Q1-FY-2024.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260429
DTEND;VALUE=DATE:20260501
DTSTAMP:20260420T055924
CREATED:20260107T101637Z
LAST-MODIFIED:20260107T101637Z
UID:365373-1777420800-1777593599@semiwiki.com
SUMMARY:SEMIEXPO Heartland
DESCRIPTION:FOCUSED ON SMART MANUFACTURING & SMART MOBILITY\n\n\nDRIVING SEMICONDUCTOR BUSINESS IN THE MIDWEST \nThank you for being part of the launch of SEMIEXPO Heartland—where Smart Manufacturing and Smart Mobility came together like never before! This groundbreaking event opened new opportunities for collaboration and growth\, driving us toward the semiconductor industry’s $1T future. \nWith so much innovation concentrated in the Midwest\, SEMIEXPO Heartland is just getting started. Stay tuned for our next chapter in Spring 2026—we’ll see you in Detroit\, MI! Get ready for even more inspiration\, insights\, and connections at the intersection of two critical markets. \nMAKE AN IMPACT AT THE INAUGURAL SEMIEXPO HEARTLAND \nPlan Now to Exhibit or Sponsor. Contact—\nShane Poblete | +1 202-847-5983 | spoblete@semi.org \n\n\n\n\n2025 Post Show Report\n\n\n\n\n\n\n\nAnalytics & Statistics\nAttendee Demographics\nKeynotes\nProgram Highlights\nAnd more!\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semiexpo-heartland/
LOCATION:Detroit Marriott at the Renaissance Center\, 400 Renaissance Dr W\, Detroit\, MI\, 48243\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-021542.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260429T070000
DTEND;TZID=America/Los_Angeles:20260429T080000
DTSTAMP:20260420T055924
CREATED:20260414T051207Z
LAST-MODIFIED:20260414T051207Z
UID:368340-1777446000-1777449600@semiwiki.com
SUMMARY:Webinar: Application-Specific Processors (ASIPs) for Physical AI
DESCRIPTION:Physical AI is increasingly popular in applications requiring real-time decision making and autonomous operation.  Different from NPUs for cloud platforms\, Physical AI processors can be made application-specific.  By jointly tuning their ISA and memory architecture to the network models required by the application\, power consumption and silicon area are drastically reduced. \nSynopsys ASIP Designer is the industry-leading tool to explore\, design\, and optimize application-specific instruction-set processors (ASIPs)\, including custom NPUs for physical AI. \nIn this Synopsys webinar\, we present the design of “SmarT”\, an ASIP with a RISC-V ISA augmented with specialized vector units for convolutions and quantization\, with 64 MACs. It supports circular gather/scatter addressing of vector data in parallel with computations. Low-overhead DMA moves data blocks from external to local memory. \nNext\, we present a multi-core RISC-V based accelerator for hyperdimensional computing\, designed with ASIP Designer by TU Munich. It applies near-memory computing (NMC) to minimize power consumption and memory bandwidth. This 5-core chip is the first university-led tape-out in Germany using TSMC 7nm technology. \nLearn about: \n\nSynopsys ASIP Designer\, the industry-leading tool to explore\, design and optimize application specific processors\nASIP Design methodologies to address challenges in jointly optimizing the memory architecture and the computational resources for Physical AI architectures\nTwo ASIP designs examples with customize memory architectures for Physical AI applications\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Falco Munsche \nTechnical Product Marketing\, Synopsys \nFalco Munsche is the Technical Product Manager for ASIP design tools at Synopsys. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare\, and as a Design Consultant for Synopsys. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nProf. Hussam Amrouch \nTechnical University of Munich\, Germany \nHussam Amrouch is Professor heading the Chair of AI Processor Design within the Technical University of Munich (TUM). He is the head of Brain-inspired Computing at the Munich Institute of Robotics. Further\, he is the head of the Semiconductor Test and Reliability at the University of Stuttgart. He is the Academic Director of TUM Venture Labs. He is Founding Director of the Munich Advanced-Technology Center for AI Chips (MACHT-AI). \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-application-specific-processors-asips-for-physical-ai/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Synopsys-ASIP-webinar-800x800-2.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260430T090000
DTEND;TZID=America/Los_Angeles:20260430T100000
DTSTAMP:20260420T055924
CREATED:20260408T195314Z
LAST-MODIFIED:20260408T195314Z
UID:368236-1777539600-1777543200@semiwiki.com
SUMMARY:Webinar: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal
DESCRIPTION:As semiconductors continue to scale\, designers are turning to 3DIC architectures to meet increasing demands for performance\, energy efficiency\, and functional density in data centers and edge AI applications. However\, stacking multiple dies introduces new multiphysics challenges including electrical\, structural\, and thermal issues. Join this webinar to learn how RedHawk-SC Electrothermal enables designers to analyze the multiphysics behavior of chips all at once in complex multi-die designs. \nTogether\, Synopsys and Ansys\, part of Synopsys\, provide engineers a comprehensive flow that offers in-design analysis along with final signoff\, enabling faster and more confident development of next-generation multi-die designs. \nAttend this webinar to:  \n\nEnhance your understanding of RedHawk-SC Electrothermal as a foundry-certified multiphysics integrity tool for multi-die designs\nLearn about new features and flow capabilities for 2.5D/3D thermal and mechanical analysis\, including GPU acceleration and ML-based solver\nIntegration of multiphysics simulation in Synopsys implementation and signoff solutions\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Lang Lin \nProduct Management\, Principal \nDr. Lang Lin\, Product Management\, Principal \nBio: Dr. Lang Lin is a technology leader at Synopsys Inc.\, where he directs product strategy for EDA solutions that ensure the multiphysics integrity\, reliability\, and security of advanced IC and multi die systems. With a Ph.D. in Electrical and Computer Engineering from the University of Massachusetts\, his background spans low power design\, multi-die design\, and hardware security—areas that continue to influence his work at the intersection of multiphysics modeling and secure silicon design. Dr. Lin has co authored over 40 papers and patents\, and his work has been recognized with top honors including IEEE HOST Best Paper Award\, IEEE DAC Best Paper Award\, and the Ansys CEO Innovation Award. He worked for Intel and Ansys before his product management role at Synopsys. \nProfile: Lang Lin | Synopsys \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-powering-3d-multi-die-designs-with-redhawk-sc-electrothermal/
LOCATION:Online
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