SemiWiki

Digital Twin Models for Semiconductor Manufacturing Unit Process: A SEMI Master Class
2025-11-05 10:00 - 12:00 (America/Los_Angeles) | Online
Join us for this engaging Master Class with Benyamin Davaji, PhD, Assistant Professor of Electrical and Computer Engineering at Northeastern University and Peter Doerschuk, Professor of Electrical and Computer Engineering and Biomedical Engineering at Cornell University, as they explore the role of digital twin models in advancing semiconductor manufacturing. The masterclass will highlight how data-guided methods and computational modeling are transforming unit process development, driving efficiency and innovation across the semiconductor industry. With expertise spanning microsystems, acoustic transducers, and nanofabrication, he will provide insights into how digital twins can bridge research and production to accelerate breakthroughs in semiconductor technology.

A digital twin is a computer representation of the structure, context, and behavior of physical systems, which are critical components in the optimization of computational systems, accurately representing physical systems and processes. A Digital Twin can be used to reduce or eliminate iterative physical experiments needed for optimization, thereby enhancing yield, saving time, and resources. Semiconductor manufacturing involves numerous complex steps, where accurate control of each step is crucial to achieving the overall manufacturing yield and minimizing variations in device characteristics. The complexity of the manufacturing processes’ flows limits flexibility for testing novel approaches. Unit processes can be based on first-principal models (physics-based), data-based models, or hybrid models combining both approaches when possible. Fabrication processes in the cleanroom and on printed electronics tools are often a function of time-varying parameters, including those of the equipment, environment, and materials. The parameters often have co-dependencies across different process steps and tool sets.
This course will cover the necessary material to create DNN-based Digital twins for nanofabrication processes in cleanrooms. The course will include experimental details for data preparation, data processing, training models, and use case demonstrations. Nanofabrication process equipment can inherently have millions of internal variables and can learn from datasets, providing a robust and complementary approach to traditional feedback control and process stabilization methods. The included Digital Twin modes are developed using images (CD-SEMs, optical images), time history data (Optical Emission Spectroscopy), and textual process information (recipes and materials). The course will include: (1) Approaches to preprocess image data and create learning-based models, (2) using DNN-based domain translation for learning to predict the DUV nanolithography and ICP Plasma Etch, (3) virtual metrology methods for quantification of learning outcomes, and (4) developing a new class of process-aware DNN-based digital twins.
ABOUT THE SPEAKERS

Moderator
Gity Samadi, PhD
Sr. Director, R&D Programs
SEMI

Ben Davaji, PhD
Assistant Professor
Northeastern University
Benyamin Davaji, PhD
Benyamin Davaji is an Assistant Professor in the Electrical and Computer Engineering Department at Northeastern University. His research focuses on integrated microsystems with an emphasis on sensing and computation using mechanical waves, acoustic/ultrasound transducers, bio-interfaces, and microcalorimetry. He also applies data-guided methods to nanofabrication process development and semiconductor manufacturing. Dr. Davaji earned his PhD in Electrical and Computer Engineering from Marquette University in 2016 and later served as a post-doctoral associate at Cornell University’s School of Electrical and Computer Engineering.

Peter Doerschuk, PhD
Professor
Cornell Engineering
Peter Doerschuk, PhD
Peter Doerschuk, Professor at Cornell University since 2006, previously served on the Purdue faculty in Electrical and Computer Engineering and Biomedical Engineering. He earned B.S., M.S., and Ph.D. degrees in Electrical Engineering from MIT, an M.D. from Harvard Medical School, and completed training at Brigham and Women’s Hospital and a postdoc at MIT. His research applies computational nonlinear stochastic systems to biology and medicine, spanning viral 3-D structure determination using electron microscopy and x-ray scattering, to nonlinear models of ethanol pharmacokinetics that enable sensor processing, pattern recognition, and individualized physiological analysis.

REGISTER HERE

Webinar: Insights on Spectrum for 6G
2025-11-05 10:00 - 11:00 | Online
About this event
Join Roger Nichols, 6G Program Manager, for an insightful discussion on the 6G spectrum. He will cover the current status of 6G technologies, standards, and policies for the next generation of wireless, including developments from 2024 after the World Radio Conference.

Who should attend this event?
This webinar is for 6G researchers and RF design and development engineers who want to explore the latest developments in 6G technologies, standards, and policies.

Research for 6G currently focuses on legacy and novel frequency spectrums. Besides continued work in spectrum below 7 GHz, the following bands are getting significant attention:

Frequency Range 3 (FR3) from 7 to 24 GHz.
Sub-terahertz bands from 90 to 300 GHz.
Frequency Range 2 (FR2) from 24 to 52 GHz.

Join Keysight’s Roger Nichols for an insightful discussion on these bands, with a special focus on FR3, which gained significant traction in 2024 following the World Radio Conference.

Explore spectrum foundations from a historical perspective.
Review 6G spectrum candidates.
Analyze what makes FR3 popular and challenging.
Evaluate if millimeter wave (mmWave) is still under consideration.

Presenters

Roger Nichols
Keysight Technologies 6G Program Manager
Roger Nichols’ 35 years of engineering and management experience in wireless test and measurement at Hewlett-Packard, Agilent Technologies, and Keysight spans roles in manufacturing, R&D, and marketing. He has managed programs, projects, and departments starting with analog cellular radio, evolving to 5G, and on every standard in between.  He has been directing Keysight’s 5G, and now 6G programs since 2014. He is also directing Keysight’s wireless standards strategies and Keysight’s over-the-air measurement R&D center of excellence.
Roger holds a BSEE from the University of Colorado, Boulder.

REGISTER HERE

Open Lab Day: Power Without Compromise
2025-11-05 09:00 - 14:00 | Keysight Technologies, 5301 Stevens Creek Blvd., Santa Clara, CA, 95051, United States
Power testing is more complex than ever. From subtle low-power signals to multi-kilowatt loads, bulky setups and limited software often slow you down and take up valuable lab space.
At Open Lab Day: Power Without Compromise, you’ll experience what’s next in power testing: faster validation, greater accuracy, and more capability in less space. Keysight’s newest power solutions combine high-density hardware with robust automation software so you can take on your toughest challenges with confidence.
See how to test your toughest power challenges without compromise by leveraging our portfolio of solutions.
Play with Power

Immersive Demo Zones: Explore real-world applications in Battery Test, DC / DC Converters, AI Data Center Power, and the latest Industry Power Trends
AI Acceleration Demos: See how to accelerate AI time-to-market through chipset power rail emulation, data center power interconnect testing, and grid / load emulation for AI server rack performance.
Rapid Insights: Hear four lightning talks and an exclusive NEW PRODUCT REVEAL, packed with ideas you can apply right away.
Memorable Energy: Fuel up with a kW Coffee Bar, energizing food, a Power Playlist and high-energy experiences you won’t forget.
Exclusive First Look: Be among the first to see Keysight’s newest power solutions in action.

Reserve your spot today to experience the future of power without compromise.
REGISTER HERE

Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs
2025-11-05 08:00 - 09:00 | Online
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL/GDS).
Formal check tools are difficult to be analyzed on generated RTL (as the errors cannot be correlated to HLS source code) Catapult Formal/Onespin SystemC help to overcome this challenge. Under HLV there are several apps, to verify and clean C++ HLS code before running HL Synthesis and then apply equivalency between C++ and RTL to guarantee that golden C++ is equivalent with final RTL design.
Under HLV there are 7 apps:

Catapult C Design Checker
Catapult Formal Assert
Catapult CoverCheck
Catapult Formal SLEC
SLEC System
OneSpin SystemC Inspect
C Coverage

Siemens HLV tool offerings offer early bug detection immediately after the HLS code is written, including exhaustive formal analysis, comprehensive simulation-based coverage metrics, allowing faster runtime and iteration loops. These are: Formal autochecks for fully pushbutton formula analysis of the HLS design, a variety of formal-based apps, SVA assertion-based formal verification support, comprehensive simulation coverage metrics, and HLS code to RTL equivalence checking.
What You Will Learn:

How to apply HLV tools for C++/SystemC designs
How to run Siemens HLV tools
How to verify C++ designs before running HLS (clean the code)
Prove equivalency between C++ and generated (or manually written) RTL
Methodologies to apply HLV equivalence checking

Who Should Attend:

Verification engineers that verify HLS designs (Catapult and other HLS tools)
Engineers that verify equivalence of C++ vs RTL
Design & Verification Engineers & Managers

Products Covered:

Catapult Formal, SLEC System and OneSpin SystemC Inspect

REGISTER HERE

Speaker:

Vlada Kalinic
Product Lead for HLV Formal apps, Siemens EDA

Vlada Kalinic is a Product Lead for HLV Formal apps in Siemens, and is involved in the product planning, roadmaps, bringing new tool features and supporting evaluations with the new customers.
Vlada is and experienced engineer that has also another role, as HLV Product Engineer. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Vlada’s career in Siemens is more that 5 years, before Siemens Vlada worked with OneSpin for 6 years and was involved in various successful evaluations with SystemC apps.

REGISTER HERE

Webinar: Imaging Radar for Autonomous Systems: Patent Trends, Key Players & Technology Focus
2025-11-05 08:00 - 08:30 | Online
Details
Imaging radar has rapidly evolved into a critical technology for autonomous systems, with patent activity accelerating significantly over the past decade. From 2015 to 2024, global imaging radar patent publications increased more than tenfold, fueled by the rise of autonomous driving, 4D radar integration, AI-based perception, and sensor fusion. This surge has created an intensely competitive IP landscape, where established OEMs and Tier-1 suppliers are being challenged by new entrants and radar-focused innovators.
In this context, patent landscape analysis provides a powerful complement to market studies, offering deeper insights into global dynamics, IP strategies, and emerging innovation hotspots. It reveals who the leading patent owners are, how their portfolios have evolved over time, and where newcomers are disrupting the field.
Based on our monitoring of imaging radar-related patent activities, this study explores major IP trends by country, the timeline of key players, and segmentation across six application domains (terrestrial, aerial, robotics, space, marine, defense) and five technology layers comprising eleven techniques (FMCW, MIMO, Beamforming, 4D imaging radar, SAR, ISAR, calibration, point cloud, SLAM, tracking, AI and sensor fusion). Particular attention is given to terrestrial applications, including ADAS and higher levels of autonomy, where intensifying competition and strategic IP positioning are defining the evolution of automotive radar.
Please make sure to join the webinar about 10 minutes before the scheduled time so you don’t miss the start.
Speaker

Yanni Zhou
Technology & Patent Analyst
KnowMade
Dr. Yanni Zhou
Yanni works at KnowMade in the field of RF Technologies for Wireless Communications, Sensing, and Imaging. She holds a Ph.D. in RF and Wireless Communication from INSA Lyon, INRIA, and an Engineer’s Degree in Electrical Engineering from INSA Lyon, France. Yanni previously worked at Nokia Bell Labs, Strategy & Technology, focusing on 5G/6G RF front-end systems and advanced sensing technologies. Her expertise also includes the design of radar sensing and imaging systems, enabling precise detection in complex and dynamic environments. She is the inventor of over 20 patents and has authored more than 10 scientific publications in the field.
Contact: yanni.zhou@knowmade.fr
REGISTER HERE

Brooklyn 6G Summit 2025
2025-11-05 - 2025-11-07 | New York University Tandon School of Engineering, New York University Tandon School of Engineering, 6 MetroTech Center, Brooklyn, NY, 11201, United States
What is the Brooklyn 6G Summit
The Brooklyn 6G Summit (B6GS) is a premier event for the global communications industry, bringing together leading voices from technology, business, academia and regulation to shape the future of wireless.
Jointly organized by Nokia and the NYU WIRELESS research center at the NYU Tandon School of Engineering, the Summit has been instrumental in shaping the trajectory of wireless communications since its inception in 2014.
The upcoming 12th edition is scheduled for November 5–7, 2025, at the NYU Tandon School of Engineering. This is a hybrid event.
The live stream takes place on November 6–7, so register to grab your
virtual seat today and join the conversations that will drive the next decade of innovation.
REGISTER HERE

Webinar: Design and Stability Analysis of GaN Power Amplifiers using Advanced Simulation Tools
2025-11-04 10:00 - 11:00 | Online
November 4, 2025 | 10:00 AM PST
This webinar will present advanced simulation tools and techniques for the design of GaN power amplifiers with increased assurance of stable operation that goes beyond simple k-factor analysis. The methods will be demonstrated using Qorvo GaN technology and related non-linear models that have been modified to facilitate advanced stability analysis using the WS-probe in Keysight Technologies’ Advanced Design System software.
Designing stable circuits is becoming harder as communication systems evolve. Instability derives from a combination of gain and feedback. Higher-frequency systems demand faster devices (more gain), while advanced functionality calls for tighter integration (more feedback). In this evolving landscape, traditional techniques are no longer sufficient. But the sheer number of alternative approaches and their perceived complexity leave them unused by many designers. This talk aims to demystify instability so you can design circuits that are actually amplifiers (not oscillators) from the start. We’ll walk through the root causes of instability and the shortcomings of popular RF and Microwave stability analysis techniques. Then, we’ll revisit prior fundamental work to provide, through examples, a simple, reliable process for rigorous stability analysis—enabled by the new WS-Probe simulation tool.
Who should attend this webinar? This Electronic Design Automation (EDA) webinar is ideal for RF and microwave engineers or anyone looking to gain a deeper understanding of amplifier stability and high-frequency circuit design.

Presenters

Matthew Ozalas
Engineer, Scientist at Keysight Technologies.
With an experience of more than 15 years, Matthew brings out a plethora of knowledge in complex RF designs using CAD tools.   Matthew has also authored several application notes on RF and Microwave design and development using Keysight ADS with his recent ones based on “Artificial neural network simulation models for RF power amplifiers” and has produced several tutorials on youtube regarding complex RF designs.
Matt received his BSEE from Penn State University in 2001 and his MSEE and MBA from Arizona State University in 2010. From 2001 to 2005, he worked at the MITRE Corporation in Bedford, MA, as an Integrated Electronics Engineer, designing RFICs and discrete RF and Microwave circuits.  From 2005 to 2013, he worked at Skyworks Solutions in Santa Rosa, CA, designing, developing, and testing high-volume multiband power amplifiers and front-end modules for wireless handsets. He joined Keysight in 2013.

Dr. Larry Dunleavy
President and CEO of Modelithics
Dr. Larry Dunleavy is the President and CEO of Modelithics, Inc. that he co-founded in 2001 to provide standardized highly accurate modeling solutions and measurement services for improved high frequency electronics hardware development for commercial wireless and defense related applications. Since 1990 he has been a faculty member within USF’s Department of Electrical Engineering and helped found the USF Center for Wireless and Microwave Information Systems (WAMI Center). His technical interests include all aspects of measurements and modeling as they related to simulation-based design of microwave and millimeter-wave circuits and systems.

Fouad Boueri
Senior Product Line Manager at Qorvo
With 24 years of diversified experience in the Semiconductors industry, spanning several functions including Product Management, Sales & Marketing, Channel Management, and Engineering Management, Fouad is a Senior Product Line Manager within the Defense & Aerospace business unit at Qorvo, High Power Analog group. The product lines include Discrete Transistors, SSPA Modules, and Filters.
Fouad holds a MS EE from the University of Michigan at Ann Arbor and an MBA from UCLA’s Anderson School of Management.

REGISTER HERE

Embedded World North America 2025
2025-11-04 - 2025-11-06 | Anaheim, CA, Anaheim, CA, United States
Connect to the embedded community
With its 20 years of history and experience in Europe, embedded world is the most professional and largest exhibition in its field, and has accumulated substantial industry and customer data and media resources. It gathers the leading enterprises of the global embedded industry, with its application range covering automotive electronics, AI, industrial control, IoT and medical industry. Building upon this success, embedded world North America is the perfect choice to source demanded products, and providing further opportunities for upgrade-in-products and boost-in-technologies.
REGISTER HERE

PIC Summit Europe 2025
2025-11-04 - 2025-11-05 | Evoluon, Eindhoven, Evoluon, Noord Brabantlaan 1A, Eindhoven, LA, 5652, Netherlands
Scaling Together in a Dynamic World
The photonic chip industry is reaching new heights – but scaling production, applications, and investments requires a united effort. As demand surges for high-speed, energy-efficient solutions, the question isn’t if photonic chips will revolutionise industries, but how fast we can make it happen.
At PIC Summit Europe 2025, we bring together an entire ecosystem of designers, foundries, integrators, OEMs, investors, and thought leaders – to tackle the industry’s biggest challenges and opportunities. From advancing manufacturing capacity to expanding market applications and securing funding for growth, this event is where the photonic chip industry aligns its vision for the future.
Why Attend?

Insights straight from the source – Get the latest insights on market and technology developments, helping you navigate the future of PICs with confidence.
Discover real-world applications – Learn which applications are proving most successful, and where the next big opportunities in photonics lie.
Meet key stakeholders – Connect with the most influential players in the industry, from technology leaders to business innovators and investors.
Shape the future of PICs – Gain direction on how to scale your business and technology while aligning with industry-wide efforts. Unlock collaboration opportunities – Whether you’re looking for investment, partnerships, or technical cooperation, this is the place to make it happen.

REGISTER HERE

Webinar: Advanced Packaging and Material Characterization for Microelectronics: SEMI Training
2025-11-03 08:30 - 17:00 | Online
Strengthen your knowledge and skills by learning about new packaging technologies in Fan-in, Fan-out WLP, Embedded packaging technology, System on Chip (SOC), System in Package (SiP), 3D IC, WLP, TSV, etc. Packaging knowledge is a must for professionals in the semiconductor industry. The first part of this course dives deep into advanced packaging. Part 2 of this course focuses on the design in electrical and thermal which are used to enhance the electrical, thermal, and reliability performance of the package.

Pricing

Members: $599
Non-Members: $649

* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact semiu-support@semi.org.
REGISTER HERE

Semitracks Course: Wafer Fab Processing
2025-11-03 - 2025-11-06 | Phoenix, AZ, Phoenix, AZ, United States
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is a 4-day course that offers an in-depth look into the semiconductor manufacturing process, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique, and we delve into the current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.
By focusing on the basics of each processing step and the issues surrounding them, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about the semiconductor industry. This skill-building series is divided into three segments:

Basic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. Participants will learn the fundamentals of each processing step and why they are used in the industry today.
The Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants will learn how each technique has evolved for use in previous and current generation ICs.
Current Issues in Wafer Fab Processing. Participants will learn how many processing steps are increasingly constrained by physics and materials science. They will also learn about the impact of using new materials in the fabrication process, and how those materials may create problems for the manufacturers in the future.

This course is a must for every manager, engineer, and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

Course Objectives

This course will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.
Participants will understand the basic concepts behind the fundamental wafer fab processing steps.
This course will identify the key issues related to each of the processing techniques, and their impact on the continued scaling of the semiconductor industry.
This course will offer a wide variety of sample problems that participants will work to help them gain knowledge of the fundamentals of wafer fab processing.
Participants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition, ion implantation, lithography, and etching.
Participants will understand how processing, reliability, power consumption and device performance are interrelated.
Participants will be able to make decisions about how to construct and evaluate processing steps for CMOS, BiCMOS, and bipolar technologies.

REGISTER HERE

Webinar: 5 Expectations for the Memory Market in 2026
2025-10-29 11:00 - 12:00 | Online
October 29, 2025 – 11:00 AM EST
October 30, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026
AI workloads, HBM4 adoption, and 3D NAND scaling—what’s next for the memory industry in 2026.
The memory semiconductor industry is entering a critical inflection point. Explosive AI workloads are pushing traditional architectures beyond their limits, creating both breakthrough opportunities and severe supply constraints across the DRAM and NAND markets.
By 2026, the next wave of memory innovation will determine which companies lead in performance and profitability—and which fall behind. From HBM4 and FinFET base dies to 3D NAND scaling with hybrid bonding, technology and market shifts are reshaping the competitive landscape.
In this live TechInsights webinar, our experts will explore five expectations shaping the memory markets in 2026, highlighting the implications for leading players and global strategies.
Key Topics You’ll Learn

Samsung’s D1c HBM4 adoption – 16Hi stacks with 1.5 TB/s bandwidth.
Foundry FinFET base dies – TSMC and the evolution of HBM integration.
KIOXIA’s HBF potential – A high-bandwidth Flash alternative for edge AI.
3D NAND scaling – 300+ layers, hybrid bonding, molybdenum wordlines, and stairless contacts.
Market & geopolitical dynamics – Revenue acceleration and U.S. export controls impacting YMTC, CXMT, and JHICC.

REGISTER HERE

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration
2025-10-29 11:00 - 12:00 | Online
Description
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to learn about network time synchronization, publisher-subscriber communication, and time-aware shaping for TSN traffic using Wireshark. By the end, you’ll be equipped to effectively utilize the AMD Kria SOM’s configurability for innovative designs. This interactive session is ideal for developers aiming to deepen their TSN knowledge and streamline their workflows.
This webinar includes a live demonstration and Q&A.
If you are unable to attend, a recording will be sent one week after the live event.
To see our complete list of webinars, visit our website: www.bltinc.com.
REGISTER HERE

Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System
2025-10-29 09:00 - 10:00 | Online
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines machine learning, reinforcement learning, generative, and agentic AI across the entire EDA workflow. This session showcases how Siemens is realizing this vision in the RTL-to-GDS space with the newly launched Aprisa AI: a fully integrated, AI-powered solution working in concert with the Siemens EDA AI System.
Aprisa AI delivers a 10x boost in engineering productivity, a 3x compute-time efficiency improvement, and 10% better PPA results compared to conventional workflows. Aprisa AI intelligently optimizes digital implementation flows to provide the best PPA for any given design. It also includes a generative and agentic AI assistant capable of answering questions about documentation and designs, launching commands, and running tools within Aprisa. This assistant is powered by the Siemens EDA AI System—an open, customizable, and secure platform that extends agentic AI capabilities across the entire EDA workflow. The system is designed to increase overall chip designer productivity through agentic automation, smart design queries, accelerated learning, and unlocking valuable insights from a centralized multimodal EDA data lake.
What you will learn:

Powerful AI/ ML digital implementation features like Aprisa’s design explorer for rapid and intelligent exploration of the design space
The role of machine learning, reinforcement learning, generative AI, and AI agents, in automating and scaling RTL-to-GDS methodologies
How the Siemens EDA AI system helps accelerate learning, performing EDA workflows, and more

Topics include:

An Introduction to Aprisa AI and the Siemens EDA AI System.
Overview of different features and workflows of Aprisa AI
Insightful demonstrations of Aprisa AI and Siemens EDA AI system
Summary & Q&A

Products Featured:

Aprisa AI
Siemens EDA AI System

Speakers:

Janet Attar
Principal Product Manager, Aprisa, Siemens EDA

Janet Attar is Principal Product Manager at Siemens EDA for the Aprisa RTL-to-GDS digital implementation solution, including responsibility for Aprisa AI planning and development. Prior to Siemens, she was a Staff Applications Engineer at Cadence, where she worked with customers to develop silicon chips for consumer electronics, and a Senior Physical Design Engineer for International Rectifier (now Infineon) where she worked on digital controllers. Janet holds a B.Eng in Electrical Engineering from Carleton University.

Niranjan Sitapure, PhD
Central AI Product Manager, Siemens EDA, Siemens EDA

Niranjan Sitapure, PhD, is the Central AI Product Manager at Siemens EDA. He oversees road mapping, development, strategic AI initiatives, and product marketing for the Siemens EDA AI portfolio. With a PhD in Engineering from Texas A&M University, Niranjan has honed his expertise in advanced AI/ML technologies, including time-series transformers, LLMs, and digital twins for engineering applications. Previously, Niranjan was a consultant at Bain & Company, where he advised Fortune 500 clients on digitization strategies, operating model redesigns, and due diligence.

REGISTER HERE

CadenceCONNECT: Jasper User Group 2025
2025-10-29 - 2025-10-30 | San Jose Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The Jasper User Group Conference is the premier industry event for formal experts and beginners alike to learn from each other how to effectively accelerate their design and validation processes by applying formal methods.

Conference Highlights

User presentations on core technologies, applications, and flows
– Roadmap discussions
– New technology demos
– Executive keynotes

REGISTER HERE

Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis
2025-10-28 09:00 - 10:00 | Online
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL, and performing verification. An agile workflow requires being able to iterate through the architecture and implementation phases quickly to converge towards an efficient design. This is especially true for designing low footprint hardware accelerators on FPGAs, where architectural choices directly impact resource fit feasibility and performance.
Join us as we discuss architectural and microarchitectural design space exploration focusing on the SoftMax function—a key component in many neural networks. We showcase how SoftMax can be targeted on FPGA, balancing performance within tight area and resource budgets for edge deployments. We will use Catapult High-Level Synthesis as we discover its capabilities for data path-oriented hardware designs encountered in vision systems and edge inference engines.

Speakers:

Shreedutt Hedge
Senior ML RTL Engineer, Lattice Semiconductor

Technical lead on the FPGA acceleration of SensAI ML solution stack. Designing accelerated ML pipelines for low power edge devices, with focus on low resource footprint. Lead accelerator architecture study, own and develop RTL microarchitecture for implementing ML operators as soft logic in FPGA.
Work with the compiler team to support YOLO series CNN model on the accelerator.

Cameron Villone
High-Level Synthesis Technologist, Siemens EDA

Cameron Villone is a High-Level Synthesis Technologist working with the Catapult High-Level Synthesis product management and marketing team, focusing on AI hardware deployment. He previously worked as a product marketing engineer for PowerPro, Siemens’ power optimization and analysis product. He held previous roles at Texas Instruments and General Motors. Cameron studied and graduated from Rochester Institute of Technology, obtaining both a bachelor’s and master’s degree in electrical engineering, focusing on Robotics, Embedded Systems, and Computer Vision.

Sivasankar Palaniappan
High-Level Synthesis Technologist, Siemens EDA

Sivasankar currently works as a High-Level Synthesis Technologist in the Marketing division of the Catapult team. He joined Siemens in July 2020 as an Associate Rotation Engineer and migrated to the new role a year later. Sivasankar has a MS in Electrical and Computer Engineering, focusing on Computer Engineering from University of California San Diego.

REGISTER HERE

ICCAD 2025
2025-10-26 - 2025-10-30 | Munich, Germany, Munich, Germany
The 2025 International Conference on Computer-Aided Design

Call For Papers

Jointly sponsored by IEEE and ACM, IEEE ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. IEEE ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. IEEE ICCAD has a long-standing tradition of producing cutting-edge, innovative technical program for attendees.

REGISTER HERE

2025 TSMC Open Innovation Platform Ecosystem Forum - Tokyo
2025-10-24 | Grand Hyatt Tokyo, 6 Chome-10-3 Roppongi, Minato City, Tokyo, 106-0032, Japan
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM
Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event; it’s a dynamic hub where the brightest minds converge to ignite the next wave of innovation.
As the AI revolution proliferates from the data center to the edge and becomes integrated into every application, the need for high-performance and energy-efficient designs is becoming paramount. Through a series of compelling, multi-track presentations, you’ll gain a firsthand understanding of how the ecosystem is collaboratively tackling these critical design requirements.
AI is also transforming how chip and multi-die designs are done. This year, the forum will highlight how the ecosystem is harnessing the immense potential of AI in next generation of design solutions for TSMC’s advanced process and packaging technologies. Prepare to be immersed in a wealth of knowledge as industry trailblazers and TSMC’s ecosystem partners offer valuable insights into the latest breakthroughs.
The event provides a unique opportunity for you to engage with thought leaders and innovators, whether you join in-person at locations across North America, Japan, Taiwan, China, and Europe, or participate online.
Don’t miss this opportunity to connect with the leading players of semiconductor technology and be part of shaping tomorrow’s innovations, today!
Opportunity to gain insights into

Solutions needed to address energy efficiency and other challenges impacting the next-generation AI chips and corresponding design flows and methodologies for TSMC A16™, N2, and N3 processes
Consistent progress in design enablement and solution development for TSMC’s advanced processes including A14, TSMC A16™ and N2
Latest advancements in design solutions on TSMC 3DFabric® chip stacking (including InFO, CoWoS®, TSMC-SoIC®, TSMC-SoW™), as well as updates on the TSMC 3DFabric Alliance
AI-assisted design flows for 2D and 3DIC design productivity and optimization
Design enablement technologies, IPs, and solutions targeting the latest HPC, AI/ML, automotive, mobile/5G and IoT applications
Comprehensive design solutions for specialty technologies including ultra-low power, ultra-low voltage, analog migration, RF, and mmWave
Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market

REGISTER HERE

Webinar: IP Design Considerations for Real-Time Edge AI Systems
2025-10-23 10:00 - 11:00 | Online
*Work Email Required*
Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support real-time AI workloads at the edge. We’ll cover:
• Memory and compute efficiency: Techniques for optimizing on-chip memory architectures and compute pipelines to deliver high throughput and low energy consumption.
• Low-latency inference: Design considerations to meet stringent latency targets through local processing and effective dataflow management.
• Power and area optimization: Strategies for balancing compute capability with ultra-low power operation and minimal silicon area.
• Multi-die considerations: Ways to approach multi-die design for advanced Edge AI applications.
• IP risk mitigation and integration: Best practices for modular, verifiable IP reuse that accelerates first-silicon success and manages integration risk.
• Evolving Edge AI requirements: Insights into how emerging architectures are shaping IP trends enabling smarter, adaptive edge devices.

Attendees will gain a detailed understanding of how IP selection, memory/compute co-design, and hardware optimization directly impact the scalability, reliability, and deployment speed of next-generation Edge AI solutions.
Speaker: Hezi Saar is a senior director of product line management for mobile, automotive, and consumer IP for the Synopsys Solutions Group. He brings more than 20 years of experience in the semiconductor and embedded systems industries.
*This webinar is in partnership with Synopsys and SemiWiki*
REGISTER HERE

EU Chips Act 2.0 Webinar
2025-10-23 | Online
Europe’s Role & Chips Act 2.0 Priorities

The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative to strengthen the European semiconductor ecosystem.
Building on the original Chips Act adopted in 2023, this updated framework aims to address emerging technologies such as Artificial Intelligence, supply chain needs, and geopolitical challenges while fostering innovation, research, and production capacity within Europe, as well as support to start-ups in order to foster scaling-up.
As GSA encompasses the entire semiconductor value chain, its members are optimally positioned to understand the ecosystem needs to evolve and grow.
In this webinar, we will present the main objectives, challenges and opportunities of this EU effort, very timely in these challenging times.

REGISTER HERE

Webinar: 5 Expectations for the Power Market in 2026
2025-10-22 11:00 - 12:00 | Online
October 22, 2025 – 11:00 AM EST
October 23, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Power Market Trends Reshaping Semiconductors in 2026
Wide-bandgap disruption, PMIC innovation, and datacenter power demand, what’s next for power semiconductors.
The rise of AI datacenters is driving unprecedented demand for power, creating both massive opportunities and major challenges for the power semiconductor industry. As computing power doubles nearly every six months, new technologies and global competition are reshaping the market faster than ever.
By 2026, datacenter power conversion markets are projected to reach nearly $4 billion, while silicon carbide (SiC) oversupply and intensifying Chinese competition will redefine strategies for global players. At the same time, the GaN industry faces transformation with TSMC’s exit, opening the door for new foundry opportunities, while China accelerates its self-sufficiency goals for wide-bandgap technologies by 2027.
In this live TechInsights webinar, our experts will break down five key developments that will define who leads, and who falls behind in the next two years.
Key Topics You’ll Learn

Datacenter power conversion – $4B market growth by 2026 as AI accelerates.
SiC oversupply & Chinese competition – How strategies must adapt.
The GaN transition – TSMC exits, new foundry opportunities emerge.
China’s wide-bandgap drive – Strategic self-sufficiency by 2027.
PMIC evolution – Higher integration, intelligence, and co-design.

REGISTER HERE

Achieving Timing Closure in FPGA Designs Workshop
2025-10-22 10:00 - 15:00 | Online
Achieving Timing Closure in FPGA Designs Workshop
Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure.
Gain hands-on experience with timing closure techniques and learn strategies to improve design performance and meet timing requirements efficiently.
Gain experience with:

Understanding basic Static Timing Analysis (STA)
Reading timing report
Applying techniques to reduce delay and to improve clock skew and clock uncertainty
Resolving timing violations
Using the Timing Constraints Wizard

This course focuses on the UltraScale, UltraScale+ and Versal architectures.
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
REGISTER HERE

Webinar: Pushing more power with CoolGaN™: design, layout and thermal management
2025-10-22 09:00 - 10:00 | Online
Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST

Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems.
You will gain a deep understanding of gate drive circuit design, layout steps, and thermal management guidelines for GaN transistors and applications in high-switching frequency topologies.
Attending the webinar will help you gain a deeper understanding of the design principles and best practices for working with GaN power devices. You will learn how to design and optimize gate drive circuits for GaN power applications, including the selection of suitable components. In addition to gate drive circuit design, the webinar will also cover the essential layout steps for maximizing GaN design performance. You will learn how to create a layout that minimizes parasitic inductance and capacitance, and how to optimize the placement of components to ensure optimal thermal performance.
The webinar will provide essential thermal management guidelines for GaN transistors and their applications in high-switching frequency topologies to achieve the highest efficiency.

You will learn about:

How to design and optimize gate drive circuits for Gallium Nitride (GaN) power applications
Layout steps for maximizing GaN design performance
Essentials of thermal management guidelines.

REGISTER HERE

CadenceCONNECT: Photonics and Quantum Technologies
2025-10-22 - 2025-10-23 | San Jose, CA
Event Summary

The year 2025 is both a turning point for integrated photonics as a key enabler for AI, physical and infrastructure interconnect, and the International Year of Quantum (IYQ). In our event, we are going to explore the enabling technologies shared by these two exciting fields. While these systems need to exist in a broader ecosystem, we will focus on the technologies required to enable the creation and analysis of the devices, the ICs, and the full system.
Join Cadence for one or both days of the 9th annual CadenceCONNECT photonics event and workshop on October 22-23 in San Jose, California. On day one, we’re featuring presentations from industry and academic experts, and on day two, you will have the opportunity to learn hands-on with photonics experts.
Who should attend?
– Photonics and quantum IC designers and architects
– Photonics and quantum design project leads
– Photonics and quantum design managers
– CAD and PDK managers
Don’t miss this opportunity to learn about solutions for your design challenges and network with other expert users during lunch and social hours.
Seating is limited. If you register and are unable to attend, please let us know.
Agenda at-a-Glance
*Subject to change
Day 1: October 22, in-person and virtual
8:30-9:00am – Registration, light breakfast
9:00-5:00pm – Sessions/Lunch/Breaks
5:00 – 7:00pm – Reception
Day 2: October 22, in-person only
8:30-9:00am – Registration, light breakfast
9:00-5:00pm – Workshop/Lunch/Breaks
Bring your laptops
REGISTER HERE

RISC-V Summit North America 2025
2025-10-22 - 2025-10-23 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive, data center, space, IoT, embedded and more. Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly, enjoy a new level of design freedom, and substantially reduce the cost of innovation. Anyone, anywhere can benefit from these contributions.

This October, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies, as well as to network and build relationships. Come be part of the RISC-V movement.

The festivities kick off with RISC-V Member Day, where technical and industry working groups meet in person to share updates on the status of various efforts.
Next, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions, paired with an expo featuring dozens of community members showcasing their the latest solutions.

It’s community-curated content, research and innovation driving the next wave of growth for RISC-V.
Learn about software, systems, development tools, security, the latest use cases in key markets and more. It’s all here.
Define the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us!
REGISTER HERE

Semiconductor Traceability and Provenance Workshop
2025-10-21 08:30 - 17:00 | NIST Gaithersburg, NIST Gaithersburg, 100 Bureau Drive, Gaithersburg, MD, 20899, United States
The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday, October 21, 2025, at its campus in Gaithersburg, Maryland. This in-person, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain, which identified traceability as the top priority of semiconductor industry stakeholders.
As semiconductor devices grow more complex and globally distributed, the risks from counterfeit components, malicious tampering, and opaque sourcing threaten the security, reliability, and resilience of critical systems. Strengthening traceability and provenance is essential to mitigating supply chain threats, supporting national security imperatives, and addressing the grand challenges in secure microelectronics (https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000.pdf).
The workshop will convene technical leaders across the semiconductor ecosystem (e.g., hyperscalers, auto and semiconductor companies, federal agencies, academia) to address the practical challenges and opportunities for implementing traceability in semiconductor chips. This one-day event will feature plenary, panel, and interactive breakout sessions. Participants will be encouraged to collaborate and discuss key questions and topics that will identify short-term (<1 year) and longer-term (2028-2029 time frame) activities related to semiconductor traceability and provenance. The topics that will be considered include but are not limited to:

Existing solutions
Technical, operational challenges to traceability adoption
Opportunities for public-private collaboration (e.g., hyperscalers, automobile,
semiconductor companies, government agencies, academia)
Roadblocks to alignment and paths to overcoming them
Economic drivers and pilot use cases for traceability
Frameworks for joint standards development and implementation
Roadmap for collaboration and path to success

Outcomes from the workshop will include a published roadmap and post-workshop report that advances shared goals in securing semiconductor supply chains.
REGISTER HERE

SPIE Optifab 2025
2025-10-20 - 2025-10-23 | Joseph A. Floreano Rochester Riverside Convention Center, Joseph A. Floreano Rochester Riverside Convention Center, 123 East Main Street, Rochester, NY, 14604, United States
Join colleagues at the largest optical manufacturing conference and exhibition in North America

SPIE Optifab is the premier event to meet with top companies and learn about the latest optical fabrication technologies. Organized jointly by SPIE and APOMA, Optifab is the largest optical manufacturing conference and exhibition held in North America.
In 2025 the meeting will be co-located with SPIE Laser Damage in Rochester, New York.
Enjoy four days of connecting with your community

Meet suppliers at the exhibition
Hear technical presentations
Enjoy invited speakers
Get training while onsite
Enjoy networking events

We look forward to gathering these two important communities in one location.
Exhibition: 21 – 23 October 2025
Technical program: 20 – 23 October 2025

REGISTER HERE

MICRO 2025 - 58th IEEE/ACM International Symposium on Microarchitecture
2025-10-18 - 2025-10-22 | Seoul, Korea, Seoul, Korea, Republic of
The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and we aim to continue this tradition at MICRO-58. In 2025, MICRO goes to Seoul, Korea.
REGISTER HERE

2025 Embedded World China
2025-10-16 - 2025-10-17 | Shanghai World Expo Exhibition and Convention Center China, 1099 Guozhan Rd, Shanghai, Pudong, 200126
Conference Profile
The embedded world China Conference will take place on October 16 and 17, 2025 at the Shanghai World Expo Exhibition and Convention Centre.
The main topics of this year’s conference are：
· Embedded Technology & Applications
· Vehicle Electronic / Electrical Architecture & Technologies
· Embedded Vision Technologies Innovation and Development Conference using Edge AI
Check the Conference brochure here.
Interested speakers for all three tracks are invited to submit their proposals to contribute to the 3rd edition of the conference with a technical presentation or paper. The embedded world China Conference 2025 calls for future-oriented technologies and solutions, best practices, new ideas and smart concepts for efficient development and lifecycle processes. The presentations will be used to initiate discussions and help other engineers and managers to benefit from shared experiences.
Experts with insight into the embedded systems industry is given an equal opportunity to participate, whether through in-depth academic discussions, technological show cases or best practice studies from research and development.
Acceptance Criteria
Papers will be selected based on the following criteria:
· novelty
· technological soundness
· technological significance
· experience of the speaker
The selection will be made by a programme committee. The members of the programme committee are independent senior engineers and researchers with excellent scientific and business experience.
REGISTER HERE

Webinar: ML-Enhanced TCAD Calibration With 10x Reduction in Time to Results
2025-10-15 17:00 - 18:00 | Online
Date: Oct 15, 2025 | 5:00 PM PST

Featured Speakers:

Saurabh Suryavanshi, Product Manager, Synopsys
Youngkwon Cho, Senior Staff Engineer, Synopsys
Dipanjan Basu, Principal Engineer, Synopsys

Calibration is an essential part of enabling TCAD products usages inside Semiconductor fab. Synopsys has been leading the development of ML-enhanced calibration that reduce the time to results by 10x while improve the quality of results. In this Synopsys Webinar, our team will provide overview of TCAD calibration and recent advances in ML-based calibration.
Why You Should Attend:

Cut TCAD calibration time and accelerate project delivery by 10x.
Overcome accuracy challenges in semiconductor manufacturing.
Streamline calibration workflows for better efficiency.

REGISTER HERE

Featured Speakers

Saurabh Suryavanshi
Product Manager, Synopsys
Saurabh is a Product Manager in the Manufacturing Solutions group at Synopsys, specializing in Digital Twin, machine learning, and GenAI technologies to accelerate semiconductor innovation. He holds a PhD in Electrical Engineering from Stanford University. Saurabh is a recognized expert with over 30 publications, multiple patents, and a strong track record of helping engineers improve productivity and reduce R&D costs.

Youngkwon Cho
Senior Staff Engineer, Synopsys
Youngkwon Cho is a Senior Staff Engineer at Synopsys, leading development of machine learning-based calibration solutions for TCAD simulation. He holds a PhD in applied physics from Ajou University and has deep expertise in optical simulation, process optimization, and AI/ML tools.

Dipanjan Basu
Principal Engineer, Synopsys
Dipanjan is a technology evangelist dedicated to enhancing semiconductor manufacturing productivity through modeling and simulation. He has extensive experience in device physics, compact modeling, and quantum transport simulation, and leads initiatives to accelerate technology development using TCAD and DTCO strategies.

REGISTER HERE
