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DTSTART;TZID=America/Los_Angeles:20260203T090000
DTEND;TZID=America/Los_Angeles:20260203T100000
DTSTAMP:20260424T021140
CREATED:20260114T022128Z
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SUMMARY:Webinar: From C++ to Silicon: Fast\, Physically Aware\, AI-Driven Exploration with Rise Design Automation and Precision Innovations
DESCRIPTION:As hardware designs grow more complex\, architectural exploration is increasingly critical to delivering differentiated silicon. Teams frequently develop promising architectures only to discover late in the cycle that physical implementation is too costly or fails to meet key specifications. This challenge intensifies as designers integrate new accelerators — video\, audio\, ML\, or custom datapaths — rapidly expanding the search space. \nAI-based automation can help\, but only when each exploration trial provides cost metrics (area\, timing\, power) that are both fast and credible. Traditional parameter sweeps are slow. Full physical analysis is expensive. And without correlation to real implementation costs\, AI-guided exploration can simply produce the wrong answers faster. \nRise Design Automation and Precision Innovations are partnering to change this dynamic. Together\, they deliver fast\, accurate\, physically aware exploration loops — ideal for reinforcement learning\, iterative refinement\, and high-volume experimentation. \nRise Design Automation provides 10× faster High-Level Synthesis (HLS) with timing and area correlation within a few percent of downstream RTL-synthesis results. The Rise toolchain can also execute downstream tools “under the hood” and incorporate their feedback directly into HLS. Integrating Precision Innovations’ industry ready OpenROAD-based RTL→GDSII flow and OpenROAD Flow Scripts adds production-grade physical estimation with strong area and timing accuracy validated down to advanced nodes (including 2–3nm). \nCombined\, this integrated flow enables rapid exploration from high-level C++/SystemC/SystemVerilog through synthesized RTL to physically correlated PPA — supporting hundreds or thousands of trials without licensing barriers. \nThis session demonstrates how an integrated\, AI-driven architectural exploration solution from Rise Design Automation and Precision Innovations provides rapid\, actionable feedback to guide design decisions\, and how you benefit from these capabilities in your own design flow. \n\n\n\n\n\n\n\n\nWhat You’ll Learn\n\n\n\n\nIn this technical deep dive\, you’ll see how Rise Design Automation and Precision Innovations help you: \n\nRun AI-guided architectural exploration with fast\, physically grounded cost metrics\nModel and explore designs in C++\, SystemC\, or SystemVerilog and automatically generate multiple RTL variants\nUse Rise’s fast\, correlated HLS engine to accelerate exploration with credible RTL-level PPA\nLeverage Precision’s OpenROAD-based RTL→GDSII flow for production-grade physical estimation — enabling early visibility into area\, timing\, and implementation feasibility\nApply reinforcement learning and design agents to guide the search toward optimal architectures\nScale exploration across hundreds or thousands of trials without restrictive per-run licensing\n\nThis webinar highlights practical techniques to accelerate exploration\, increase confidence\, and improve architectural decisions earlier in the design process. \n\n\n\n\nLive Demonstration\n\n\n\n\nSee a complete exploration loop from high-level behavioral model through Rise Design Automation’s HLS\, through RTL synthesis\, and into Precision Innovations’ OpenROAD-based physical estimator — with AI-guided refinement driven by real PPA feedback \n\n\n\n\nWho Should Attend:\n\n\n\n\nHardware architects\, design engineers\, verification leads\, and research teams who want to: \n\nAccelerate architectural exploration for complex accelerators\nApply AI/ML or reinforcement-learning workflows to silicon design\nImprove correlation between high-level design\, RTL\, and physical estimates\nConfidently explore many architectural options without slow iteration loops\nShift verification and physical awareness earlier in the flow\nDeploy scalable exploration without restrictive per-run licensing\n\nWhether you’re adding a new accelerator to an SoC or exploring ML-driven design automation\, this session provides a practical foundation for leveraging Rise + Precision. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-from-c-to-silicon-fast-physically-aware-ai-driven-exploration-with-rise-design-automation-and-precision-innovations/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-13-181938.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260128T100000
DTEND;TZID=America/Los_Angeles:20260128T110000
DTSTAMP:20260424T021140
CREATED:20251211T205410Z
LAST-MODIFIED:20251211T205410Z
UID:364596-1769594400-1769598000@semiwiki.com
SUMMARY:Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
DESCRIPTION:In this webinar\, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks. \nWe will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout. \nWe will show you how these tools work on real designs as well. \nWHO SHOULD ATTEND THIS WEBINAR?\nIf you are designing chips to deploy in networked environments\, you need to understand the risks ahead and how to minimize them. \nIf you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions. \nSPEAKERS\nBeau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies \nDr. Paul Calzada will take you through a live demonstration of CODAx\, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions. \n* This webinar is in partnership with SemiWiki and Caspia Technologies \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-why-ai-assisted-security-verification-for-chip-design-is-so-important/
LOCATION:Online
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260128T090000
DTEND;TZID=America/Los_Angeles:20260128T170000
DTSTAMP:20260424T021140
CREATED:20260113T042846Z
LAST-MODIFIED:20260113T042846Z
UID:365659-1769590800-1769619600@semiwiki.com
SUMMARY:Power Seminar - Burnaby
DESCRIPTION:About this event\nAs power levels rise and systems scale\, high-power testing becomes more complex and time-consuming. This hands-on Power Solutions Seminar focuses on practical test strategies for batteries\, fuel cells\, green energy\, and power conversion. \nYou will experience expert-led technical sessions with hands-on\, real-world application insights. Explore Keysight’s three new High-Power ATE System Supplies and demos across our power portfolio to improve test efficiency\, accuracy\, and development speed. \n\n\n\n\n\n\n\nWho should attend this event?\nThis event is designed for development engineers in power electronics\, battery systems\, and green energy. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/power-seminar-burnaby/
LOCATION:Burnaby\, BC\, Burnaby\, British Columbia\, Canada
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-202823.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260128
DTEND;VALUE=DATE:20260129
DTSTAMP:20260424T021140
CREATED:20260113T043124Z
LAST-MODIFIED:20260113T043124Z
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SUMMARY:Webinar: Powering the Future: Megawatt Charging Solutions for Heavy-Duty Electrification
DESCRIPTION:About this event\nJoin our upcoming webinar to discover how Keysight is powering the future of heavy-duty electric transportation with advanced megawatt-charging test solutions. \nLearn how to validate ultra-high-power delivery beyond 3 MW\, ensure compliance with MCS and ISO 15118-20\, and streamline interoperability testing\, all within a single\, fully controllable platform designed for both compliance and development debugging. \nWe’ll explore how seamless integration of software\, hardware\, and project services accelerates the deployment of safe\, scalable\, and standards-driven charging infrastructure for trucks\, ships\, and heavy machinery. \n\n\n\n\n\n\n\nWho should attend this event?\nThose involved in the shift towards a future-proven transportation\, logistics\, and construction ecosystem. Specific titles: OEM Electrification Leaders; EVSE Manufacturers & Charging Infrastructure Developers; Compliance & Standards Specialists; Fleet Electrification Managers: Grid Integration & Energy Management Specialists. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-powering-the-future-megawatt-charging-solutions-for-heavy-duty-electrification/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203022.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260127T090000
DTEND;TZID=America/Los_Angeles:20260127T100000
DTSTAMP:20260424T021140
CREATED:20251217T021629Z
LAST-MODIFIED:20251217T021629Z
UID:364770-1769504400-1769508000@semiwiki.com
SUMMARY:Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)
DESCRIPTION:Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process\, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process. \nWhat you will learn \n\nThe breadth of the entire Gencellicon portfolio\nHow timing closure solutions can alleviate your design process using Siemens tools\n\nWho should attend \n\nImplementation engineers\nSoC architects\nDesign Verification teams\nTest engineers\nPower architects\nPhysical designers\n\n\n\n\nSpeaker: \n\n\n\n\nHimanshu Bhatnagar \nSenior Director\, Siemens EDA \n\n\n\nHimanshu brings over 20 years of expertise in chip design\, having developed complex SoCs across networking\, communications\, imaging\, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis\, a practical guide to synthesis and static timing analysis. Before founding Excellicon\, now Gencellicon\, Himanshu held key positions at leading semiconductor companies\, including Mindspeed Technologies\, Conexant Systems\, and ST Microelectronics. At Conexant Systems\, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally\, Himanshu has served as an advisor to various EDA companies. \n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-solving-timing-closure-challenges-using-gencellicon-previously-excellicon/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-16-181547.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260127T083000
DTEND;TZID=America/Los_Angeles:20260127T170000
DTSTAMP:20260424T021140
CREATED:20260107T031557Z
LAST-MODIFIED:20260107T031557Z
UID:365310-1769502600-1769533200@semiwiki.com
SUMMARY:Semiconductor Traceability and Provenance Workshop
DESCRIPTION:The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday\, January 27\, 2026\, at the NIST National Cybersecurity Center of Excellence (NCCoE) conference facility\, in Rockville\, Maryland. This in-person\, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain\, which identified traceability as the top priority of semiconductor industry stakeholders. \nAs semiconductor devices grow more complex and globally distributed\, the risks from counterfeit components\, malicious tampering\, and opaque sourcing threaten the security\, reliability\, and resilience of critical systems. Strengthening traceability and provenance is essential to mitigating supply chain threats\, supporting national security imperatives\, and addressing the grand challenges in secure microelectronics (https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000.pdf). \nThe workshop will convene technical leaders across the semiconductor ecosystem (e.g.\, hyperscalers\, auto and semiconductor companies\, federal agencies\, academia) to address the practical challenges and opportunities for implementing traceability in semiconductor chips. This one-day event will feature plenary\, panel\, and interactive breakout sessions. Participants will be encouraged to collaborate and discuss key questions and topics that will identify short-term (<1 year) and longer-term (2028-2029 time frame) activities related to semiconductor traceability and provenance. The topics that will be considered include but are not limited to: \n\nExisting solutions\nTechnical\, operational challenges to traceability adoption\nOpportunities for public-private collaboration (e.g.\, hyperscalers\, automobile\,\nsemiconductor companies\, government agencies\, academia)\nRoadblocks to alignment and paths to overcoming them\nEconomic drivers and pilot use cases for traceability\nFrameworks for joint standards development and implementation\nRoadmap for collaboration and path to success\n\n\nOutcomes from the workshop will include a published roadmap and post-workshop report that advances shared goals in securing semiconductor supply chains. \nRegistration Info\nThe registration fee for this event is $97.00 and includes AM/PM breaks and lunch. \nRegistration closes on Tuesday\, January 20\, 2026. \nRegistration Contact for Additional Information or Questions:\nCarol L. Shibley\ncarol.shibley@nist.gov\n(301) 975-8302 \nTECHNICAL CONTACT:\nKostas Amberiadis\nkostas.amberiadis@nist.gov \nREGISTER HERE
URL:https://semiwiki.com/event/semiconductor-traceability-and-provenance-workshop-2/
LOCATION:NIST’s National Cybersecurity Center of Excellence (NCCoE)\, 9700 Great Seneca Highway\, Rockville\, MD\, 20850\, United States
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260122
DTEND;VALUE=DATE:20260124
DTSTAMP:20260424T021140
CREATED:20250828T044931Z
LAST-MODIFIED:20250828T044931Z
UID:361015-1769040000-1769212799@semiwiki.com
SUMMARY:IEEE Hybrid Bonding Symposium
DESCRIPTION:January 22-23\, 2026\, hosted by SEMI International\, Silicon Valley\, CA USA \nNote: HBS’26 is a hybrid event\, with both in-person and virtual participation via WebEx. \nDownload the Call for Presentations! \nHybrid Bonding has emerged as the technology of choice in the semiconductor and heterogeneous integration industries for ultra-fine-pitch interconnection. With significant benefits for interconnect density and device performance\, it will become widely adopted for a broad range of high-performance semiconductor devices in the years to come. The success of Hybrid Bonding technology for high-volume manufacturing depends critically on the process technology as well as materials and equipment. Design\, performance characterization\, thermal management and reliability are also important considerations to enable applications in various areas. \nReview the HBS’25 Program\, and watch videos of most of the presentations.\nPost-Symposium Report on the 2025 Hybrid Bonding Symposium \nREGISTER HERE
URL:https://semiwiki.com/event/ieee-hybrid-bonding-symposium/
LOCATION:SEMI HQ\, SEMI HQ\, 673 S Milpitas Blvd.\, Milpitas\, CA\, 95035\, United States
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