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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260513T080000
DTEND;TZID=America/Los_Angeles:20260513T170000
DTSTAMP:20260416T024217
CREATED:20251211T210953Z
LAST-MODIFIED:20251211T210953Z
UID:364610-1778659200-1778691600@semiwiki.com
SUMMARY:DVCon China 2026
DESCRIPTION:Hello everyone! Welcome to the 2026 DvCon China Conference! As the chair of this conference\, l am truly honored to be here with all of you. lt’s exciting to gather together and discuss the latest trends and cutting-edge technologies in the field of design verification. \nIn recent years\, we’ve seen tremendous growth in China’s chip development across various sectors\, particularly in critical areas like CPUs\, GPUs\, artificial intelligence\, automotive electronics\, communications\, and the Internet of Things (loT). lt’s inspiring to witness the rapid rise of domestic companies in these fields\, which not only drives technological advancement but also enhances our overall market competitiveness. \nAbout DVCon China\nDVCon China is a technical conference in China targeting the application of standardized languages\, tools\, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative\, the format of DVCon China is similar to the successful DVCon United States conference held for over 20 years in the Silicon Valley. \nIn order to boost the interest\, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in China\, this highly technical conference is organized to invite industry experts to learn and share best practices on: \n1. The application of system-level design and verification languages such as SystemC\, SystemVerilog or e 2.The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL) 3.Verification methodologies based on the Universal Verification Methodology (UVM) \nREGISTER HERE
URL:https://semiwiki.com/event/dvcon-china-2026/
LOCATION:Shanghai Renaissance Pudong Hotel\, Renaissance Shanghai Pudong\, 719 Yingchun Rd\,\, Pudong\, Shanghai\, 201204\, China
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-11-130932.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260514
DTEND;VALUE=DATE:20260515
DTSTAMP:20260416T024217
CREATED:20260414T060032Z
LAST-MODIFIED:20260414T060032Z
UID:368370-1778716800-1778803199@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Bracknell
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nEvent Details\n06 May 2026 – 30 Jun 2026 \nVarious \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-bracknell/
LOCATION:Bracknell\, UK\, Bracknell\, United Kingdom
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260514T083000
DTEND;TZID=America/Los_Angeles:20260514T173000
DTSTAMP:20260416T024217
CREATED:20260326T213508Z
LAST-MODIFIED:20260326T213508Z
UID:367926-1778747400-1778779800@semiwiki.com
SUMMARY:TSMC 2026 Boston Technology Workshop
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-2026-boston-technology-workshop/
LOCATION:Boston Marriott Burlington\, Boston Marriott Burlington\, One Burlington Mall Road\, Burlington\, MA\, 01803\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-26-142210.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260514T090000
DTEND;TZID=America/Los_Angeles:20260514T163000
DTSTAMP:20260416T024217
CREATED:20260326T213902Z
LAST-MODIFIED:20260326T213902Z
UID:367928-1778749200-1778776200@semiwiki.com
SUMMARY:TSMC 2026 Taiwan Technology Symposium
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the TSMC 2026 Technology Symposium! \nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-2026-taiwan-technology-symposium/
LOCATION:Sheraton Hsinchu Hotel\, Sheraton Hsinchu Hotel\, No. 265號\, E Section 1\, Guangming 6th Rd\, Zhubei City\, Hsinchu County\, 302\, Taiwan
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-26-142210.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260515T100000
DTEND;TZID=America/Los_Angeles:20260515T110000
DTSTAMP:20260416T024217
CREATED:20260414T062904Z
LAST-MODIFIED:20260414T062904Z
UID:368405-1778839200-1778842800@semiwiki.com
SUMMARY:Webinar: How Frequency Ranges Expanded\, and Why Measurement Fidelity Became Critical
DESCRIPTION:As systems move into higher frequencies and wider bandwidths\, small measurement errors can lead to costly design decisions. Engineers working in wireless\, radar\, satellite\, and optical domains must now validate signals that push existing tools to their limits. \nJoin Jun Chie\, Vice President of Product Management at Keysight\, to explore where measurement fidelity begins to break down\, and how engineers are adapting. You’ll see how next-generation instrumentation helps improve signal accuracy\, reduce uncertainty\, and increase confidence in design decisions. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-frequency-ranges-expanded-and-why-measurement-fidelity-became-critical/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260416T024217
CREATED:20250828T060208Z
LAST-MODIFIED:20250828T060208Z
UID:361093-1779062400-1779321599@semiwiki.com
SUMMARY:VOICE 2026
DESCRIPTION:VOICE is a developer conference\, created by test engineers for test engineers.\n\n\n\n\n\n\n\n\nEach year\, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs)\, foundries\, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements\, express new ideas\, share best practices and network with one another. \n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/voice-2026/
LOCATION:Scottsdale\, Arizona\, Scottsdale\, AZ\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-230026.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260518
DTEND;VALUE=DATE:20260521
DTSTAMP:20260416T024217
CREATED:20260414T061153Z
LAST-MODIFIED:20260414T061153Z
UID:368387-1779062400-1779321599@semiwiki.com
SUMMARY:Surface Preparation and Cleaning Conference (SPCC)
DESCRIPTION:Surface Preparation and Cleaning Conference (SPCC)\, formerly presented by Linx Consulting\, brings together key business insights\, IC manufacturers\, equipment makers\, materials and chemical providers\, metrology experts\, process technologists to address critical challenges\, and innovations in surface preparation and cleaning. \nHeld at the Wild Horse Pass Resort in Chandler\, Arizona\, SPCC 2026 will feature technical sessions\, poster presentations\, and business-focused programming\, creating a unique forum where technology and industry strategy converge. \nREGISTER HERE
URL:https://semiwiki.com/event/surface-preparation-and-cleaning-conference-spcc/
LOCATION:Wild Horse Pass\, Wild Horse Pass\, 5040 Wild Horse Pass Blvd\, Chandler\, AZ\, 85226\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-231044.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260519
DTEND;VALUE=DATE:20260520
DTSTAMP:20260416T024217
CREATED:20260414T060148Z
LAST-MODIFIED:20260414T060148Z
UID:368372-1779148800-1779235199@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Cambridge
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nEvent Details\n06 May 2026 – 30 Jun 2026 \nVarious \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-cambridge/
LOCATION:Cambridge\, UK\, Cambridge\, England\, United Kingdom
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260522T100000
DTEND;TZID=America/Los_Angeles:20260522T110000
DTSTAMP:20260416T024217
CREATED:20260414T063003Z
LAST-MODIFIED:20260414T063003Z
UID:368408-1779444000-1779447600@semiwiki.com
SUMMARY:Webinar: How System Scale Expanded\, and Why Network Traffic Validation Became Essential
DESCRIPTION:AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions\, not just in isolated tests. \nJoin Ram Periakaruppan\, vice president and general manager of network applications and security at Keysight\, to learn how large-scale traffic emulation reveals congestion\, latency issues\, and performance limits. You’ll see how to validate AI infrastructure under real workloads and ensure it performs reliably at scale. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-system-scale-expanded-and-why-network-traffic-validation-became-essential/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260526
DTEND;VALUE=DATE:20260530
DTSTAMP:20260416T024217
CREATED:20260107T103602Z
LAST-MODIFIED:20260107T103602Z
UID:365387-1779753600-1780099199@semiwiki.com
SUMMARY:2026 IEEE 76th Electronic Components and Technology Conference
DESCRIPTION:About ECTC\nThe Electronic Components and Technology Conference (ECTC) is the premier international event that brings together the best in packaging\, components and microelectronic systems science\, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the IEEE Electronics Packaging Society. \nREGISTER HERE
URL:https://semiwiki.com/event/2026-ieee-76th-electronic-components-and-technology-conference/
LOCATION:Orlando\, FL\, Orlando\, FL\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-023521.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260526
DTEND;VALUE=DATE:20260531
DTSTAMP:20260416T024217
CREATED:20260107T103813Z
LAST-MODIFIED:20260107T103813Z
UID:365390-1779753600-1780185599@semiwiki.com
SUMMARY:Hardwear.io Security Trainings and Conference USA 2026
DESCRIPTION:Learn from leading hardware security researchers & professionals and discuss\nthe latest & most innovative research on attacking and defending hardware. \nConnect with industry peers. Join us for a bigger\, bolder\, and better hardwear.io. \nARE YOU READY FOR HARDWEAR.IO USA 2026?\n\nIn the past couple of months our goal was to knuckle down and build a physical event where we can meet again and hang out in a safe & welcoming environment. And we did it! We managed to pull it off\, and (dare we say?) our USA event was incredible. \nBuilding on this success\, Hardwear.io USA returns as a physical conference in Santa Clara Marriott\, USA between 26th May – 30th May 2026. \n26th May – 30th May: fasten your seatbelts for intensive in-person trainings\, top-notch hardware-security talks\, professional networking\, stimulating CTFs and a challenging HardPwn. Mark your calendars and get ready. \nJoin Hardwear.io USA 2026 to learn\, network\, and collaborate with like-minded professionals! \n\nREGISTER HERE
URL:https://semiwiki.com/event/hardwear-io-security-trainings-and-conference-usa-2026/
LOCATION:Santa Clara Marriott\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-023728.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260527
DTEND;VALUE=DATE:20260528
DTSTAMP:20260416T024217
CREATED:20260414T060317Z
LAST-MODIFIED:20260414T060317Z
UID:368374-1779840000-1779926399@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Milan
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-milan/
LOCATION:Milan\, Italy\, Milan\, Italy
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260528T083000
DTEND;TZID=America/Los_Angeles:20260528T170000
DTSTAMP:20260416T024217
CREATED:20260326T214043Z
LAST-MODIFIED:20260326T214043Z
UID:367930-1779957000-1779987600@semiwiki.com
SUMMARY:TSMC Europe Technology Symposium
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-europe-technology-symposium/
LOCATION:Hilton Amsterdam Airport Schiphol\, Hilton Amsterdam Airport Schiphol\, Schiphol Boulevard 701\, 1118 BN Schiphol Airport\, Amsterdam\, Netherlands
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-26-142210.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260529T100000
DTEND;TZID=America/Los_Angeles:20260529T110000
DTSTAMP:20260416T024217
CREATED:20260414T063056Z
LAST-MODIFIED:20260414T063056Z
UID:368410-1780048800-1780052400@semiwiki.com
SUMMARY:Webinar: How Manufacturing Complexity Increased\, and Why Validation Had to Evolve
DESCRIPTION:As semiconductor complexity increases and board designs become denser\, manufacturing teams face tighter tolerances\, reduced test access\, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address. \nJoin Jason Kary\, Senior Vice President and President of Keysight’s Electronic Industrial Solutions Group\, to explore how manufacturing validation is evolving. You’ll learn how wafer-level and in-circuit test strategies improve coverage\, detect defects earlier\, and enable consistent\, high-volume production at scale without compromising quality. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-manufacturing-complexity-increased-and-why-validation-had-to-evolve/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260601
DTEND;VALUE=DATE:20260605
DTSTAMP:20260416T024217
CREATED:20260211T220349Z
LAST-MODIFIED:20260211T220349Z
UID:366626-1780272000-1780617599@semiwiki.com
SUMMARY:Realize LIVE Americas 2026
DESCRIPTION:Join us in 2026\nWe are ready to deliver more \n3\,000+ attendees. Join our community of users\, industry experts and trusted partners. Realize LIVE offers something for everyone! \n450+ sessions. Explore breakout sessions\, technical tracks\, trainings and more. More than 60% of sessions were led by customers\, sharing real-world insights. \n90% overall satisfaction rate. Realize LIVE is your digital transformation destination! Join our community and walk away a better user. \n\n\n\nGet hands-on with your digital transformation\n\n\n\n\n\nConnect with users\, industry experts and partners to share insights and explore the latest trends\, technologies and best practices. Explore session formats\, topics and industries across 450+ sessions\, including 50 hands-on training sessions. \n\n\n\n\nAccelerate your digital transformation journey\n\n\n\n\n\nLearn from experts and industry leaders\, build skills and discover the latest trends and technology with more than 400 sessions. \n\n\n\n\n\n\nBecome a better user\nLeave more productive! In 2025 90% of attendees left with new skills and enhanced tool proficiency. Speakers shared how they achieve up to 5x productivity boost. \n\n\nBe inspired by thought leaders\nIn 2025 65% of Realize LIVE sessions were led by customers\, sharing real-world insights and innovations. You can expect even more in 2026. \n\n\nStay ahead with product roadmaps\nAttendees will stay up-to-date with exclusive product presentations showcasing the latest advancements in Siemens technology\, and hear about functionality updates\, so you can plan for what comes next. \n\n\nGain exclusive hands-on training and certification\nAttendees receive complimentary hands-on training\, 60 days access to Siemens Xcelerator Academy and 20 lab hours. Plus\, the opportunity to earn your Siemens Xcelerator Certification. \n\n\nDive into the Siemens ecosystem\nRealize LIVE is your destination for all things digital transformation. Meet with experts\, engage with partners and experience live demos in the Solutions Center. \n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/realize-live-americas-2026/
LOCATION:Huntington Place Convention Center\, Huntington Place Convention Center\, 1 Washington Boulevard\, Detroit\, MI\, 48226\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/Screenshot-2026-02-11-140309.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260602
DTEND;VALUE=DATE:20260603
DTSTAMP:20260416T024217
CREATED:20260414T060424Z
LAST-MODIFIED:20260414T060424Z
UID:368377-1780358400-1780444799@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Grenoble
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-grenoble/
LOCATION:Grenoble\, France
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260602
DTEND;VALUE=DATE:20260606
DTSTAMP:20260416T024217
CREATED:20250828T060731Z
LAST-MODIFIED:20250828T060731Z
UID:361098-1780358400-1780703999@semiwiki.com
SUMMARY:COMPUTEX Taipei 2026
DESCRIPTION:Main Themes\nCOMPUTEX is a leading global exhibition focused on AIoT and startups. \nThe expo will continue with the position of “AI Next”\, \nfeaturing the latest tech trends: AI & Robotics\, Next-Gen Tech\, and Future Mobility. \nRecognized for its adaptability to industry changes. \nIt has established itself as a premier platform for showcasing technological innovations. \nAbout COMPUTEX\n\n\nEstablished in 1981\, COMPUTEX TAIPEI (also called COMPUTEX) is the leading global ICT and IoT show with a complete supply chain and ecosystems. \nCo-organized by the Taiwan External Trade Development Council (TAITRA) and Taipei Computer Association (TCA)\, COMPUTEX\, based upon Taiwan’s complete ICT clusters\, covers the whole spectrum of ICT industry\, from established brands to startups and from ICT supply chain to IoT ecosystems. \nWith strong R&D and manufacturing capabilities and IPR protection\, Taiwan is a strategic destination for foreign companies and investors looking for partners in global technology ecosystems \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/computex-taipei-2026/
LOCATION:Taipei Nangang Exhibition Center\, Taipei Nangang Exhibition Center\, No. 1\, Jingmao 2nd Rd\, Taipei City\, Nangang District\, 115\, Taiwan
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/taipei-taiwan-computex-2026.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260607
DTEND;VALUE=DATE:20260613
DTSTAMP:20260416T024217
CREATED:20251211T213235Z
LAST-MODIFIED:20251211T213235Z
UID:364629-1780790400-1781308799@semiwiki.com
SUMMARY:IMS2026
DESCRIPTION:Welcome to IMS2026\n\n\n\n\n\n\n\n\n\n\n\n\n\nThe IEEE International MTT Symposia (IMS) (www.ims-ieee.org) is the world’s premier RF/microwave technical conference and industry exhibition. Attendees will appreciate that IMS2026 has been refreshed with the technical content reorganized\, and new branding\, new website\, and new mobile app launched. \nIMS2026 kicks off with the IEEE MTT-S RF Integrated Circuits (RFIC) Symposium\, then introduces two new symposia formed out of traditional IMS technical content\, the IEEE MTT-S RF Technology & Techniques (RFTT) Symposium and the IEEE MTT-S RF Systems & Applications (RFSA) Symposium\, before concluding the week with the ARFTG Microwave Measurement Conference. \n\n\n\n\n\n\n\nA Week of Opportunities\nIn historic Boston\, IMS2026 kicks off with the IEEE MTT-S RF Integrated Circuits (RFIC) Symposium\, then introduces two new symposia formed out of traditional IMS technical content\, the IEEE MTT-S RF Systems & Applications (RFSA) Symposium and IEEE MTT-S RF Technology & Techniques (RFTT) Symposium\, before concluding the week with the ARFTG Microwave Measurement Conference. \n\nIMS2026 isn’t just about innovation — it’s about connection. It’s the best place to network with peers\, learn from experts\, uncover new opportunities\, and tackle the challenges defining the future of our field. This is where the community comes together to learn about groundbreaking theories and practices\, and explore cutting-edge products and services. \nIMS by the Numbers \n\n8\,484 registered attendees representing 55 countries\n500+ exhibiting companies\, including 98 first timer exhibitors\n14 Start-Up Pavilion participants\n200+ education sessions\n\nREGISTER HERE
URL:https://semiwiki.com/event/ims2026/
LOCATION:Boston\, MA\, Boston\, MA\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/12/header.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260608
DTEND;VALUE=DATE:20260611
DTSTAMP:20260416T024217
CREATED:20260107T105021Z
LAST-MODIFIED:20260107T105021Z
UID:365393-1780876800-1781135999@semiwiki.com
SUMMARY:SWTest 2026
DESCRIPTION:The Semiconductor Wafer Test Conference (SWTest) is celebrating its 35th year as the only industry event that focuses on all the aspects associated with microelectronic wafer and die level testing. The conference has the perfect mixture of manufacturer and vendor presentations. It is a probe technology forum where attendees come to learn about recent developments in the industry and exchange ideas. There is a relaxed atmosphere with a golf tournament\, an EXPO\, social activities and plenty of time for informal discussion and networking. \nTechnical Program\nSWTest 2026 is a two-and-a-half-day conference that starts with a Monday Keynote Speaker and consists of a Technical Program with technical presentations organized in 8 theme-oriented sessions. There will also be poster presentations during the coffee breaks. \nExhibitors\nThe SWTest EXPO is the Who’s Who of Industry Leaders in the Semiconductor Wafer Test Industry. The top probe card\, probe equipment and related service suppliers will showcase the latest products and services at SWTest 2026. \nREGISTER HERE
URL:https://semiwiki.com/event/swtest-2026/
LOCATION:Omni La Costa Resort & Spa\, 2100 Costa Del Mar Rd\, Carlsbad\, CA\, 92009\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-024905.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260610
DTEND;VALUE=DATE:20260612
DTSTAMP:20260416T024217
CREATED:20260107T105553Z
LAST-MODIFIED:20260107T105553Z
UID:365397-1781049600-1781222399@semiwiki.com
SUMMARY:Hardware Pioneer Max
DESCRIPTION:Join the UK’s largest expo dedicated to cutting-edge hardware technology for innovation-driven engineers\n\n\n\n\nAt Hardware Pioneers Max you have the unique opportunity to meet with leading experts and suppliers that can help you learn faster\, make better decisions and speed up your product development process. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/hardware-pioneer-max/
LOCATION:ExCeL London\, Royal Victoria Dock\, 1 Western Gateway\, London\, E16 1XL\, United Kingdom
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-025525.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260610
DTEND;VALUE=DATE:20260612
DTSTAMP:20260416T024217
CREATED:20260326T224703Z
LAST-MODIFIED:20260326T224703Z
UID:367952-1781049600-1781222399@semiwiki.com
SUMMARY:2026 European Executive Forum
DESCRIPTION:June 10 8:00 AM – June 11 5:00 PM CEST\n2026 European Executive Forum\n\nMunich\, Germany\n\nREGISTER HERE
URL:https://semiwiki.com/event/2026-european-executive-forum/
LOCATION:Munich\, Germany
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260614
DTEND;VALUE=DATE:20260619
DTSTAMP:20260416T024217
CREATED:20250828T061019Z
LAST-MODIFIED:20250828T061019Z
UID:361103-1781395200-1781827199@semiwiki.com
SUMMARY:2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
DESCRIPTION:New concepts and breakthroughs in VLSI processes and devices including Memory\, Logic\, I/O\, and I/F (RF/Analog/MS\, Imager\, MEMS\, etc.) – Advanced gate stack and interconnect in VLSI processes and devices – Advanced lithography and fine patternig technologies for high density VLSI – New functional devices beyond CMOS with a path for VLSI implantation – Packing of VLSI devices including 3D – system integration – Processes and devices modeling of VLSI devices – Reliability related to the above devices. \nHonolulu\, Hawaii\, USA  |  Event Format : Hybrid (In-person and Virtual) \nREGISTER HERE
URL:https://semiwiki.com/event/2026-ieee-jsap-symposium-on-vlsi-technology-and-circuits-vlsi-technology-and-circuits/
LOCATION:Honolulu\, Hawaii\, Honolulu\, HI\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-230953.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260616
DTEND;VALUE=DATE:20260618
DTSTAMP:20260416T024217
CREATED:20250828T061412Z
LAST-MODIFIED:20250828T061412Z
UID:361106-1781568000-1781740799@semiwiki.com
SUMMARY:Automobil-Elektronik Kongress 2026
DESCRIPTION:We are excited to announce the 30th Automobil-Elektronik Kongress\, set to take place on June 16 and 17\, 2026 at the Forum am Schlosspark in Ludwigsburg\, Germany. This prestigious technical conference will bring together industry experts\, researchers\, and innovators to discuss the latest advancements in automotive electronics. Join us to stay at the forefront of innovation in the automotive electronics industry and network with leading professionals in the field. \nREGISTER HERE
URL:https://semiwiki.com/event/automobil-elektronik-kongress-2026/
LOCATION:Forum am Schlosspark\, Stuttgarter Str. 33\, Ludwigsburg\, 71638\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-231304.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260617
DTEND;VALUE=DATE:20260620
DTSTAMP:20260416T024217
CREATED:20260107T105806Z
LAST-MODIFIED:20260107T105806Z
UID:365400-1781654400-1781913599@semiwiki.com
SUMMARY:3D & Systems Summit 2026
DESCRIPTION:Themed Heterogeneous Integration: Bolstering Europe’s Resilience the 3D & Systems Summit 2025 will primarily focus on exploring strategies for enhancing Europe’s semiconductor industry addressing topics as geopolitical dynamics\, market trends\, as well as the latest advancements in chiplet applications and hybrid bonding techniques. The Summit will feature an exclusive exhibition area\, showcasing industry leaders alongside innovative emerging companies. This Summit is a platform for gathering and exchange of knowledge and fostering of collaborations within the semiconductor sector. \nAttendees will have several opportunities for B2B matching\, including networking receptions\, coffee breaks\, lunches\, and a unique Networking Dinner Cruise along the beautiful Elbe River. \nREGISTER HERE
URL:https://semiwiki.com/event/3d-systems-summit-2026/
LOCATION:Hilton Dresden Hotel\, Hilton Dresden Hotel\, An der Frauenkirche 5 D\, Dresden\, 01067\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-025739.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260622
DTEND;VALUE=DATE:20260627
DTSTAMP:20260416T024217
CREATED:20251211T213919Z
LAST-MODIFIED:20251211T213919Z
UID:364634-1782086400-1782518399@semiwiki.com
SUMMARY:ISC 2026
DESCRIPTION:CONFERENCE & EXHIBITION\n\n\n\n\n\n\n\n\nHPC\, AI\, Quantum: Powering Innovation and Sustainability \n\n\n\n\nISC 2026 connects scientists\, engineers\, and technology leaders to explore the future of high performance computing. We will examine today’s breakthroughs in artificial intelligence\, high performance computing and quantum technologies\, as well as what lies ahead. \nAdditionally\, we are committed to sustainability by promoting energy-efficient and cost-effective computing\, while empowering the next-generation workforce to continue the community’s legacy of innovation. \nISC 2026 will bring together a mix of people from different backgrounds and areas of expertise to drive HPC. Whether you are just entering the field\, in a mid-level position\, a part of senior management\, or a student\, we welcome you to join our efforts to connect people and technologies. \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/isc-2026/
LOCATION:Hamburg\, Germany\, Hamburg\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-11-133841.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260623
DTEND;VALUE=DATE:20260624
DTSTAMP:20260416T024217
CREATED:20260114T021718Z
LAST-MODIFIED:20260129T235644Z
UID:365702-1782172800-1782259199@semiwiki.com
SUMMARY:Verification Futures Conference 2026 UK
DESCRIPTION:Verification Futures UK 2026\, co-located with Semiconductors Futures 2026 organised by Tessolve and co-organised this year with Alpinum. The conference continues its strong tradition of delivering a unique blend of conference presentations\, exhibitions\, training\, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers\, researchers\, and vendors to shape practical solutions. In 2026\, Verification Futures continues to strengthen its core emphasis on verification methodologies\, DV tools\, and engineering workflows\, including areas such as formal methods for complex SoCs\, CPU & RISC-V verification\, open-source and licence-free verification tools\, AI in design verification (AI in DV)\, verification planning and coverage\, and HW/SW co-verification. \nSemiconductors Futures 2026 brings together the semiconductor community\, covering AI/ML in IP & SoC design\, AI’s impact on EDA and workflows\, FPGA & mixed-signal\, with a focus on the automotive\, data centre\, and AI products. New tracks consider emerging technologies such as quantum computing\, photonics\, and chiplets\, as well as startups and investments. We expect 50+ engineering students to attend a separate session. \nCALL FOR PAPERS \nREGISTER HERE
URL:https://semiwiki.com/event/verification-futures-conference-2026-uk/
LOCATION:Hybrid: In-Person and Virtual Conference\, Reading\, United Kingdom
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260623
DTEND;VALUE=DATE:20260626
DTSTAMP:20260416T024217
CREATED:20260414T063431Z
LAST-MODIFIED:20260414T063431Z
UID:368412-1782172800-1782431999@semiwiki.com
SUMMARY:LID World Summit 2026
DESCRIPTION:CEA-Leti’s flagship event\n\n\n\n\nDiscover sustainable semiconductor breakthroughs to guide your roadmap from lab-to-market and to tomorrow’s AI factory at LID World Summit 2026. \nJoin industry leaders to discover groundbreaking innovation that will help meet technological goals for the healthcare\, automotive\, industrial\, defense\, and consumer-electronics sectors. Leave with confidence in the possible. \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/lid-world-summit-2026/
LOCATION:Grenoble\, France
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-233332.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260627
DTEND;VALUE=DATE:20260628
DTSTAMP:20260416T024217
CREATED:20260414T062122Z
LAST-MODIFIED:20260414T062122Z
UID:368392-1782518400-1782604799@semiwiki.com
SUMMARY:Scaling DRAM Technology to Meet Future Demands: System Challenges and Opportunities
DESCRIPTION:Tutorial Abstract\nSince the invention of the 1T1C bit cell more than 50 years ago\, DRAMs have become the main memory of choice for processors in computing systems and consumer electronics devices. As new computing paradigms have been created\, including AI\, 3D graphics\, HPC\, cloud computing\, and smart phones\, specialized processors and DRAM memories have been developed that are optimized for these use cases. The same 1T1C DRAM bit cell is used in each of these applications\, but the internal architecture and interfaces of the DRAMs supporting these markets are optimized in different ways\, and the DRAMs are packaged differently (sometimes with additional buffer chips) to meet the needs of the system. \nAcross all markets\, there is a relentless demand for higher performance and better power efficiency\, as insufficient DRAM bandwidth can bottleneck application performance and interfaces to DRAMs can consume half of the SOC power. DRAMs are also being stressed by growing reliability concerns as they incorporate on-die ECC and mitigation for disturbance effects such as RowHammer and RowPress. As AI continues to grow across markets (HPC\, server\, client\, mobile\, etc.)\, the design of efficient\, performant and reliable memory systems is becoming increasingly critical. AI models are continuing to grow\, pushing the capacity and bandwidth requirements of DRAMs. Simply scaling with historical techniques will no longer achieve the required characteristics due to physical challenges\, limits of process scaling\, and system architecture constraints including thermals and power delivery. \nThis tutorial will describe DRAM architecture in detail\, highlighting the similarities and differences between different DRAM technologies and the unique tradeoffs and design choices made to meet system needs. We will also cover the key components that memory transactions travel thorough to get to DRAMs and back\, including memory controllers\, PHYs\, and where applicable\, modules and buffer chips. We will describe the architecture of these critical components and discuss how DRAM architecture choices impact their performance and power efficiency. Standard scaling techniques for DRAMs will be highlighted along with challenges that the industry is currently facing. Input from industry experts will show the pros and cons of DRAM architecture choices\, demonstrating the system impact and requirements for mainstream adoption. Future DRAM architectures will also be discussed. \nTopics that will be covered\nThe tutorial will focus on DRAM architecture\, specifically looking at design tradeoffs and subsequent impact to the overall system performance\, power\, cost and reliability. The tutorial will cover the following topics: \n\nBackground and History of DRAM markets. How they were historically defined\, what changed\, and the drivers of new technologies.\nDRAM array architecture\, internal data paths\, shared structures\, and interfaces.\nThe future of DRAM\, including 3D DRAM cells.\nMemory modules\, including DIMMs\, CAMMs\, MRDIMMs\, and CXL modules and their buffer chips.\nCapacity\, power\, reliability\, cost tradeoffs that motivate different DRAM architectures for different markets including computing\, mobile\, graphics\, and AI. This will include underlying core architecture\, packaging and system integration.\nPower and energy differences between DRAM technologies.\nNovel packaging techniques including stacking and 2.5D assembly.\nReliability\, Availability\, and Serviceability (RAS) techniques\, including on-die error correction\, system-level ECC\, redundancy and repair\, and RowHammer and RowPress mitigation.\nProcessing in memory that has been implemented in DRAM silicon.\nMemory controller architecture and design challenges with current and future DRAMs.\nPHY architectures and challenges with achieving higher data rates and power efficiencies.\nSystem performance considerations\, including latency under load and the impact of core timings and core architecture on performance.\nMemory system architecture considerations to achieve maximum performance\, highlighting the impact of DRAM core timing and architecture tradeoffs on the host controller design.\nIndustry adoption challenges facing new DRAM technologies and features.\nChallenges for the future.\n\nOrganizers and Affiliations\nSteven Woo is a Fellow and Distinguished Inventor at Rambus Inc.\, where he leads research in Rambus Labs on advanced memory systems for accelerators and computing infrastructure\, and manages a team of senior architects. Since joining Rambus\, Steve has worked in various roles leading architecture\, technology\, and performance analysis efforts\, and in marketing and product planning roles leading strategy and customer programs.  He has more than 30 years of experience working on advanced memory systems and holds more than 100 US and international patents. Steve received his PhD and MS degrees in Electrical Engineering from Stanford University\, and Master of Engineering and BS Engineering degrees from Harvey Mudd College. \nWendy Elsasser is a Technical Director of Research Science at Rambus Inc. She works in the Rambus Labs R&D division researching future system architecture and developing innovative solutions to address the challenges of the memory sub-system. She has over 25 years of experience in industry\, starting with semi-custom micro-controller design\, test\, and implementation. Over the last 20 years\, her focus has been on memory sub-systems\, primarily external DRAM. Her experience includes DRAM controller architecture\, design\, and validation as well as active contributions to consortiums and standards bodies. Specifically\, she was a leader in the Gen-Z consortium and JEDEC\, helping to define future memory interfaces and DRAM standards. Her work has resulted in 15 patents. \nRobert Palmer is a Senior Technical Director of Research Science at Rambus Inc.\, leading research in future memory module and memory buffer chip architectures. He has over 25 years of industry experience developing silicon IP and communication ICs\, spanning the design of high-speed wireline transceiver circuits\, serial link and memory controller PHY microarchitectures\, and DDR and CXL memory buffer chip architectures and microarchitectures. In addition to his tenure at Rambus\, Robert has held positions at Velio Communications and Nvidia Research. He holds over 60 US and international patents. \nTaeksang Song is a Corporate Vice President at Samsung Electronics where he is leading a team dedicated to pioneering cutting-edge technologies including CAMM\, MRDIMM\, CXL memory expanders\, fabric attached memory solutions and processing near memory to meet the evolving demands of next-generation data-centric AI architectures. He has 20 years of professional experience in memory and sub-system architecture\, interconnect protocols\, system-on-chip design and collaborating with CSPs to enable heterogeneous computing infrastructure. Prior to joining Samsung Electronics\, he worked at Rambus Inc.\, Micron Technology and SK hynix in lead architect roles for the emerging memory controllers and systems. Taeksang received his PhD from KAIST\, South Korea\, in 2006. He has authored and co-authored over 20 technical papers and holds over 50 U.S. patents. \nREGISTER HERE
URL:https://semiwiki.com/event/scaling-dram-technology-to-meet-future-demands-system-challenges-and-opportunities/
LOCATION:Raleigh\, North Carolina\, Raleigh\, NC\, United States
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260627
DTEND;VALUE=DATE:20260702
DTSTAMP:20260416T024217
CREATED:20260414T062249Z
LAST-MODIFIED:20260414T062249Z
UID:368397-1782518400-1782950399@semiwiki.com
SUMMARY:ISCA 2026
DESCRIPTION:The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. In 2026\, the 53rd edition of ISCA will be held in Raleigh at the Raleigh Convention Center from June 27 to July 1\, 2026. \nREGISTER HERE
URL:https://semiwiki.com/event/isca-2026/
LOCATION:Raleigh Convention Center\, Raleigh Convention Center\, 500 Fayetteville St\, Raleigh\, NC\, 27601\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-232202.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260628
DTEND;VALUE=DATE:20260702
DTSTAMP:20260416T024217
CREATED:20260107T110056Z
LAST-MODIFIED:20260107T110056Z
UID:365403-1782604800-1782950399@semiwiki.com
SUMMARY:ALD/ALE 2026
DESCRIPTION:Overview\n\n\n\n\nThe AVS 26th International Conference on Atomic Layer Deposition (ALD 2026) featuring the 13th International Atomic Layer Etching Workshop (ALE 2026) will be a three-day meeting dedicated to the science and technology of atomic layer controlled deposition of thin films and atomic layer etching.  Since 2001\, the ALD conference has been held alternately in the United States\, Europe and Asia\, allowing fruitful exchange of ideas\, know-how and practices between scientists. The conference will take place Sunday\, June 28-Wednesday\, July 1\, 2026\, at the JW Marriott Water Street\, Tampa\, Florida. \nAs in past conferences\, the meeting will be preceded (Sunday\, June 28) by one day of tutorials and perspectives and a welcome reception. Sessions will take place (Monday-Wednesday\, June 29-July 1) along with an industry tradeshow. All presentations will be audio-recorded and provided to attendees following the conference (posters will be included as PDFs). Anticipated attendance is 700+. View List of Invited Speakers \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/ald-ale-2026/
LOCATION:JW Marriott Water Street\, JW Marriott Water Street\, 510 Water St\, Tampa\, FL\, 33602\, United States
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END:VEVENT
END:VCALENDAR