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DTSTART;TZID=America/Los_Angeles:20260203T090000
DTEND;TZID=America/Los_Angeles:20260203T100000
DTSTAMP:20260403T153153
CREATED:20260114T022128Z
LAST-MODIFIED:20260114T022128Z
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SUMMARY:Webinar: From C++ to Silicon: Fast\, Physically Aware\, AI-Driven Exploration with Rise Design Automation and Precision Innovations
DESCRIPTION:As hardware designs grow more complex\, architectural exploration is increasingly critical to delivering differentiated silicon. Teams frequently develop promising architectures only to discover late in the cycle that physical implementation is too costly or fails to meet key specifications. This challenge intensifies as designers integrate new accelerators — video\, audio\, ML\, or custom datapaths — rapidly expanding the search space. \nAI-based automation can help\, but only when each exploration trial provides cost metrics (area\, timing\, power) that are both fast and credible. Traditional parameter sweeps are slow. Full physical analysis is expensive. And without correlation to real implementation costs\, AI-guided exploration can simply produce the wrong answers faster. \nRise Design Automation and Precision Innovations are partnering to change this dynamic. Together\, they deliver fast\, accurate\, physically aware exploration loops — ideal for reinforcement learning\, iterative refinement\, and high-volume experimentation. \nRise Design Automation provides 10× faster High-Level Synthesis (HLS) with timing and area correlation within a few percent of downstream RTL-synthesis results. The Rise toolchain can also execute downstream tools “under the hood” and incorporate their feedback directly into HLS. Integrating Precision Innovations’ industry ready OpenROAD-based RTL→GDSII flow and OpenROAD Flow Scripts adds production-grade physical estimation with strong area and timing accuracy validated down to advanced nodes (including 2–3nm). \nCombined\, this integrated flow enables rapid exploration from high-level C++/SystemC/SystemVerilog through synthesized RTL to physically correlated PPA — supporting hundreds or thousands of trials without licensing barriers. \nThis session demonstrates how an integrated\, AI-driven architectural exploration solution from Rise Design Automation and Precision Innovations provides rapid\, actionable feedback to guide design decisions\, and how you benefit from these capabilities in your own design flow. \n\n\n\n\n\n\n\n\nWhat You’ll Learn\n\n\n\n\nIn this technical deep dive\, you’ll see how Rise Design Automation and Precision Innovations help you: \n\nRun AI-guided architectural exploration with fast\, physically grounded cost metrics\nModel and explore designs in C++\, SystemC\, or SystemVerilog and automatically generate multiple RTL variants\nUse Rise’s fast\, correlated HLS engine to accelerate exploration with credible RTL-level PPA\nLeverage Precision’s OpenROAD-based RTL→GDSII flow for production-grade physical estimation — enabling early visibility into area\, timing\, and implementation feasibility\nApply reinforcement learning and design agents to guide the search toward optimal architectures\nScale exploration across hundreds or thousands of trials without restrictive per-run licensing\n\nThis webinar highlights practical techniques to accelerate exploration\, increase confidence\, and improve architectural decisions earlier in the design process. \n\n\n\n\nLive Demonstration\n\n\n\n\nSee a complete exploration loop from high-level behavioral model through Rise Design Automation’s HLS\, through RTL synthesis\, and into Precision Innovations’ OpenROAD-based physical estimator — with AI-guided refinement driven by real PPA feedback \n\n\n\n\nWho Should Attend:\n\n\n\n\nHardware architects\, design engineers\, verification leads\, and research teams who want to: \n\nAccelerate architectural exploration for complex accelerators\nApply AI/ML or reinforcement-learning workflows to silicon design\nImprove correlation between high-level design\, RTL\, and physical estimates\nConfidently explore many architectural options without slow iteration loops\nShift verification and physical awareness earlier in the flow\nDeploy scalable exploration without restrictive per-run licensing\n\nWhether you’re adding a new accelerator to an SoC or exploring ML-driven design automation\, this session provides a practical foundation for leveraging Rise + Precision. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-from-c-to-silicon-fast-physically-aware-ai-driven-exploration-with-rise-design-automation-and-precision-innovations/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-13-181938.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260128T100000
DTEND;TZID=America/Los_Angeles:20260128T110000
DTSTAMP:20260403T153153
CREATED:20251211T205410Z
LAST-MODIFIED:20251211T205410Z
UID:364596-1769594400-1769598000@semiwiki.com
SUMMARY:Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
DESCRIPTION:In this webinar\, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks. \nWe will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout. \nWe will show you how these tools work on real designs as well. \nWHO SHOULD ATTEND THIS WEBINAR?\nIf you are designing chips to deploy in networked environments\, you need to understand the risks ahead and how to minimize them. \nIf you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions. \nSPEAKERS\nBeau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies \nDr. Paul Calzada will take you through a live demonstration of CODAx\, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions. \n* This webinar is in partnership with SemiWiki and Caspia Technologies \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-why-ai-assisted-security-verification-for-chip-design-is-so-important/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/12/background.jpeg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260128T090000
DTEND;TZID=America/Los_Angeles:20260128T170000
DTSTAMP:20260403T153153
CREATED:20260113T042846Z
LAST-MODIFIED:20260113T042846Z
UID:365659-1769590800-1769619600@semiwiki.com
SUMMARY:Power Seminar - Burnaby
DESCRIPTION:About this event\nAs power levels rise and systems scale\, high-power testing becomes more complex and time-consuming. This hands-on Power Solutions Seminar focuses on practical test strategies for batteries\, fuel cells\, green energy\, and power conversion. \nYou will experience expert-led technical sessions with hands-on\, real-world application insights. Explore Keysight’s three new High-Power ATE System Supplies and demos across our power portfolio to improve test efficiency\, accuracy\, and development speed. \n\n\n\n\n\n\n\nWho should attend this event?\nThis event is designed for development engineers in power electronics\, battery systems\, and green energy. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/power-seminar-burnaby/
LOCATION:Burnaby\, BC\, Burnaby\, British Columbia\, Canada
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-202823.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260128
DTEND;VALUE=DATE:20260129
DTSTAMP:20260403T153153
CREATED:20260113T043124Z
LAST-MODIFIED:20260113T043124Z
UID:365664-1769558400-1769644799@semiwiki.com
SUMMARY:Webinar: Powering the Future: Megawatt Charging Solutions for Heavy-Duty Electrification
DESCRIPTION:About this event\nJoin our upcoming webinar to discover how Keysight is powering the future of heavy-duty electric transportation with advanced megawatt-charging test solutions. \nLearn how to validate ultra-high-power delivery beyond 3 MW\, ensure compliance with MCS and ISO 15118-20\, and streamline interoperability testing\, all within a single\, fully controllable platform designed for both compliance and development debugging. \nWe’ll explore how seamless integration of software\, hardware\, and project services accelerates the deployment of safe\, scalable\, and standards-driven charging infrastructure for trucks\, ships\, and heavy machinery. \n\n\n\n\n\n\n\nWho should attend this event?\nThose involved in the shift towards a future-proven transportation\, logistics\, and construction ecosystem. Specific titles: OEM Electrification Leaders; EVSE Manufacturers & Charging Infrastructure Developers; Compliance & Standards Specialists; Fleet Electrification Managers: Grid Integration & Energy Management Specialists. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-powering-the-future-megawatt-charging-solutions-for-heavy-duty-electrification/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203022.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260127T090000
DTEND;TZID=America/Los_Angeles:20260127T100000
DTSTAMP:20260403T153153
CREATED:20251217T021629Z
LAST-MODIFIED:20251217T021629Z
UID:364770-1769504400-1769508000@semiwiki.com
SUMMARY:Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)
DESCRIPTION:Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process\, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process. \nWhat you will learn \n\nThe breadth of the entire Gencellicon portfolio\nHow timing closure solutions can alleviate your design process using Siemens tools\n\nWho should attend \n\nImplementation engineers\nSoC architects\nDesign Verification teams\nTest engineers\nPower architects\nPhysical designers\n\n\n\n\nSpeaker: \n\n\n\n\nHimanshu Bhatnagar \nSenior Director\, Siemens EDA \n\n\n\nHimanshu brings over 20 years of expertise in chip design\, having developed complex SoCs across networking\, communications\, imaging\, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis\, a practical guide to synthesis and static timing analysis. Before founding Excellicon\, now Gencellicon\, Himanshu held key positions at leading semiconductor companies\, including Mindspeed Technologies\, Conexant Systems\, and ST Microelectronics. At Conexant Systems\, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally\, Himanshu has served as an advisor to various EDA companies. \n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-solving-timing-closure-challenges-using-gencellicon-previously-excellicon/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-16-181547.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260127T083000
DTEND;TZID=America/Los_Angeles:20260127T170000
DTSTAMP:20260403T153153
CREATED:20260107T031557Z
LAST-MODIFIED:20260107T031557Z
UID:365310-1769502600-1769533200@semiwiki.com
SUMMARY:Semiconductor Traceability and Provenance Workshop
DESCRIPTION:The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday\, January 27\, 2026\, at the NIST National Cybersecurity Center of Excellence (NCCoE) conference facility\, in Rockville\, Maryland. This in-person\, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain\, which identified traceability as the top priority of semiconductor industry stakeholders. \nAs semiconductor devices grow more complex and globally distributed\, the risks from counterfeit components\, malicious tampering\, and opaque sourcing threaten the security\, reliability\, and resilience of critical systems. Strengthening traceability and provenance is essential to mitigating supply chain threats\, supporting national security imperatives\, and addressing the grand challenges in secure microelectronics (https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000.pdf). \nThe workshop will convene technical leaders across the semiconductor ecosystem (e.g.\, hyperscalers\, auto and semiconductor companies\, federal agencies\, academia) to address the practical challenges and opportunities for implementing traceability in semiconductor chips. This one-day event will feature plenary\, panel\, and interactive breakout sessions. Participants will be encouraged to collaborate and discuss key questions and topics that will identify short-term (<1 year) and longer-term (2028-2029 time frame) activities related to semiconductor traceability and provenance. The topics that will be considered include but are not limited to: \n\nExisting solutions\nTechnical\, operational challenges to traceability adoption\nOpportunities for public-private collaboration (e.g.\, hyperscalers\, automobile\,\nsemiconductor companies\, government agencies\, academia)\nRoadblocks to alignment and paths to overcoming them\nEconomic drivers and pilot use cases for traceability\nFrameworks for joint standards development and implementation\nRoadmap for collaboration and path to success\n\n\nOutcomes from the workshop will include a published roadmap and post-workshop report that advances shared goals in securing semiconductor supply chains. \nRegistration Info\nThe registration fee for this event is $97.00 and includes AM/PM breaks and lunch. \nRegistration closes on Tuesday\, January 20\, 2026. \nRegistration Contact for Additional Information or Questions:\nCarol L. Shibley\ncarol.shibley@nist.gov\n(301) 975-8302 \nTECHNICAL CONTACT:\nKostas Amberiadis\nkostas.amberiadis@nist.gov \nREGISTER HERE
URL:https://semiwiki.com/event/semiconductor-traceability-and-provenance-workshop-2/
LOCATION:NIST’s National Cybersecurity Center of Excellence (NCCoE)\, 9700 Great Seneca Highway\, Rockville\, MD\, 20850\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/semiconductor-traceability-jan2026.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260122T093000
DTEND;TZID=America/Los_Angeles:20260122T160000
DTSTAMP:20260403T153153
CREATED:20260113T042624Z
LAST-MODIFIED:20260113T042624Z
UID:365654-1769074200-1769097600@semiwiki.com
SUMMARY:SpaceTech Symposium – Austin
DESCRIPTION:Satellite communications and design present complex challenges — from phased arrays to 5G non-terrestrial networks (NTNs). Are you equipped with the latest solutions to ensure mission success? \nJoin Keysight and CesiumAstro’s Vice President of Engineering\, James Carwell\, at our action-packed SpaceTech Symposium to learn practical insights and engage in demos to help you navigate these challenges. \nWalk away with: \n\nExpert tips on satellite link evaluation and testing.\nInsights into 3GPP adoption and critical R&D work paving the way for NTN and 6G.\nProven methods to ensure network security in your satellite system.\nBest practices for phased array system design and validation.\n\nPlus\, enjoy a complimentary lunch while networking with industry and education professionals in the satellite and wireless space. \nWho should attend this event?\nEngineers\, developers\, and leaders ready to accelerate design cycles\, strengthen system performance\, and stay ahead of emerging space-communication standards. \nREGISTER HERE
URL:https://semiwiki.com/event/spacetech-symposium-austin/
LOCATION:Capital Factory\, Capital Factory\, 701 Brazos St.\, Austin\, TX\, 78701\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-202518.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260122T083000
DTEND;TZID=America/Los_Angeles:20260122T170000
DTSTAMP:20260403T153153
CREATED:20251211T212321Z
LAST-MODIFIED:20251211T212321Z
UID:364621-1769070600-1769101200@semiwiki.com
SUMMARY:Optical Design Engineering User Conference
DESCRIPTION:About this event\nStay connected with the latest optical design product innovations across CODE V\, LightTools\, RSoft\, ImSym\, and our optical scattering measurement solutions. Get tips and tricks on design best practices from our experts\, and network with industry peers and the Keysight Optical Design Engineering team. The user conference is held in parallel with Photonics West\, making it an ideal opportunity to deepen your expertise while connecting with the broader photonics community. \n\n\n\n\n\n\n\nWho should attend this event?\nOptical engineers using CODE V\, LightTools\, RSoft\, ImSym\, and our optical scattering measurement solutions. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/optical-design-engineering-user-conference/
LOCATION:San Francisco\, CA\, San Francisco\, CA\, United States
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260122
DTEND;VALUE=DATE:20260124
DTSTAMP:20260403T153153
CREATED:20250828T044931Z
LAST-MODIFIED:20250828T044931Z
UID:361015-1769040000-1769212799@semiwiki.com
SUMMARY:IEEE Hybrid Bonding Symposium
DESCRIPTION:January 22-23\, 2026\, hosted by SEMI International\, Silicon Valley\, CA USA \nNote: HBS’26 is a hybrid event\, with both in-person and virtual participation via WebEx. \nDownload the Call for Presentations! \nHybrid Bonding has emerged as the technology of choice in the semiconductor and heterogeneous integration industries for ultra-fine-pitch interconnection. With significant benefits for interconnect density and device performance\, it will become widely adopted for a broad range of high-performance semiconductor devices in the years to come. The success of Hybrid Bonding technology for high-volume manufacturing depends critically on the process technology as well as materials and equipment. Design\, performance characterization\, thermal management and reliability are also important considerations to enable applications in various areas. \nReview the HBS’25 Program\, and watch videos of most of the presentations.\nPost-Symposium Report on the 2025 Hybrid Bonding Symposium \nREGISTER HERE
URL:https://semiwiki.com/event/ieee-hybrid-bonding-symposium/
LOCATION:SEMI HQ\, SEMI HQ\, 673 S Milpitas Blvd.\, Milpitas\, CA\, 95035\, United States
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260121
DTEND;VALUE=DATE:20260122
DTSTAMP:20260403T153153
CREATED:20260107T111253Z
LAST-MODIFIED:20260107T111253Z
UID:365420-1768953600-1769039999@semiwiki.com
SUMMARY:Webinar: Turning Compliance Into Competitive Credibility: Exclusive Launch of New CMMC Readiness Research
DESCRIPTION:About this event\nBe the first to see brand new\, Keysight-commissioned research on Cybersecurity Maturity Model Certification (CMMC) readiness across the U.S. Defense Industrial Base. In this live webinar\, we’ll unveil findings from hundreds of security\, IT\, and compliance leaders and show where organizations really stand. \nPlus\, attendees will be the first to get the full research paper\, The Power of Proof: Turning CMMC Compliance into Competitive Credibility. \n\n\n\n\n\n\nWho should attend this event?\nDesigned for professionals in governance\, risk\, compliance\, security validation\, and program management\, this webinar offers actionable intelligence for any organization preparing for CMMC certification. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-turning-compliance-into-competitive-credibility-exclusive-launch-of-new-cmmc-readiness-research/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-031208.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260120
DTEND;VALUE=DATE:20260123
DTSTAMP:20260403T153153
CREATED:20260113T042212Z
LAST-MODIFIED:20260113T042212Z
UID:365651-1768867200-1769126399@semiwiki.com
SUMMARY:POWERGEN 2026
DESCRIPTION:Unprecedented Demand. Unmatched Opportunity.\n\n\nA surge in data centers\, industrial expansion\, and electrification is reshaping power generation planning across North America. Utilities are under mounting pressure to maintain reliability and add new capacity. IPPs are accelerating project development to capture opportunity. EPCs and OEMs are finding innovative ways to build faster\, smarter\, and stronger amid supply chain and permitting headwinds. \nAt POWERGEN 2026\, we’re focusing on what it takes to deliver real megawatts and how collaboration across the generation ecosystem can meet the moment. \nWho should attend this event?\nThose involved in building\, operating and maintaining reliable megawatts during a period of rapid load growth including Utilities\, Grid & Energy Technology Providers / Solution Providers\, Independent Power Producers (IPPs) / Generators / Developers\, Original Equipment Manufacturers (OEMs). \n\nREGISTER HERE
URL:https://semiwiki.com/event/powergen-2026/
LOCATION:Henry B. González Convention Center\, 900 E Market St\, San Antonio\, TX\, 78205\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-202137.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260117
DTEND;VALUE=DATE:20260123
DTSTAMP:20260403T153153
CREATED:20250828T044529Z
LAST-MODIFIED:20250828T044529Z
UID:361011-1768608000-1769126399@semiwiki.com
SUMMARY:SPIE Photonics West 2026
DESCRIPTION:Share your work\, insights\, and breakthroughs. The 2026 call for papers is open.\nSPIE Photonics West is the world’s largest optics and photonics technologies event. Present your research in biomedical optics\, biophotonics\, industrial lasers\, optoelectronics\, microfabrication\, displays\, quantum\, and emerging vision technologies. \nConferences and Courses: 17–22 January \nThis is the place to be in January\nExperience the benefits of attending SPIE Photonics West—networking with colleagues\, learning the latest research\, and experiencing the newest innovations make this the most exciting week in photonics. See for yourself. \nPlan to take a course from an expert\nCourse offerings will give you the technical training you need to excel in your field. Choose from more than 55 courses in San Francisco during SPIE Photonics West. Adding a course to your registration adds to your entire event experience. \nFive major exhibitions\nExplore the companies that exhibit at the SPIE Photonics West Exhibition\, BiOS Expo\, AR | VR | MR Expo\, and Quantum West Expo. These leading companies are providing new capabilities and innovative products to help move your projects forward. Plus\, new this year\, Vision Tech Expo is growing. \nREGISTER HERE
URL:https://semiwiki.com/event/spie-photonics-west-2026/
LOCATION:San Francisco\, CA\, San Francisco\, CA\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/images-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260116T093000
DTEND;TZID=America/Los_Angeles:20260116T173000
DTSTAMP:20260403T153153
CREATED:20251016T010527Z
LAST-MODIFIED:20251209T210536Z
UID:362695-1768555800-1768584600@semiwiki.com
SUMMARY:Webinar: ASU-Silvaco Device TCAD Workshop: From Fundamentals to Applications
DESCRIPTION:This workshop is a fast-paced\, one-day program led by Prof. Dragica Vasileska and Prof. Stephen M. Goodnick. Spend the morning grounding yourself in semiconductor physics and transport\, then transition in the afternoon to instructor-led\, hands-on Silvaco TCAD labs (e.g.\, MOS Capacitors\, MOSFETs\, SOI Devices\, FinFETs). \nThe workshop is offered in a hybrid format. Participants have the option to join either in person at ASU or virtually via Zoom. \nAttendees will learn to use Silvaco TCAD effectively and know how to select the appropriate physical models and material parameters for their devices. Whether you are an industry professional or student\, you will leave with a practical grasp of semiconductor physics and the skills to use Silvaco TCAD effectively and efficiently. Complimentary lunch will be served\, followed by a Silvaco overview and Digital Twin session from Silvaco’s VP of Worldwide Field Applications Engineering\, Garrett Schlenvogt. \nWhen: January 16\, 2026 \nTime: 9:30am-5:30pm \nWhere: ASU Tempe Campus \nOld Main Building \n400 East Tyler Mall \nSecond Floor \nTempe\, AZ\, 85287 \nSeating is limited so register soon. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-asu-silvaco-device-tcad-workshop-from-fundamentals-to-applications/
LOCATION:ASU Tempe Campus\, ASU Tempe Campus\, Old Main Building\, 400 East Tyler Mall\, Second Floor\, Tempe\, AZ\, 85287\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/10/Screenshot-2025-12-09-130429.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260115T100000
DTEND;TZID=America/Los_Angeles:20260115T120000
DTSTAMP:20260403T153153
CREATED:20251219T204521Z
LAST-MODIFIED:20251219T204742Z
UID:364919-1768471200-1768478400@semiwiki.com
SUMMARY:Webinar: Accelerate IC Layout Parasitic Analysis with ParagonX
DESCRIPTION:We are pleased to offer two webinar sessions for your convenience. Please choose the time that best fits your schedule: \n10:00AM – 12:00PM CET (session #1 for EMEA/APAC)\n10:00AM – 12:00PM PST (session #2 for NA) \nFeatured Speakers: \n\nKopal Kulshreshtha\, Principal Product Specialist\, Synopsys\nRob Dohanyos\, Principal Product Specialist\, Synopsys\n\nIntroducing ParagonX\, a powerful tool for intelligent analysis\, debugging\, simulation\, and visualization of IC layout parasitics. It is perfect for root-cause analysis in top-level analog\, custom digital\, and mixed-signal designs. \nWhy You Should Attend: \n\nAssess and quantify the effects of layout parasitics early in the design process.\nElevate your productivity with rapid iterations that guide layout optimizations.\nSeamlessly integrate ParagonX into your analog and custom design workflow.\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-accelerate-ic-layout-parasitic-analysis-with-paragonx/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/12/SNPS4324872076-ParagonX-Banners-400x400px.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260115T090000
DTEND;TZID=America/Los_Angeles:20260115T170000
DTSTAMP:20260403T153153
CREATED:20251211T212005Z
LAST-MODIFIED:20251211T212203Z
UID:364616-1768467600-1768496400@semiwiki.com
SUMMARY:Advanced Measurements Seminar - Calgary
DESCRIPTION:About this event\nStart the new year off right with fresh insights and sharp skills. Join Keysight experts in Calgary for an all-day Advanced Measurements Seminar and cocktail reception. This hands-on technical event features live demonstrations with the latest RF and high-speed digital technologies. \nGain practical\, lab-ready insights to enhance accuracy\, reduce uncertainty\, and push your measurement capabilities further in 2026. Lunch and cocktails are on us. \nLearn more and reserve your spot today! \n\n\n\n\n\n\n\nWho should attend this event?\nIdeal for RF and high-speed digital engineers looking to deepen their measurement expertise. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/advanced-measurements-seminar-calgary/
LOCATION:Calgary\, AB\, Calgary\, Alberta\, Canada
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260114T110000
DTEND;TZID=America/Los_Angeles:20260114T120000
DTSTAMP:20260403T153153
CREATED:20250930T070232Z
LAST-MODIFIED:20250930T070232Z
UID:362252-1768388400-1768392000@semiwiki.com
SUMMARY:Webinar: 5 Expectations for the Manufacturing Market in 2026
DESCRIPTION:Discover the 5 Critical Manufacturing Market Trends Reshaping Semiconductors in 2026\nAI-driven investments\, sustainability\, and advanced materials—what’s next for semiconductor manufacturing. \nThe semiconductor manufacturing industry is undergoing a transformative period as AI-driven investments accelerate\, sustainability pressures mount\, and foundries navigate capacity expansion amid weak consumer demand. \nIn this live TechInsights webinar\, our manufacturing experts will highlight five critical developments shaping semiconductor fabrication and equipment markets in 2026\, offering actionable insights for strategists\, foundry operators\, and equipment suppliers. \nKey Topics You’ll Learn \n\nTSMC’s 2nm Mass Production Leadership – Achieving 7% of total capacity by 2026 while foundry/logic CAPEX rises for the first time since 2022.\nChina’s Role in Equipment Sales – Export control uncertainties and slower recovery extending into 2027\, with fabrication emissions projected to reach 200M metric tons CO₂e.\nInventory Optimization & AI Growth – Leveraging oversupply in consumer\, industrial\, and automotive segments to focus on AI-driven production.\nGlass Substrates Challenge Traditional Materials – Superior flatness\, signal integrity\, and sub-2-micron via capabilities for AI accelerators and HBM applications.\nWafer Fab Equipment Growth Focus – Concentration in microlithography for cutting-edge AI chips\, with subsystem suppliers benefiting from Asian capacity expansions.\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-5-expectations-for-the-manufacturing-market-in-2026/
LOCATION:This course will be held Online
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260114T100000
DTEND;TZID=America/Los_Angeles:20260114T110000
DTSTAMP:20260403T153153
CREATED:20251219T204133Z
LAST-MODIFIED:20251219T204814Z
UID:364917-1768384800-1768388400@semiwiki.com
SUMMARY:Webinar: Advances in ATPG: From Power and Timing Awareness to Intelligent Pattern Search with AI
DESCRIPTION:Date: Jan 14\, 2026 | 10:00 AM PST \n\n\nFeatured Speakers: \n\nSrikanth Venkat Raman\, Product Management Director\, Synopsys\nKhader Abdel-Hafez\, Scientist\, Synopsys\nTheo Toulas\, R&D Principal Engineer\, Synopsys\nBruce Xue\, Staff Engineer\, Synopsys\n\nAs System-on-Chip (SoC) designs become increasingly complex\, meeting test quality and cost goals requires advances in automatic test pattern generation (ATPG). Synopsys TestMAX™ ATPG is Synopsys’ state-of-the-art pattern generation solution. In this Synopsys webinar\, we will showcase the latest ATPG advancements\, from power- and timing-aware capabilities to leveraging AI for reducing test costs. Discover how you can meet the power constraints of your SoC tests with power-efficient ATPG patterns. Learn how timing-aware ATPG can enhance test quality. We will also explore Synopsys TSO.ai™ (Test Space Optimization AI)\, the industry’s first autonomous AI application for semiconductor testing\, designed to minimize test cost and time-to-market for today’s complex designs. \nWhy You Should Attend: \n\nDiscover best practices for limiting power consumption during shift and capture operations.\nSee practical demonstrations of how you manage test power at the top-level of your SoC through a top-level budget and partition-level budgets.\nLearn how advanced fault models (slack-based transition\, path delay\, and hold-time) can improve the quality of your tests from a timing standpoint.\nGain insights from Synopsys experts on how TestMAX™ ATPG leverages tighter connection with PrimeTime® to better handle timing exceptions (SDC) during test generation. See how ATPG can handle Muti-cycle paths (MCPs).\nLearn how TSO.ai automatically searches for an optimal solution in a large test search space to minimize pattern count and ATPG turn-around time reducing test costs dramatically.\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-advances-in-atpg-from-power-and-timing-awareness-to-intelligent-pattern-search-with-ai/
LOCATION:Online
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260114T080000
DTEND;TZID=America/Los_Angeles:20260114T090000
DTSTAMP:20260403T153153
CREATED:20260107T111051Z
LAST-MODIFIED:20260107T111051Z
UID:365416-1768377600-1768381200@semiwiki.com
SUMMARY:Webinar: Physics-Based Foundations for Power Supply Design
DESCRIPTION:Overview:\n\nThis webinar provides engineers with a science-driven framework for power supply design\, rooted in the physics of electromagnetic energy flow. Inspired by Ralph Morrison’s pioneering approach\, the session begins with core principles of energy behavior\, then explores how current\, fields\, and waves interact inside real circuits. \nAttendees will gain practical insight into:\n\nHow electromagnetic interactions shape power integrity\nWhy grounding\, return paths\, inductance\, capacitance\, and loop control are critical to reliable design\nHow to apply field-based thinking to achieve predictable\, first-time success\nHow to apply field-based thinking to achieve predictable\, first-time success\n\nBy the end of the session\, participants will walk away with a clear\, concise\, and powerful engineering perspective—one that replaces “black magic” with confidence and clarity in designing robust power systems. \n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-physics-based-foundations-for-power-supply-design/
LOCATION:Virtual
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260113T090000
DTEND;TZID=America/Los_Angeles:20260113T100000
DTSTAMP:20260403T153153
CREATED:20251211T205651Z
LAST-MODIFIED:20251211T205651Z
UID:364602-1768294800-1768298400@semiwiki.com
SUMMARY:Webinar: PQShield with Microchip’s PolarFire® SoC FPGAs: Securing the Future of Embedded Systems in the Post-Quantum Era
DESCRIPTION:As the quantum threat moves from theory to reality\, attacks put all long-lifecycle designs at risk. In this early PQC era\, simply implementing the new NIST algorithms isn’t enough. Implementations will evolve\, and new physical attacks like side-channel analysis present a major threat to the security of these complex new algorithms. \nThe solution requires both crypto-agility and deep hardware security. This webinar showcases PQShield’s hardware/software co-design as a side-channel secure PQC solution for Microchip’s PolarFire ® Series of products. \n\n\n\nSpeaker: \n\n\n\n\n\nSebastien Riou \nFellow\, Product Security Architecture\, PQShield \n\n\n\nSebastien has 15+ years experience in the semiconductor industry\, focusing on achieving “banking grade security” on resource constrained ICs such as smart cards and mobile secure elements. Formerly of Tiempo-Secure\, he helped create the world first integrated secure element IP achieving CC EAL5+ certification. He is the author of a semi-finalist algorithm at the Lightweight Cryptography NIST Standardisation process. He holds Master degrees in Computer Science and Cognitive Science from INPG. \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-pqshield-with-microchips-polarfire-soc-fpgas-securing-the-future-of-embedded-systems-in-the-post-quantum-era/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-11-125606.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260113T080000
DTEND;TZID=America/Los_Angeles:20260113T170000
DTSTAMP:20260403T153153
CREATED:20251211T211727Z
LAST-MODIFIED:20251211T211727Z
UID:364613-1768291200-1768323600@semiwiki.com
SUMMARY:Terascale AI\, 1.6T and Beyond Seminar: Santa Clara
DESCRIPTION:About this event\nNext-generation AI systems are pushing electrical\, optical\, and packaging technologies to their limits. Join Keysight experts as they share insights on validating 224G / 448G SerDes\, preparing for emerging IEEE 1.6T optical standards\, advancing silicon photonics\, and strengthening die-to-die interconnects for chiplet-based architectures. \nThis is your chance to learn directly from the engineers shaping the future of high-speed I / O design — all in one room. Sign up today. \n\n\n\n\n\n\n\nWho should attend this event?\nThis seminar is ideal for engineers working on next-generation connectivity and AI infrastructure\, including optical design\, silicon photonics\, high-speed digital\, validation\, test & measurement\, signal integrity\, compliance\, and chiplet / die-to-die interconnect architectures. \n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/terascale-ai-1-6t-and-beyond-seminar-santa-clara/
LOCATION:Santa Clara\, CA\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-11-131707.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260111
DTEND;VALUE=DATE:20260115
DTSTAMP:20260403T153153
CREATED:20250828T044214Z
LAST-MODIFIED:20250828T044214Z
UID:361004-1768089600-1768435199@semiwiki.com
SUMMARY:ISS 2026 Industry Strategy Symposium
DESCRIPTION:Join us at the Ritz-Carlton in Half Moon Bay\, CA to get the latest insights on economic trends\, market drivers\, geopolitics\, technology\, and what these will mean for the near future to help drive your business forward. The cooperative platform of ISS and its tremendous collective assets will serve to help power your strategies for the coming months and years. \nREADY\, SET\, RAMP!\n \nBuilding upon last year’s theme “Ready\, Set\, Ramp? “ of readiness and anticipation\, this year marks a bold declaration of action and confidence as we propel forward with vigor and purpose. \n“Ready\, Set\, Ramp! serves as a call to action for industry stakeholders to navigate these uncharted waters with agility and strategic vision.\nIt replaces the question marks of uncertainty with the exclamation points of determination and readiness! \nAs the semiconductor industry accelerates towards the monumental trillion-dollar milestone\, it’s crucial to explore strategies for coping with the rapid acceleration. Understanding and maneuvering through the dynamic landscape becomes paramount for sustained prosperity. \nISS delves into the multifaceted dimensions of this journey\, encompassing technological innovations\, burgeoning demand\, market diversification\, global integration\, R&D investments\, workforce shortage\, and sustainable practices. Addressing challenges and harnessing opportunities necessitates a holistic approach\, requiring collaborative efforts from industry stakeholders\, governments\, and research institutions. \n\nWhat are the demands and challenges inherent in this accelerated growth?\nHow is the industry allocating resources to facilitate this ramp-up?\nHow do we set the stage for all-time highs in semiconductor revenue and Wafer Fabrication Equipment (WFE) Investment?\nExploring the impact of emerging technologies and market diversification on the ramp-up trajectory.\nAccelerated computing powering a new industrial revolution–Are we prepared?\nWhat collaborative efforts and partnerships are necessary to overcome challenges and capitalize on opportunities as we surge toward the trillion-dollar milestone?\n\nBy engaging in these critical key questions and through collaborative discussions\, ISS attendees gain actionable insights and strategies for capitalizing on the industry’s upward trajectory while mitigating risks and challenges along the way\, positioning themselves for success in the race toward the trillion-dollar milestone. \nKEYNOTES\n\nAMD—Ramine Roane\, Corporate VP\, AI\nApplied Materials—Omkaram Nalamasu\, PhD\, Senior Vice President and CTO; Prabu Raja\, PhD\, President\, Semiconductor Products Group\nKLA—Oreste Donzella\, Executive Vice President – Electronics\, Packaging and Components (EPC) Group\nTSMC—Kevin Zhang\, PhD\, Senior Vice President of Business Development & Global Sales and Deputy Co-COO\nFormer U.S. Secretary of Commerce—The Honorable Wilbur Ross\n\n ISS 2025 Organizing Committee\nThank you to these industry leaders for their time and expertise supporting the continued success of this annual conference. \nREGISTER HERE
URL:https://semiwiki.com/event/iss-2026-industry-strategy-symposium/
LOCATION:The Ritz-Carlton\, Half Moon Bay\, The Ritz-Carlton\, 1 Miramontes Point Rd\, Half Moon Bay\, CA\, 94019\, United States
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260106
DTEND;VALUE=DATE:20260110
DTSTAMP:20260403T153153
CREATED:20250828T043604Z
LAST-MODIFIED:20250828T043604Z
UID:360996-1767657600-1768003199@semiwiki.com
SUMMARY:CES 2026
DESCRIPTION:The world’s most powerful tech event is your place to experience the innovations transforming how we live. \n\n\nThis is where global brands get business done\, meet new partners and where the industry’s sharpest minds take the stage to unveil their latest releases and boldest breakthroughs. Get a real feel for the latest solutions to the world’s biggest challenges with immersive activations and demos. Engage with the greatest minds and most impactful brands of our time. Sign up to be notified when registration opens for CES 2026. \n\n\nCES unites the brightest tech luminaries to pioneer the future and solve the world’s biggest challenges. \n\n\n\n\n\nCES connects innovators\, decision makers\, media\, influencers\, visionaries\, and potential customers across the entire tech ecosystem. \nDon’t be left in the past as we shape the future.\n\nGlobally showcase your technology products\nStand side-by-side with the world’s most disruptive innovators\nPromote your brand through curated opportunities to connect with influencers and prospective partners\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/ces-2026/
LOCATION:Las Vegas Convention Center\, Las Vegas Convention Center\, 3150 Paradise Rd\, Las Vegas\, NV\, 89109\, United States
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260105T110000
DTEND;TZID=America/Los_Angeles:20260105T120000
DTSTAMP:20260403T153153
CREATED:20250930T070018Z
LAST-MODIFIED:20250930T070104Z
UID:362249-1767610800-1767614400@semiwiki.com
SUMMARY:Webinar: 5 Expectations for the Mobile Market in 2026
DESCRIPTION:January 5\, 2026 – 11:00 AM EST    \nJanuary 6\, 2026 – 10:00 AM JST/KST \nDiscover the 5 Critical Mobile Market Trends Reshaping Semiconductors in 2026\nMobile AI\, shifting supply chains\, and new form factors—what’s next for the mobile semiconductor industry. \nThe mobile semiconductor market faces an inflection point in 2026. While trade and tariff uncertainties continue to disrupt global supply chains\, breakthrough technologies promise to reinvigorate growth in an industry facing maturity pressures. \nAs Google\, Apple\, and new disruptors expand AI-driven mobile experiences\, OEMs are rethinking hardware design\, SoC innovation\, and DRAM integration to meet rising consumer expectations. At the same time\, geopolitical dynamics are reshaping long-term manufacturing strategies\, and BRIC and emerging markets are exerting new influence over global demand. \nIn this live TechInsights webinar\, our experts will break down five critical developments reshaping the mobile industry in 2026 and beyond. \nKey Topics You’ll Learn \n\nMobile AI adoption – Google\, Apple\, and potential disruptors drive consumer traction.\nHardware & AI co-evolution – SoCs and DRAM innovation across Android OEMs.\nTariffs & trade impact – How pricing and supply chains are being reshaped.\nEmerging market influence – BRIC nations and new growth regions take the stage.\nForm-factor innovation – New designs promise to revitalize a stagnating market.\n\nREGISTER HERE
URL:https://semiwiki.com/event/5-expectations-for-the-mobile-market-in-2026/
LOCATION:Online
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