SemiWiki

Webinar: 5 Expectations for the Manufacturing Market in 2026
2026-01-14 11:00 - 12:00 (America/Los_Angeles) | This course will be held Online
Discover the 5 Critical Manufacturing Market Trends Reshaping Semiconductors in 2026
AI-driven investments, sustainability, and advanced materials—what’s next for semiconductor manufacturing.
The semiconductor manufacturing industry is undergoing a transformative period as AI-driven investments accelerate, sustainability pressures mount, and foundries navigate capacity expansion amid weak consumer demand.
In this live TechInsights webinar, our manufacturing experts will highlight five critical developments shaping semiconductor fabrication and equipment markets in 2026, offering actionable insights for strategists, foundry operators, and equipment suppliers.
Key Topics You’ll Learn

TSMC’s 2nm Mass Production Leadership – Achieving 7% of total capacity by 2026 while foundry/logic CAPEX rises for the first time since 2022.
China’s Role in Equipment Sales – Export control uncertainties and slower recovery extending into 2027, with fabrication emissions projected to reach 200M metric tons CO₂e.
Inventory Optimization & AI Growth – Leveraging oversupply in consumer, industrial, and automotive segments to focus on AI-driven production.
Glass Substrates Challenge Traditional Materials – Superior flatness, signal integrity, and sub-2-micron via capabilities for AI accelerators and HBM applications.
Wafer Fab Equipment Growth Focus – Concentration in microlithography for cutting-edge AI chips, with subsystem suppliers benefiting from Asian capacity expansions.

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Webinar: Advances in ATPG: From Power and Timing Awareness to Intelligent Pattern Search with AI
2026-01-14 10:00 - 11:00 | Online
Date: Jan 14, 2026 | 10:00 AM PST

Featured Speakers:

Srikanth Venkat Raman, Product Management Director, Synopsys
Khader Abdel-Hafez, Scientist, Synopsys
Theo Toulas, R&D Principal Engineer, Synopsys
Bruce Xue, Staff Engineer, Synopsys

As System-on-Chip (SoC) designs become increasingly complex, meeting test quality and cost goals requires advances in automatic test pattern generation (ATPG). Synopsys TestMAX™ ATPG is Synopsys’ state-of-the-art pattern generation solution. In this Synopsys webinar, we will showcase the latest ATPG advancements, from power- and timing-aware capabilities to leveraging AI for reducing test costs. Discover how you can meet the power constraints of your SoC tests with power-efficient ATPG patterns. Learn how timing-aware ATPG can enhance test quality. We will also explore Synopsys TSO.ai™ (Test Space Optimization AI), the industry’s first autonomous AI application for semiconductor testing, designed to minimize test cost and time-to-market for today’s complex designs.
Why You Should Attend:

Discover best practices for limiting power consumption during shift and capture operations.
See practical demonstrations of how you manage test power at the top-level of your SoC through a top-level budget and partition-level budgets.
Learn how advanced fault models (slack-based transition, path delay, and hold-time) can improve the quality of your tests from a timing standpoint.
Gain insights from Synopsys experts on how TestMAX™ ATPG leverages tighter connection with PrimeTime® to better handle timing exceptions (SDC) during test generation. See how ATPG can handle Muti-cycle paths (MCPs).
Learn how TSO.ai automatically searches for an optimal solution in a large test search space to minimize pattern count and ATPG turn-around time reducing test costs dramatically.

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Webinar: Physics-Based Foundations for Power Supply Design
2026-01-14 08:00 - 09:00 | Virtual
Overview:

This webinar provides engineers with a science-driven framework for power supply design, rooted in the physics of electromagnetic energy flow. Inspired by Ralph Morrison’s pioneering approach, the session begins with core principles of energy behavior, then explores how current, fields, and waves interact inside real circuits.
Attendees will gain practical insight into:

How electromagnetic interactions shape power integrity
Why grounding, return paths, inductance, capacitance, and loop control are critical to reliable design
How to apply field-based thinking to achieve predictable, first-time success
How to apply field-based thinking to achieve predictable, first-time success

By the end of the session, participants will walk away with a clear, concise, and powerful engineering perspective—one that replaces “black magic” with confidence and clarity in designing robust power systems.

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Webinar: PQShield with Microchip’s PolarFire® SoC FPGAs: Securing the Future of Embedded Systems in the Post-Quantum Era
2026-01-13 09:00 - 10:00 | Online
As the quantum threat moves from theory to reality, attacks put all long-lifecycle designs at risk. In this early PQC era, simply implementing the new NIST algorithms isn’t enough. Implementations will evolve, and new physical attacks like side-channel analysis present a major threat to the security of these complex new algorithms.
The solution requires both crypto-agility and deep hardware security. This webinar showcases PQShield’s hardware/software co-design as a side-channel secure PQC solution for Microchip’s PolarFire ® Series of products.

Speaker:

Sebastien Riou
Fellow, Product Security Architecture, PQShield

Sebastien has 15+ years experience in the semiconductor industry, focusing on achieving “banking grade security” on resource constrained ICs such as smart cards and mobile secure elements. Formerly of Tiempo-Secure, he helped create the world first integrated secure element IP achieving CC EAL5+ certification. He is the author of a semi-finalist algorithm at the Lightweight Cryptography NIST Standardisation process. He holds Master degrees in Computer Science and Cognitive Science from INPG.

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Terascale AI, 1.6T and Beyond Seminar: Santa Clara
2026-01-13 08:00 - 17:00 | Santa Clara, CA, Santa Clara, CA, United States
About this event
Next-generation AI systems are pushing electrical, optical, and packaging technologies to their limits. Join Keysight experts as they share insights on validating 224G / 448G SerDes, preparing for emerging IEEE 1.6T optical standards, advancing silicon photonics, and strengthening die-to-die interconnects for chiplet-based architectures.
This is your chance to learn directly from the engineers shaping the future of high-speed I / O design — all in one room. Sign up today.

Who should attend this event?
This seminar is ideal for engineers working on next-generation connectivity and AI infrastructure, including optical design, silicon photonics, high-speed digital, validation, test & measurement, signal integrity, compliance, and chiplet / die-to-die interconnect architectures.

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ISS 2026 Industry Strategy Symposium
2026-01-11 - 2026-01-14 | The Ritz-Carlton, Half Moon Bay, The Ritz-Carlton, 1 Miramontes Point Rd, Half Moon Bay, CA, 94019, United States
Join us at the Ritz-Carlton in Half Moon Bay, CA to get the latest insights on economic trends, market drivers, geopolitics, technology, and what these will mean for the near future to help drive your business forward. The cooperative platform of ISS and its tremendous collective assets will serve to help power your strategies for the coming months and years.
READY, SET, RAMP!

Building upon last year’s theme “Ready, Set, Ramp? “ of readiness and anticipation, this year marks a bold declaration of action and confidence as we propel forward with vigor and purpose.
“Ready, Set, Ramp! serves as a call to action for industry stakeholders to navigate these uncharted waters with agility and strategic vision.
It replaces the question marks of uncertainty with the exclamation points of determination and readiness!
As the semiconductor industry accelerates towards the monumental trillion-dollar milestone, it’s crucial to explore strategies for coping with the rapid acceleration. Understanding and maneuvering through the dynamic landscape becomes paramount for sustained prosperity.
ISS delves into the multifaceted dimensions of this journey, encompassing technological innovations, burgeoning demand, market diversification, global integration, R&D investments, workforce shortage, and sustainable practices. Addressing challenges and harnessing opportunities necessitates a holistic approach, requiring collaborative efforts from industry stakeholders, governments, and research institutions.

What are the demands and challenges inherent in this accelerated growth?
How is the industry allocating resources to facilitate this ramp-up?
How do we set the stage for all-time highs in semiconductor revenue and Wafer Fabrication Equipment (WFE) Investment?
Exploring the impact of emerging technologies and market diversification on the ramp-up trajectory.
Accelerated computing powering a new industrial revolution–Are we prepared?
What collaborative efforts and partnerships are necessary to overcome challenges and capitalize on opportunities as we surge toward the trillion-dollar milestone?

By engaging in these critical key questions and through collaborative discussions, ISS attendees gain actionable insights and strategies for capitalizing on the industry’s upward trajectory while mitigating risks and challenges along the way, positioning themselves for success in the race toward the trillion-dollar milestone.
KEYNOTES

AMD—Ramine Roane, Corporate VP, AI
Applied Materials—Omkaram Nalamasu, PhD, Senior Vice President and CTO; Prabu Raja, PhD, President, Semiconductor Products Group
KLA—Oreste Donzella, Executive Vice President – Electronics, Packaging and Components (EPC) Group
TSMC—Kevin Zhang, PhD, Senior Vice President of Business Development & Global Sales and Deputy Co-COO
Former U.S. Secretary of Commerce—The Honorable Wilbur Ross

ISS 2025 Organizing Committee
Thank you to these industry leaders for their time and expertise supporting the continued success of this annual conference.
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CES 2026
2026-01-06 - 2026-01-09 | Las Vegas Convention Center, Las Vegas Convention Center, 3150 Paradise Rd, Las Vegas, NV, 89109, United States
The world’s most powerful tech event is your place to experience the innovations transforming how we live.

This is where global brands get business done, meet new partners and where the industry’s sharpest minds take the stage to unveil their latest releases and boldest breakthroughs. Get a real feel for the latest solutions to the world’s biggest challenges with immersive activations and demos. Engage with the greatest minds and most impactful brands of our time. Sign up to be notified when registration opens for CES 2026.

CES unites the brightest tech luminaries to pioneer the future and solve the world’s biggest challenges.

CES connects innovators, decision makers, media, influencers, visionaries, and potential customers across the entire tech ecosystem.
Don’t be left in the past as we shape the future.

Globally showcase your technology products
Stand side-by-side with the world’s most disruptive innovators
Promote your brand through curated opportunities to connect with influencers and prospective partners

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Webinar: 5 Expectations for the Mobile Market in 2026
2026-01-05 11:00 - 12:00 | Online
January 5, 2026 – 11:00 AM EST
January 6, 2026 – 10:00 AM JST/KST
Discover the 5 Critical Mobile Market Trends Reshaping Semiconductors in 2026
Mobile AI, shifting supply chains, and new form factors—what’s next for the mobile semiconductor industry.
The mobile semiconductor market faces an inflection point in 2026. While trade and tariff uncertainties continue to disrupt global supply chains, breakthrough technologies promise to reinvigorate growth in an industry facing maturity pressures.
As Google, Apple, and new disruptors expand AI-driven mobile experiences, OEMs are rethinking hardware design, SoC innovation, and DRAM integration to meet rising consumer expectations. At the same time, geopolitical dynamics are reshaping long-term manufacturing strategies, and BRIC and emerging markets are exerting new influence over global demand.
In this live TechInsights webinar, our experts will break down five critical developments reshaping the mobile industry in 2026 and beyond.
Key Topics You’ll Learn

Mobile AI adoption – Google, Apple, and potential disruptors drive consumer traction.
Hardware & AI co-evolution – SoCs and DRAM innovation across Android OEMs.
Tariffs & trade impact – How pricing and supply chains are being reshaped.
Emerging market influence – BRIC nations and new growth regions take the stage.
Form-factor innovation – New designs promise to revitalize a stagnating market.

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Essential Debugging Techniques Workshop
2025-12-17 10:00 - 16:00 | Online
Essential Debugging Techniques Workshop
This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with general debugging concepts, tools and techniques. Special topics include helping guide attendees through the differences of using ISE Design Suite based ChipScope in Vivado for migrating to 7 Series devices and onward.
Additionally, this workshop will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. The demonstrations utilizing actual AMD ZCU104 Evaluation Boards provide attendees with experience designing, expanding and modifying an embedded system, including techniques for triggering on boot and hardware-software co-debugging.

COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.

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Webinar: From Silos to Systems, From Data to Insight (AM Session)
2025-12-17 10:00 - 11:00 | Online
December 17, 2025 | 10:00 AM PST
Join us to discover how Keysight Design Data Management (SOS) Enterprise Collaboration, as the backbone for modern engineering enterprises, enables teams to build organizational knowledge, secure collaboration, and prepare their data for AI and agentic workflows that drive measurable competitive advantage. The biggest challenges today are managing complexity, ensuring governance, and preparing data for AI. That’s exactly why Keysight SOS becomes critical.
What You Can Learn:

How to transition from disconnected design data silos to a unified, governed platform that accelerates collaboration and reuse.
How structured, traceable data enables analytics, machine learning, and AI copilots to boost design productivity and reduce rework.
How Keysight SOS Enterprise Collaboration empowers organizations to scale globally with secure governance, hybrid deployment, and AI-ready infrastructure.

Who Should Attend?

Engineering Directors and VPs of R&D seeking to modernize design collaboration and build enterprise-wide data governance.
CAD/EDA Managers and Methodology Leads responsible for tool integration, data management, and multi-site standardization.
Design and Verification Leads looking to improve traceability, reuse, and cross-domain visibility in complex design workflows.
IT and Data Governance Executives focused on compliance, audit readiness, and secure access to sensitive design data.
AI/ML Engineers and Data Scientists aiming to leverage structured engineering data for analytics, modelling, and AI-driven design acceleration.

Not in the Americas? Our European friendly session is also available – join here.

Presenter

Pedro Pires
Product Manager – Keysight Technologies
Pedro Pires is a Product Leader at Keysight Technologies with deep expertise in data management, engineering productivity, and MLOps for electronic design automation (EDA). With over a decade of experience spanning product strategy, design infrastructure, and enterprise data lifecycle management, he has helped global semiconductor organizations modernize their engineering environments through scalable collaboration, governance, and process automation.
At Keysight, Pedro leads initiatives that connect design and data platforms across global teams, defining the architecture for next-generation solutions that unify design data and enable AI readiness through sound data foundations. He holds a Master’s in Microelectronics Engineering, an MSc in Finance and Big Data, and is pursuing an Executive MBA at IESE Business School in Barcelona.

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SEMICON Japan 2025
2025-12-17 - 2025-12-19 | Tokyo Big Sight, 3 Chome-11-1 Ariake, Koto City, Tokyo, Japan
SEMICON Japan is the premier event that brings together the semiconductor manufacturing supply chain for the latest insights, trends and innovations as the industry powers digital transformation. SEMICON Japan 2025 will highlight Smart applications powered by semiconductor technology such as automotive and Internet of Things (IoT).
REGISTER HERE

Webinar: 5 Expectations for the Consumer Electronics Market in 2026
2025-12-16 11:00 - 12:00 | Online
December 16, 2025 – 11:00 AM EST
December 17, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Consumer Electronics Market Trends Reshaping Semiconductors in 2026
AI, tariffs, smart home, and display innovations—what’s next for consumer electronics.
The consumer electronics market is poised for transformation in 2026, driven by technology innovation, geopolitical dynamics, and rising consumer expectations for convenience, performance, and usability.
In this live TechInsights webinar, our consumer electronics experts will highlight five critical trends shaping the market, giving strategists, designers, and executives the insights needed to adapt, innovate, and lead.
Key Topics You’ll Learn

Transformer-Based AI Adoption – How device makers are using AI to enhance products and services.
Impact of US Import Tariffs – How tariffs affect both supply chains and consumer demand.
Matter Smart Home Standard – Advancements delivering true multi-brand interoperability.
Display Technology Innovations – How new approaches are transforming the smart TV market.
Momentum for Smart Glasses – AI-driven use cases and new entrants driving adoption.

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Webinar: Trained Eyes on 64G UCIe: Scale Chiplet Integration for AI
2025-12-10 09:00 - 10:00 | Online
Join us to hear firsthand from the innovators at Siemens and Alphawave Semi and learn proven practices to enhance your UCIe-enabled AI system performance!
The semiconductor industry is shifting rapidly from monolithic SoC design to chiplet-based systems. At the same time, AI compute workloads have pushed into petaflop-class speeds, demanding higher throughput from die-to-die (D2D) connectivity. 64G UCIe (Universal Chiplet Interconnect Express) delivers the performance, power, and area (PPA) advantages to meet the demands of tomorrow’s AI workloads. However, to achieve the performance for next-gen UCIe-based systems, design engineers face significant signal integrity challenges — from crosstalk and reflections to process variation.
This webinar will explore the emerging D2D connectivity applications, and the bandwidth demands that make 64G signaling a necessity. You’ll also learn how to:

Optimize system performance, power, and area (PPA) with best-in-class IP
Reduce design risks for advanced architectures with shift-left design methodologies
Ensure design intent translates into reliable hardware via simulation-to-silicon correlation

Who Should Attend:

Design engineers and system architects involved in designing, simulating, and validating chiplet-based systems — especially those tackling die-to-die (D2D) connectivity, UCIe integration, or seeking system-level PPA optimization.

Don’t miss out on this incredible chance to learn how to implement a comprehensive 64G UCIe design flow and participate in a live Q&A session! Register today to secure your spot.
REGISTER HERE

Meet the speakers

Alphawave Semi
Archana Cheruliyil
Principal Product Marketing Manager

Archana Cheruliyil is the Product Line Manager for HBM, D2D, and 3DIO IP at Alphawave Semi, where she drives the development of next-generation interface IP solutions and oversees marketing efforts. With a deep passion for identifying optimal solutions within the dynamic and complex landscape of AI systems, she works to address the evolving needs of customers. Archana is an invited speaker at conferences and panels on 3DIO interconnects and technology, where she shares insights on emerging trends and practical implementations in advanced packaging.
Previously, Archana served as the IP Strategy and Planning Lead at Intel Corporation, where she played a key role in defining and advancing the interface IP roadmap for both the Client and Data Center business units. She has over a decade of experience in analog mixed-signal design, specializing in high-speed clocking circuits, and has successfully led a matrixed engineering team to deliver cutting-edge IP on leading-edge process nodes.
Archana holds a Master of Science in Electrical Engineering (MSEE) from the University at Buffalo.

Siemens
Bryan McDevitt
Applications Engineer,

Bryan McDevitt is an Applications Engineer at Siemens EDA, where he has spent 18 years supporting board- and package-level simulations with the HyperLynx suite of tools. Before moving into applications engineering, he worked as an electrical engineer designing single board computers.

Siemens
Kendall Hiles
Sr. Product Specialist – 3D IC Packaging flow

Kendall Hiles is a Sr. Product Specialist for the 3D IC Packaging flow at Siemens Digital Industries Software, bringing over 40 years of comprehensive experience in electronics design and test engineering. He specializes in customizing EDA tools and developing sophisticated automated workflows that effectively bridge traditional design methodologies with cutting-edge packaging innovations and advanced semiconductor technologies. Throughout his extensive career, his expertise encompasses developing robust batch processing capabilities and establishing streamlined handoffs across the entire IC Packaging toolchain, ensuring efficient data flow and maintaining design integrity throughout complex multi-tool workflows. His current work includes pioneering automation solutions for creating system-level test vehicle daisy chains specifically designed for chiplet-based architectures, as well as developing comprehensive automated analysis capabilities for DC Drop power analysis, Loop PDN analysis, and high-frequency S-Parameter extractions for advanced IC package designs. Kendall’s innovative approaches have significantly improved design productivity while reducing time-to-market for complex packaging solutions, making him a recognized expert in the intersection of traditional PCB design and modern IC packaging technologies.

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AI Everywhere 2025
2025-12-10 - 2025-12-11 | Online
Description

In the data center, the shift to inference is in full swing. Infrastructure for inference is being built out at scale around the world in what Jensen Huang calls “AI factories,” optimized for the best possible tokens per dollar performance on a small but growing number of open-source LLMs. Sovereign AI efforts are also gaining momentum. Several chip companies in this market have become AI cloud service providers, shifting their business models to providing APIs for fast tokens, where they have an advantage versus Nvidia. Is now the time for data center inference-only chips to shine? What’s the limitation on tokens per second, and what are the avenues for chip and system design that can break these bottlenecks? And will cutting-edge techniques like reasoning and agentic AI drive demand for more tokens? ​
At the edge, tokens per watt is becoming a dominant metric as all kinds of appliances get the ability to communicate in natural language. However, the rollout of AI-powered vision and audio analytics technologies, as well as time series sensor data analytics applications, is also becoming widespread in industrial, automotive, healthcare, and consumer electronics. Are edge chips keeping pace with the demands of new open-source models, and how do techniques like reasoning and agentic AI apply at the edge? How do we support edge AI applications from R&D to deployment and throughout the product’s life cycle? What challenges remain for chip and system design in the spectrum of edge use cases, and how can we discourage fragmentation and encourage efficiency, usability, and portability?​
These topics and more will be explored during this two-day virtual conference on December 10-11.
More information about the conference agenda will follow soon.
What to expect?
With a conference space and resource center, AI Everywhere functions similarly to a live exhibition and conference. The technical conference will include keynotes, panel discussions and technical presentations on a variety of subjects, including significant technical trends, design ideas and new application areas. Along with the conference, there will be a resource center with microsites from relevant businesses that will include useful links and AI-focused technical materials available for download.
Who should attend?
This event will cater for AI system designers across the spectrum of AI use cases, embedded engineers and software developers, data scientists and anyone with an interest in AI hardware, software and system design. The aim is to present the latest in hardware and software for this extremely fast-moving sector and discuss the challenges that remain and how the industry should respond to them.
Contact

Are you interested in getting involved? Please see our details below
For Companies
We are offering sponsor packages to generate leads, raise brand awareness and participate in the conference and exhibition. If you would like more information about sponsorship opportunities, please contact: sales@aspencore.com
For Attendees
If you want to register for the event as an attendee and you have any questions, technical issues, or want a certificate of attendance please contact: events@events.mail.eetimes.com

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Webinar: Automate PCB documentation with BluePrint-PCB
2025-12-09 13:00 - 14:00 | Online
Streamlining fabrication and assembly documentation

December 9, 2025 at 06:00 AM Pacific Standard Time
December 9, 2025 at 01:00 PM Pacific Standard Time

BluePrint-PCB is a documentation automation tool that streamlines PCB fabrication, assembly, and inspection by generating intelligent, customizable electronic drawings directly from design data. BluePrint-PCB by Siemens integrates with PCB design workflows to produce comprehensive documentation packages tailored for fabrication and assembly processes. It supports direct imports from Siemens tools like Xpedition and PADS Professional, as well as industry-standard formats such as ODB++, IPC-2581, and PADS ASCII. Users can enhance documentation with additional formats including DXF, PDF, CSV, and JPEG.
Key capabilities include:

Automated drawing generation using drag-and-drop palettes for elements like drill charts, parts lists, and stackups, all populated with live design data.
Customizable documentation profiles that allow organizations to standardize symbols, tables, borders, and note blocks across teams.
Stackup Visualizer for interactive layer management, material assignment, and 3D visualization of PCB stackups and drill spans.
3D documentation export to Adobe PDF with interactive views, camera controls, and scrollable content.
Assembly panel design tools for creating optimized PCB arrays with features like mill tabs and fiducials.

A full set of Dimensioning tools; Auto Dim, Coordinate Dimensioning, Point to Point, and GD&T.
BluePrint-PCB enhances collaboration and reduces revision cycles by synchronizing all drawing content with the source PCB design file, ensuring accuracy and consistency throughout the documentation lifecycle.

Meet the speaker

Siemens
Ray Fugitt
Technical Marketing Engineer

Ray is a Technical Marketing Engineer at Siemens Digital Industries Software. He has 40 years of Printed circuit board experience, including 23 years at Downstream Technologies and 11 years at Hadco Corporation in Product and CAM engineering.
Starting on the Manufacturing floor in AOI and Electrical Test, He worked his way to the Engineering and CAM areas. Later he was CAM supervisor and was part of the move to Valor Genesis software.
He joined Downstream in technical marketing for CAM350 and later, technical sales positions. He has supported and provided training for the BluePrint PCB and CAM350 products for over 20 years. He continues in this role at Siemens Digital Industries Software.

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Webinar: 5 Expectations for the PC/Laptop/Tablet Market in 2026
2025-12-09 11:00 - 12:00 | Online
December 9, 2025 – 11:00 AM EST
December 10, 2025 – 10:00 AM JST/KST
Discover the 5 Critical PC/Laptop/Tablet Market Trends Reshaping Semiconductors in 2026
AI, tariffs, and processor innovations—what’s next for client computing markets.
The client computing market is entering a pivotal transition as post-COVID refresh cycles conclude. With a cooling tablet segment and the end of PC upgrades, replacement cycles are expected to reach historically low levels by 2026.
In this live TechInsights webinar, our experts will outline five critical developments shaping the PC, laptop, and tablet markets, providing actionable insights for strategists, designers, and executives navigating this dynamic landscape.
Key Topics You’ll Learn

Expansion of On-Device AI – Beyond integrated NPUs, discrete NPUs and GPUs will handle AI workloads alongside graphics processing.
Tariff-Related Pricing Impacts – How higher U.S. tariffs could depress demand or force vendors and retailers to absorb margins.
Mid-Market Opportunities – Vendors traditionally focused on high-end commercial and AI PCs may find untapped potential in underserved segments.
Alternative Processor Architectures – Chinese OEMs adopting HiSilicon Kirin processors and testing RISC-V may influence market dynamics.
Challenges to x86 Dominance – Arm processors from Qualcomm, Apple, and collaborations like NVIDIA-MediaTek could reshape the landscape.

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CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
2025-12-08 10:00 - 11:30 | Online
Speaker: Kee Tat Ong, Principal Application Engineer
10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure
11:00am~11:15am Q&A
Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to tape out the design which has not increased proportionately. This means there is reduced time to debug and optimize the circuit. Quantus Insight is a tool to quickly analyze a circuit and obtain insights of the parasitic resistances and capacitances affecting the design and a mechanism to do rapid experimentation on an extracted design. For the front-end designer, Quantus insight allows the designer to gain a better understanding of the source of parasitic and to perform a what-if analysis on the design. For back-end layout engineers, Quantus Insight allows them to visualize the parasitic devices so that they can modify the layouts to meet the design constraints set by circuit designers
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IEDM 2025 - 71st Annual IEEE International Electron Devices Meeting
2025-12-06 - 2025-12-10 | San Francisco, CA, San Francisco, CA, United States
100 YEARS of FETs: SHAPING the FUTURE of DEVICE INNOVATIONS

Inside IEEE IEDM 2025

Focus Sessions

Focus Session #1 – Efficient AI Solutions: Architecture, Circuit, and 3D Integration Innovations for Memory and Logic
Focus Session #2 – Beyond Silicon: The Invisible Revolution in Thin-Film Transistors
Focus Session #3 – From P-bits to Qubits: Classical, Quantum-Inspired and True Quantum Technologies for Computing
Focus Session #4 – Silicon Photonics for Energy Efficient AI Computing

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2025 GSA Awards Dinner Celebration
2025-12-04 16:00 - 19:30 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
GSA recognizes semiconductor companies that have demonstrated excellence through their success, vision, strategy and future opportunities in the industry at its annual Awards Dinner Celebration. It is an honor to be selected as a nominee and an even more distinguished achievement to win a GSA Award.
REGISTER HERE

Webinar: Simplify 1.6T Ethernet Testing: A New Way to Validate Interconnects
2025-12-04 10:00 - 11:00 | Online
As 1.6T Ethernet moves from concept to deployment, validating interconnects is more critical — and complex — than ever. But the challenge demands more than just speed — it’s proving performance in real-world conditions. Traditional test methods are slow and require manual intervention — adding complexity, longer development cycles, and gaps in validation.
In this webinar, you’ll learn how Keysight’s Interconnect and Network Performance Tester 1600GE (INPT-1600GE) and Interconnect Test System (ITS) software simplify validation. Together, they deliver accuracy, flexibility, and efficiency — all in an office-quiet, portable solution. You’ll also see a demonstration of the patented ITS Interconnect Library, which boosts productivity through automation.
You’ll gain practical strategies to:

Ensure reliability, stability, and interoperability of silicon chips, optical transceivers, active cables, and network equipment.
Reduce overhead costs with a streamlined platform designed for real-world testing.
Prepare for tomorrow with 212G bit error rate (BER) and forward error correction (FEC) validation.

Register today and learn how we can help you reduce test complexity to accelerate and simplify your validation process.

Presenters

Charles Seifert
Senior Manager, Product Management, Hardware Platforms, Keysight Technologies
As a senior manager in Keysight’s Network Applications & Security organization, Charles is responsible for Keysight’s Ethernet data communications test and measurement hardware systems spanning from 10Mbps to 1.6 Terabit Ethernet. Charles has 25 years of network testing and measurement experience, having worked in the industry since 2000.

Angela Grigoroaia
Software Architect, Network Test & Security, Keysight Technologies
Angela is the development lead for Keysight’s Interconnect Test System software. She has worked in the network test industry since 2011 and has extensive experience in designing, developing, and architecting industry-leading network test products such as IxNetwork and CyPerf, with a particular focus on making applications easy to automate.

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2025 TSMC Open Innovation Platform Ecosystem Forum - China
2025-12-04 | Shangri-La Nanjing, Shangri-La Nanjing, 329 Zhongyang Rd, Gulou, Nanjing, Jiangsu, 210009, China
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM
Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event; it’s a dynamic hub where the brightest minds converge to ignite the next wave of innovation.
As the AI revolution proliferates from the data center to the edge and becomes integrated into every application, the need for high-performance and energy-efficient designs is becoming paramount. Through a series of compelling, multi-track presentations, you’ll gain a firsthand understanding of how the ecosystem is collaboratively tackling these critical design requirements.
AI is also transforming how chip and multi-die designs are done. This year, the forum will highlight how the ecosystem is harnessing the immense potential of AI in next generation of design solutions for TSMC’s advanced process and packaging technologies. Prepare to be immersed in a wealth of knowledge as industry trailblazers and TSMC’s ecosystem partners offer valuable insights into the latest breakthroughs.
The event provides a unique opportunity for you to engage with thought leaders and innovators, whether you join in-person at locations across North America, Japan, Taiwan, China, and Europe, or participate online.
Don’t miss this opportunity to connect with the leading players of semiconductor technology and be part of shaping tomorrow’s innovations, today!
Opportunity to gain insights into

Solutions needed to address energy efficiency and other challenges impacting the next-generation AI chips and corresponding design flows and methodologies for TSMC A16™, N2, and N3 processes
Consistent progress in design enablement and solution development for TSMC’s advanced processes including A14, TSMC A16™ and N2
Latest advancements in design solutions on TSMC 3DFabric® chip stacking (including InFO, CoWoS®, TSMC-SoIC®, TSMC-SoW™), as well as updates on the TSMC 3DFabric Alliance
AI-assisted design flows for 2D and 3DIC design productivity and optimization
Design enablement technologies, IPs, and solutions targeting the latest HPC, AI/ML, automotive, mobile/5G and IoT applications
Comprehensive design solutions for specialty technologies including ultra-low power, ultra-low voltage, analog migration, RF, and mmWave
Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market

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PDF Solutions 2025 Users Conference & Analyst Day
2025-12-03 - 2025-12-04 | Santa Clara Marriott, Santa Clara, CA, United States
The semiconductor industry is experiencing accelerated innovation; demand has never been higher, complexity never greater, and the opportunities never more exciting. But realizing this potential requires partnerships, shared secure scalable solutions, and a collective commitment to pushing boundaries.
In this two-day conference, you’ll:

Hear from visionaries at Qualcomm, Intel, GlobalFoundries, STMicroelectronics, and SAP and many others.
We will demo breakthrough technologies in AI-driven manufacturing, equipment connectivity, and yield optimization.
We will present real case studies with measurable impact, from technology development to high-volume production, and from fabless to foundries and assembly and test.

This event is about sparking conversations, sharing hard-won insights, and building the relationships that will drive our industry forward.
Whether you’re focused on equipment integration, manufacturing analytics, test operations, or supply chain orchestration, you’ll find solutions, inspiration, and industry partners.
Learn about PDF Solutions, hear from industry leaders, explore the demo kiosks, ask the tough questions, share your own experiences, and connect with colleagues who share your passion for innovation and excellence.
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Webinar: 5 Expectations for the Advanced Packaging Market in 2026
2025-12-02 11:00 - 12:00 | This course will be held Online
December 2, 2025 – 11:00 AM EST
December 3, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Advanced Packaging Market Trends Reshaping Semiconductors in 2026
AI, 3D stacking, and next-gen substrates—what’s next for advanced packaging.
The advanced packaging industry is at the forefront of semiconductor innovation, driven by the explosive growth of AI and the increasing complexity of semiconductor designs. Executives and engineers must navigate transitions from traditional wafer-based processes to glass substrates, 3D stacking, and advanced thermal solutions to handle higher power densities.
In this live TechInsights webinar, our experts will highlight five critical developments shaping advanced packaging in 2026, providing actionable insights for strategists, designers, and executives looking to stay ahead of the curve.
Key Topics You’ll Learn

Co-Packaged Optics Go Mainstream – How integration of optics and electronics is redefining high-speed datacenter interconnects.
AI’s Appetite for HBM – Scaling high-bandwidth memory to meet AI accelerator demands.
Scaling Up for Panels and Glass – Transitioning from wafer to panel-scale substrates for next-gen packages.
Turning Up the Heat in 3D – Advanced thermal management solutions for increasingly complex 3D stacked packages.
A Mobile Reconfiguration: Chiplets in the Smartphone? – Exploring chiplet integration for smaller, high-performance mobile devices.

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CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio
2025-12-01 10:00 - 11:30 | Online
Speaker: Hong-Cheang Quek, AE Director
10:00am~11:00am iPegasus Verification System for Virtuoso Studio
11:00am~11:15am Q&A
Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence iPegasus Verification System delivers instant signoff quality design rule checks (DRC) to achieve higher quality layout from the Virtuoso Layout Suite. In addition to performing DRC/density checks using foundry-certified signoff rule decks, iPegasus is also generate metal fills using foundry-provided fill decks. Join this presentation to learn how iPegasus can boost your productivity and be easily adopted as part of your daily work.
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Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques
2025-11-25 11:00 - 12:00 | Online
Description
Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx Parameterized Macros (XPM) for seamless synchronization. Join us for a live demonstration and interactive Q&A to enhance your understanding of CDC challenges and solutions.
Presented by BLT, an AMD Premier Partner and Authorized Training Provider.
To see our complete list of webinars, visit our website: bltinc.com
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2025 TSMC Open Innovation Platform Ecosystem Forum - Amsterdam
2025-11-25 | Hilton Amsterdam Airport Schiphol, Hilton Amsterdam Airport Schiphol, Schiphol Boulevard 701, 1118 BN Schiphol Airport, Amsterdam, Netherlands
