SemiWiki

LID World Summit 2026
2026-06-23 - 2026-06-25 | Grenoble, France
CEA-Leti’s flagship event

Discover sustainable semiconductor breakthroughs to guide your roadmap from lab-to-market and to tomorrow’s AI factory at LID World Summit 2026.
Join industry leaders to discover groundbreaking innovation that will help meet technological goals for the healthcare, automotive, industrial, defense, and consumer-electronics sectors. Leave with confidence in the possible.

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Webinar: Americas Session | End-to-End Co-Design for Ethernet: Bridging Photonics and Electronics with EOE Simulation
2026-06-24 01:00 - 02:00 (America/Los_Angeles) | Online
About this event
This webinar shows how engineers can use a unified EOE simulation workflow in Keysight Advanced Design System (ADS) to co-design and validate high-speed Ethernet systems across both electronic and photonic domains for faster, more accurate development.

Who should attend this event?
Signal integrity engineers working on high-speed Ethernet links, Photonic design engineers developing optical transceivers and PICs, System architects in data center and AI infrastructure, Hardware design engineers involved in co-packaged optics (CPO) and pluggable modules, R&D teams focused on next-generation interconnect technologies.

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Synopsys Virtual Prototyping Day
2026-06-24 09:00 - 12:00 | Online
Join us for our 6th Annual Virtual Prototyping Day and learn how you can “shift left” your development cycle with virtual prototypes.
Highly complex SoC and muti-die designs are putting pressure on silicon and software development teams to meet time-to-market demands. Virtual prototypes are the answer to begin development earlier, reduce costs, collaborate across teams, and get your design to market faster.
This popular series features customers and partners who will present how they solve their design challenges using virtual prototypes.
This is an on-line event where you can attend from the convenience of your office, home, or anywhere you happen to be!
We have 2 specialized tracks designed to cater to the diverse interests and needs of our community:
Track 1 – System Architecture Design & Exploration
Optimize the efficiency and performance of complex systems by enabling early architecture design exploration and optimization. This approach helps in identifying potential issues and opportunities for improvement, ultimately leading to reduced development costs and faster time-to-market.
Track 2 – Software Development & Test
Enhance software development and testing with a virtual environment, where developers can simulate and validate system behavior without the need for physical hardware. This accelerates the development process, improves early detection of issues, and reduces costs associated with hardware dependencies and testing infrastructure.
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Webinar: Intel: Pushing EMIB Forward Design Methodology Insights with Synopsys Tools - SemiWiki
2026-06-25 09:00 - 10:00 | Online
Date: Jun 25, 2026 | 9:00 AM PST

In this webinar, Intel will present how EMIB (Embedded Multi‑die Interconnect Bridge) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share an EMIB reference methodology built on Synopsys 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump planning, automated die-to‑die routing for HBM and UCIe, and a unified exploration‑to-signoff data model help Intel manage system‑level co-design complexity while maintaining closure on timing, power, thermal, and SIPI. Intel will also discuss SIPI methodology using Synopsys Tools and EMIB’s ability to support dense, high‑speed HBM interfaces.
What you’ll learn

How EMIB addresses key multi-die design challenges
Why early bump planning is critical for EMIB success
How automated die-to-die routing accelerates convergence
How a unified flow supports scalable timing, power, thermal, and SIPI signoff
How EMIB enables high-speed HBM integration with confidence

Featured Speaker

Sadha Parasuraman
Design Methodology Architect and EDA Enablement Manager, Intel

Sadha Parasuraman is an EDA Enablement Manager and Design Methodology Architect for advanced design and customer enablement at Intel Foundry. Sadha’s Extensive experience in design flows and methodology stacks across semiconductor technologies.

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TSMC 2026 China Technology Symposium
2026-06-25 09:00 - 16:30 | Shanghai International Convention Center (SHICC), No.2727, Riverside Avenue, Pudong, Shanghai, 200120, China
Join us to get the latest on:

TSMC’s industry-leading HPC, Smartphones, IoT, and Automotive platform solutions
TSMC’s advanced logic technology progress on 3nm, 2nm, A16, A14 processes and beyond
TSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®, InFO, CoWoS®, and TSMC-SoW™
TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more
TSMC’s manufacturing excellence, capacity expansion plans, and green manufacturing achievements
TSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design

For more information on the TSMC Technology Symposium, e-mail us at: symposium@tsmc.com.
We look forward to seeing you at the TSMC 2026 Technology Symposium!
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Webinar: How Manufacturing Complexity Increased, and Why Validation Had to Evolve
2026-06-25 10:00 - 11:00 | Online
About this event
Engineering at the Edge Webinar Series – Episode 4
As semiconductor complexity increases and board designs become denser, manufacturing teams face tighter tolerances, reduced test access, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address.
Join Jason Kary, Senior Vice President and President of Keysight’s ElectronicIndustrial Solutions Group, to explore how manufacturing validation is evolving. You’ll learn how wafer-level and in-circuit test strategies improve coverage, detect defects earlier, and enable consistent, high-volume production at scale without compromising quality.

Who should attend this event?
Semiconductor and electronics manufacturing engineers should attend. This session fits teams focused on test coverage, yield improvement, and high-volume production validation.

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Scaling DRAM Technology to Meet Future Demands: System Challenges and Opportunities
2026-06-27 | Raleigh, North Carolina, Raleigh, NC, United States
Tutorial Abstract
Since the invention of the 1T1C bit cell more than 50 years ago, DRAMs have become the main memory of choice for processors in computing systems and consumer electronics devices. As new computing paradigms have been created, including AI, 3D graphics, HPC, cloud computing, and smart phones, specialized processors and DRAM memories have been developed that are optimized for these use cases. The same 1T1C DRAM bit cell is used in each of these applications, but the internal architecture and interfaces of the DRAMs supporting these markets are optimized in different ways, and the DRAMs are packaged differently (sometimes with additional buffer chips) to meet the needs of the system.
Across all markets, there is a relentless demand for higher performance and better power efficiency, as insufficient DRAM bandwidth can bottleneck application performance and interfaces to DRAMs can consume half of the SOC power. DRAMs are also being stressed by growing reliability concerns as they incorporate on-die ECC and mitigation for disturbance effects such as RowHammer and RowPress. As AI continues to grow across markets (HPC, server, client, mobile, etc.), the design of efficient, performant and reliable memory systems is becoming increasingly critical. AI models are continuing to grow, pushing the capacity and bandwidth requirements of DRAMs. Simply scaling with historical techniques will no longer achieve the required characteristics due to physical challenges, limits of process scaling, and system architecture constraints including thermals and power delivery.
This tutorial will describe DRAM architecture in detail, highlighting the similarities and differences between different DRAM technologies and the unique tradeoffs and design choices made to meet system needs. We will also cover the key components that memory transactions travel thorough to get to DRAMs and back, including memory controllers, PHYs, and where applicable, modules and buffer chips. We will describe the architecture of these critical components and discuss how DRAM architecture choices impact their performance and power efficiency. Standard scaling techniques for DRAMs will be highlighted along with challenges that the industry is currently facing. Input from industry experts will show the pros and cons of DRAM architecture choices, demonstrating the system impact and requirements for mainstream adoption. Future DRAM architectures will also be discussed.
Topics that will be covered
The tutorial will focus on DRAM architecture, specifically looking at design tradeoffs and subsequent impact to the overall system performance, power, cost and reliability. The tutorial will cover the following topics:

Background and History of DRAM markets. How they were historically defined, what changed, and the drivers of new technologies.
DRAM array architecture, internal data paths, shared structures, and interfaces.
The future of DRAM, including 3D DRAM cells.
Memory modules, including DIMMs, CAMMs, MRDIMMs, and CXL modules and their buffer chips.
Capacity, power, reliability, cost tradeoffs that motivate different DRAM architectures for different markets including computing, mobile, graphics, and AI. This will include underlying core architecture, packaging and system integration.
Power and energy differences between DRAM technologies.
Novel packaging techniques including stacking and 2.5D assembly.
Reliability, Availability, and Serviceability (RAS) techniques, including on-die error correction, system-level ECC, redundancy and repair, and RowHammer and RowPress mitigation.
Processing in memory that has been implemented in DRAM silicon.
Memory controller architecture and design challenges with current and future DRAMs.
PHY architectures and challenges with achieving higher data rates and power efficiencies.
System performance considerations, including latency under load and the impact of core timings and core architecture on performance.
Memory system architecture considerations to achieve maximum performance, highlighting the impact of DRAM core timing and architecture tradeoffs on the host controller design.
Industry adoption challenges facing new DRAM technologies and features.
Challenges for the future.

Organizers and Affiliations
Steven Woo is a Fellow and Distinguished Inventor at Rambus Inc., where he leads research in Rambus Labs on advanced memory systems for accelerators and computing infrastructure, and manages a team of senior architects. Since joining Rambus, Steve has worked in various roles leading architecture, technology, and performance analysis efforts, and in marketing and product planning roles leading strategy and customer programs.  He has more than 30 years of experience working on advanced memory systems and holds more than 100 US and international patents. Steve received his PhD and MS degrees in Electrical Engineering from Stanford University, and Master of Engineering and BS Engineering degrees from Harvey Mudd College.
Wendy Elsasser is a Technical Director of Research Science at Rambus Inc. She works in the Rambus Labs R&D division researching future system architecture and developing innovative solutions to address the challenges of the memory sub-system. She has over 25 years of experience in industry, starting with semi-custom micro-controller design, test, and implementation. Over the last 20 years, her focus has been on memory sub-systems, primarily external DRAM. Her experience includes DRAM controller architecture, design, and validation as well as active contributions to consortiums and standards bodies. Specifically, she was a leader in the Gen-Z consortium and JEDEC, helping to define future memory interfaces and DRAM standards. Her work has resulted in 15 patents.
Robert Palmer is a Senior Technical Director of Research Science at Rambus Inc., leading research in future memory module and memory buffer chip architectures. He has over 25 years of industry experience developing silicon IP and communication ICs, spanning the design of high-speed wireline transceiver circuits, serial link and memory controller PHY microarchitectures, and DDR and CXL memory buffer chip architectures and microarchitectures. In addition to his tenure at Rambus, Robert has held positions at Velio Communications and Nvidia Research. He holds over 60 US and international patents.
Taeksang Song is a Corporate Vice President at Samsung Electronics where he is leading a team dedicated to pioneering cutting-edge technologies including CAMM, MRDIMM, CXL memory expanders, fabric attached memory solutions and processing near memory to meet the evolving demands of next-generation data-centric AI architectures. He has 20 years of professional experience in memory and sub-system architecture, interconnect protocols, system-on-chip design and collaborating with CSPs to enable heterogeneous computing infrastructure. Prior to joining Samsung Electronics, he worked at Rambus Inc., Micron Technology and SK hynix in lead architect roles for the emerging memory controllers and systems. Taeksang received his PhD from KAIST, South Korea, in 2006. He has authored and co-authored over 20 technical papers and holds over 50 U.S. patents.
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ISCA 2026
2026-06-27 - 2026-07-01 | Raleigh Convention Center, Raleigh Convention Center, 500 Fayetteville St, Raleigh, NC, 27601, United States
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. In 2026, the 53rd edition of ISCA will be held in Raleigh at the Raleigh Convention Center from June 27 to July 1, 2026.
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ALD/ALE 2026
2026-06-28 - 2026-07-01 | JW Marriott Water Street, JW Marriott Water Street, 510 Water St, Tampa, FL, 33602, United States
Overview

The AVS 26th International Conference on Atomic Layer Deposition (ALD 2026) featuring the 13th International Atomic Layer Etching Workshop (ALE 2026) will be a three-day meeting dedicated to the science and technology of atomic layer controlled deposition of thin films and atomic layer etching. Since 2001, the ALD conference has been held alternately in the United States, Europe and Asia, allowing fruitful exchange of ideas, know-how and practices between scientists. The conference will take place Sunday, June 28-Wednesday, July 1, 2026, at the JW Marriott Water Street, Tampa, Florida.
As in past conferences, the meeting will be preceded (Sunday, June 28) by one day of tutorials and perspectives and a welcome reception. Sessions will take place (Monday-Wednesday, June 29-July 1) along with an industry tradeshow. All presentations will be audio-recorded and provided to attendees following the conference (posters will be included as PDFs). Anticipated attendance is 700+. View List of Invited Speakers

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Realize LIVE Europe 2026
2026-06-29 - 2026-07-01 | RAI Amsterdam Convention Centre, Europaplein 24, Amsterdam, 1078 GZ, Netherlands
Join us in 2026
We are ready to deliver more
1,800+ attendees. Join our community of users, industry experts and trusted partners. Realize LIVE offers something for everyone!
350+ sessions. Explore breakout sessions, technical tracks, trainings and more. More than 60% of sessions were led by customers, sharing real-world insights.
90% overall satisfaction rate. Realize LIVE is your digital transformation destination! Join our community and walk away a better user.

Accelerate your digital transformation journey

Learned from experts and industry leaders, built skills and discovered the latest trends and technology with more than 350+ sessions at Realize LIVE Europe.

Become a better user
Leave empowered — 88% of attendees left Realize LIVE Europe 2025 with new skills and enhanced tool proficiency.

Get inspired by thought leaders
In 2025 over 60% of sessions were led by customers, sharing real-world insights and innovations. You can expect even more in 2026.

Stay ahead with product roadmaps
Attendees will stay up-to-date with exclusive product presentations showcasing the latest advancements in Siemens technology, and hear about functionality updates, so you can plan for what comes next.

Gain exclusive hands-on training and certification
Attendees receive complimentary hands-on training, 60 days access to Siemens Xcelerator Academy and 20 lab hours. Plus, the opportunity to earn your Siemens Xcelerator Certification (€1000 value).

Connect and celebrate with product experts
Joined dedicated portfolio meet-ups, industry receptions and our Community Corner to connect with peers who are on their digital transformation journey. Don’t forget the evening events — a great chance to relax and network!

Dive into the Siemens ecosystem
Realize LIVE Europe is your destination for all things digital transformation. Meet experts, engage with partners and experience live demos in the Solutions Center.

REGISTER HERE

SMACD 2026
2026-06-29 - 2026-07-02 | Dresden, Germany, Dresden, Germany
Welcome to SMACD 2026
International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design
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CadenceCONNECT: Tech Days Europe 2026 - Leuven
2026-06-30 | Leuven, Belgium, Leuven, Belgium
Join us at CadenceCONNECT: Tech Days Europe 2026, our annual, free, multi-track event dedicated to the engineers, innovators, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows, boosting productivity, and enabling breakthroughs across every domain.
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Webinar: See it Before You Build it with VisionSym
2026-06-30 09:00 - 10:00 | Online
About this event
Join our upcoming webinar to discover how VisionSym transforms CAD models into photorealistic images using LightTools or LucidShape—eliminating the need for physical prototypes.
With GPU-accelerated ray tracing and photometrically accurate simulations, VisionSym enables both design verification and visual appearance evaluation in one streamlined workflow.
In this session, you’ll learn how to:

Validate designs against automotive regulations and OEM specs
Use photorealistic simulations to improve efficiency and accuracy

Who should attend this event?
Engineers and managers seeking faster, more integrated design workflows.

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Webinar: ImSym – Imaging System Simulator Discovery Training
2026-06-30 09:00 - 10:00 | Online
About this event
This discovery training introduces ImSym – Imaging System Simulator, an advanced platform for end-to-end imaging system simulation.
ImSym allows engineers to virtually prototype imaging systems by modeling the full image formation pipeline, from scene and optics through the detector and image signal processing. This enables earlier insight into real-world image performance and supports more efficient design decisions.
What You Will Learn:

Understand what ImSym is and the imaging challenges it addresses
Identify key components of the imaging system pipeline
Gain a high-level view of the ImSym interface and workflow
Understand the fundamentals of end-to-end image simulation

Who should attend this event?
This training is ideal for:

Optical and lens designers
Stray light engineers
System engineers
Imaging and optical engineers
Engineering managers evaluating imaging workflows

No prior ImSym experience required. A basic understanding of imaging systems or optics is recommended.

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CadenceCONNECT: Tech Days Europe 2026 - Barcelona
2026-07-02 | Barcelona, Spain, Barcelona, Spain

LucidShape User Group Meeting - North America
2026-07-21 09:00 - 17:00 | Novi, MI, Novi, MI, Novi, MI, United States
About this event
Join us for our annual LucidShape User Group Meeting— This year’s meeting brings together the LucidShape community for a day of insights, innovation, and collaboration. Whether you’re focused on automotive lighting, simulation workflows, or advanced design techniques, you’ll gain practical knowledge you can apply right away.
What You’ll Experience

Latest LucidShape Innovations
Discover new features and capabilities designed to enhance your optical design workflows.
Real-World Applications
Explore how LucidShape is used across lighting design applications—from concept to validation.
Technical Deep Dives
Learn more about simulation methods, modeling accuracy, and performance optimization.
Networking Opportunities
Connect with fellow users, industry peers, and the Keysight team.

Who should attend this event?
This event is ideal for:

Optical and lighting design engineers
Simulation and modeling specialists
Automotive lighting professionals
Anyone looking to deepen their expertise in LucidShape

Attendance is free, but space is limited. Secure your place today and join us in Novi for a valuable day of learning and connection.

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DAC 2026
2026-07-26 - 2026-07-29 | Long Beach Convention & Entertainment Center, 300 E Ocean Blvd, Long Beach, CA, 90802, United States
The Long Beach Convention Center will serve as a dynamic venue for DAC 2026: The Chips to Systems Conference. Set along the scenic Southern California coastline, the center offers modern meeting spaces and a vibrant setting that reflects the innovative spirit of DAC. Its central location in downtown Long Beach provides easy access to hotels, dining, and entertainment, making it an ideal hub for bringing together industry leaders, researchers, and practitioners to explore the future of design automation from chips to systems.

What is DAC?

Leading worldwide event for design engineering professionals since 1963

DAC: The Chips to Systems Conference DAC is where the future of electronic design takes shape. Each year, system architects, chip designers, engineers, researchers, and executives from 11,000+ organizations worldwide come together to learn, connect, and innovate. With over 60 expert-selected technical sessions and 150 exhibitors showcasing the latest in AI automated tools, EDA, and IP, DAC is the place to discover breakthrough ideas, build lasting connections, and stay at the forefront of the chip design industry. Don’t miss it.

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Realize LIVE Asia-Pacific 2026
2026-08-04 - 2026-08-05 | Bengaluru, India, Bengaluru, India
Where your digital transformation gets real — fast
We are excited to be visiting a new city with the Realize LIVE digital transformation conference to showcase artifial intelligence, digitalization, sustainability and optimization across the product lifecycle. Learn, network and connect with the Siemens software community, and walk away with new tools and insights for your digital journey.
Get a sneak peek of what you can expect!

Accelerate your digital transformation journey

Become a better user
Leave empowered — 85% of Realize LIVE event attendees leave with new skills and enhanced tool proficiency.

Become inspired by thought leaders
Realize LIVE participants become inspired after attending sessions led by customers and Siemens experts, who share real-world insights and innovations, leave event participants inspired.

Stay ahead with product roadmaps
Stay up-to-date with exclusive product presentations showcasing the latest advancements in Siemens technology, and preview upcoming updates to plan for what’s next.

Gain exclusive access to training and certification
Get 60 days of access to Siemens Xcelerator Academy, as well as a voucher to Siemens Xcelerator Certification (valid for six months).

Connect and celebrate with product experts
Join the Realize LIVE reception and dedicated meet-ups to connect with peers who are on their digital transformation journey.

Dive into the Siemens ecosystem
Realize LIVE is your destination for all things related to digital transformation. Meet experts; engage with partners; and experience live demos in the solutions center.

REGISTER HERE

AI Infra Summit 2026
2026-09-15 - 2026-09-17 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
What is the AI Infra Summit?

The AI Infra Summit is the premier full-stack AI Infrastructure conference, arranged in a modular way that equally enables both enterprises and technology/solution providers to benefit from domain-specific content, all while doing business on the exhibition floor. Our 4 track event is divided into Hardware & Systems, Edge AI Infrastructure, Enterprise AI, & Datacenter Infrastructure.
The AI Infra Summit takes place Tuesday – Thursday, 15-17 September 2026.
Registration opens at 9am, Keynotes begin 10am, Exhibition Hall opens 12:30pm.
The event takes place at the Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA 95054, United States.

REGISTER HERE

Global Photonics Economic Forum 2026
2026-09-24 - 2026-09-25 | Málaga, Spain, Málaga, Spain, Málaga, Spain
A Strategic Platform for Industry Leaders
The Third Edition of the Global Photonics Economic Forum will convene September 24 – 25 in Malaga, Spain. Building on the success of the 2024 and 2025 edition this year the forum will focus on defining and sharing joint strategies to tackle the current volatile geopolitical landscape.
Global photonics and semiconductor industries are facing unprecedented disruption. Rising trade barriers, escalating global tensions, and shifting industrial policies, such as the CHIPS Act and Europe’s strategic autonomy push, are fragmenting supply chains and inflating the cost of doing business. Export controls, investment restrictions, and localization mandates are no longer isolated events. For companies navigating this environment, resilience can no longer be built in isolation. Strategic alliances and cross-border collaboration are now essential to maintain access to critical markets, secure supply chains, and influence future standards.
There is no other forum exclusively dedicated to shaping the global economic future of optics and photonics technologies. It’s not just about the message, it’s about who delivers it. The GPEF brings you direct insights from billion-dollar CEOs and senior executives who are navigating these very challenges. Their collective experience, strategic vision, and real-world solutions will shape the conversations and collaborations that will define the future of our industry.
Photonics is at the center of several high-stakes global transitions, from AI compute demand and sustainable manufacturing to defense readiness and semiconductor sovereignty.
Global Photonics Economic Forum 2026 – Focus Areas

Navigating Geopolitical Trade Dynamics and Supply Chain Resilience

Understanding how global trade policies, strategic alliances, and regional initiatives (e.g., CHIPS Act, European Strategic Autonomy) impact photonics and semiconductor industries.
Exploring opportunities for Europe, Japan, Singapore, and other regions to strengthen global collaborations.

Scaling Photonics Innovations and Industrial Leadership

Sharing strategies for turning R&D breakthroughs into scalable, commercially viable technologies.
Insights from CEOs of billion-dollar corporations on market trends, industrial policies, and innovation roadmaps in photonics and semiconductors.

Strategic Investment, Entrepreneurship, and Economic Impact

Discussing venture capital perspectives, funding models, and pathways for start-ups and scale-ups.
Highlighting the economic impact of photonics in AI, Quantum, and Data-driven technologies over the next 25 years.

Defense, Security, and Critical Technologies for Global Stability

Examining the role of photonics in defense, security, and strategic industries.
Bridging innovation in photonics with global security needs and industrial resilience.

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Microelectronics UK 2026
2026-09-29 - 2026-09-30 | ExCeL London, Royal Victoria Dock, 1 Western Gateway, London, E16 1XL, United Kingdom
Microelectronics UK brings together engineers, technical leaders and technology providers from across the microelectronics ecosystem — spanning semiconductors, photonics and embedded systems — for two days of technical insight, collaboration and commercial connection.
Following a strong 2025 edition, the event showcases the UK’s world-class capabilities in R&D, design innovation and advanced manufacturing, while connecting the domestic supply chain with global partners, policymakers and end-users.
REGISTER HERE

User2User Mid-Atlantic 2026
2026-11-04 | Laurel, MD, Laurel, MD, United States
About User2User Mid-Atlantic

User2User Mid-Atlantic is focused around these areas:

Printed circuit board design (PCB) and design for manufacturing
PCB simulation
Application specific integrated circuit and field programmable gate array: advanced functional verification
Calibre design

Why attend User2User Mid-Atlantic 2026?
Learn
Peer-delivered technical sessions will cover a wide range of topics, so you can explore new concepts or dive deep into your core area of expertise with fellow like-minded professionals.
Connect
Network with like-minded peers and electronic design automation (EDA) industry leaders exploring macro trends, as well as super users sharing business challenges and solutions to their roadblocks.
Grow
EDA visionaries will share insights into global cross-industry challenges from companies who are optimizing their business using Siemens EDA tools.

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ICCAD 2026
2026-11-08 - 2026-11-12 | San Jose, CA
Call for Papers

Jointly sponsored by IEEE and ACM, IEEE/ACM ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. IEEE/ACM ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. IEEE/ACM ICCAD has a long-standing tradition of producing cutting-edge, innovative technical program for attendees.

REGISTER HERE
