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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260310
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T144804
CREATED:20250828T050840Z
LAST-MODIFIED:20250828T050840Z
UID:361050-1773100800-1773359999@semiwiki.com
SUMMARY:embedded world 2026
DESCRIPTION:Global platform for the embedded community\nThe embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \n\nThe No. 1 hub for the international embedded community\n\n\n\nAs the global platform and the industry place to meet for the embedded community\, embedded world attracts the top experts\, key players and industry associations from all over the world. \nBecome part of the community and use THE industry platform to network and make valuable business contacts! \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/embedded-world-2026/
LOCATION:Exhibition Centre Nuremberg\, Exhibition Centre Nuremberg\, Messezentrum 1\, Nürnberg\, 90471\, Germany
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/145-embedded-world-2026.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260309
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T144804
CREATED:20260107T032607Z
LAST-MODIFIED:20260107T032607Z
UID:365322-1773014400-1773359999@semiwiki.com
SUMMARY:GOMACTech 2026
DESCRIPTION:GOMACTech (Government Microcircuit Applications & Critical Technology Conference)\n“Beyond the Noise”\n\n\n\nGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews. \n\nREGISTER HERE
URL:https://semiwiki.com/event/gomactech-2026/
LOCATION:New Orleans Ernest N. Morial Convention Center\, New Orleans Ernest N. Morial Convention Center\, 900 Convention Center Blvd\, New Orleans\, LA\, 70130\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-06-192512.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260309
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T144804
CREATED:20250624T161151Z
LAST-MODIFIED:20250624T161151Z
UID:357528-1773014400-1773359999@semiwiki.com
SUMMARY:Semitracks Course: Semiconductor Reliability and Product Qualification
DESCRIPTION:Product reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past\, reliability meant discovering\, characterizing and modeling failure mechanisms\, and determining their impact on the reliability of the circuit. Today\, reliability can involve tradeoffs between performance and reliability; assessing the impact of new materials; dealing with limited margins\, and other factors. This requires information on subjects like: statistics\, testing\, technology\, processing\, materials science\, chemistry\, and customer expectations. While customers expect high reliability levels\, incorrect testing\, calculations\, and qualification procedures can severely impact reliability. Semiconductor Reliability and Product Qualification is a 4-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and qualification. This course is designed for every manager\, engineer\, and technician concerned with reliability in the semiconductor field\, qualifying semiconductor components\, or supplying tools to the industry. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what failure mechanisms might occur\, and how to test for them\, develop models for them\, and eliminate them from the product. This skill building series is divided into four segments: \n\nOverview of Reliability and Statistics. Participants will learn the fundamentals of statistics\, sample sizes\, distributions and their parameters.\nFailure Mechanisms. Participants will learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die and at the package level. These include: time-dependent dielectric breakdown\, hot carrier degradation\, electromigration\, stress-induced voiding\, moisture\, corrosion\, contamination\, thermomechanical effects\, interfacial fatigue\, and others.\nQualification Principles. Participants will learn how test structures can be designed to help test for a particular failure mechanism.\nTest Strategies. Participants will learn about the JEDEC test standards\, how to design screening tests\, and how to perform burn-in testing effectively.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the failure mechanisms\, test structures\, equipment\, and testing methods used to achieve today’s high reliability components.\nParticipants will be able to gather data\, determine how best to plot the data and make inferences from that data.\nThis course will identify the major failure mechanisms\, explain how they are observed\, how they are modeled\, and how they are eliminated.\nThis course will offer a variety of video demonstrations of analysis techniques\, so the participants can get an understanding of the types of results they might expect to see with their equipment.\nParticipants will be able to identify the steps and create a basic qualification process for semiconductor devices.\nParticipants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.\nParticipants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-semiconductor-reliability-and-product-qualification/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260303T100000
DTEND;TZID=America/Los_Angeles:20260303T110000
DTSTAMP:20260403T144804
CREATED:20260210T181806Z
LAST-MODIFIED:20260212T175607Z
UID:366569-1772532000-1772535600@semiwiki.com
SUMMARY:Webinar: Intelligent Networks: Power\, Reliability & Maintenance in Telecom
DESCRIPTION:About\nAs global connectivity demands surge\, network infrastructure hardware is under unprecedented pressure to deliver higher performance\, lower latency\, and greater energy efficiency\, while remaining cost-effective and reliable. This challenge is compounded with the explosive growth of AI applications\, emerging 5G and 6G architectures\, virtualization and open interfaces\, adding further strain on legacy systems and supply chains that were never built for this pace of evolution. As reliability remains the primary KPI\, providers must shift from a reactive replacement model to a predictive maintenance model. \nJoin our panel of industry experts as they explore the multidimensional challenges of designing\, deploying\, and maintaining network infrastructure in this new era\, focusing on: \n• Power efficiency and thermal optimization across silicon\, networks\, and data centers\n• Proactive monitoring and predictive analytics\n• Requirements for HW and SW co design in next generation architectures\n• Balancing sustainability goals with total cost of ownership \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intelligent-networks-power-reliability-maintenance-in-telecom/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/1770674564867.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T144804
CREATED:20260107T032340Z
LAST-MODIFIED:20260107T032340Z
UID:365317-1772409600-1772755199@semiwiki.com
SUMMARY:22nd Annual Device Packaging Conference (DPC 2026)
DESCRIPTION:The 22nd Annual Device Packaging Conference (DPC 2026) will be held in Phoenix\, Arizona\, on March 2-5\, 2026. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS). The conference is a major forum for the exchange of knowledge and provides numerous technical\, social and networking opportunities for meeting leading experts in these fields. People who will benefit from this conference include: scientists\, process engineers\, product engineers\, manufacturing engineers\, professors\, students\, business managers\, and sales & marketing professionals. The 2026 conference will feature 4 keynote presentations\, an embedded Global Business Council Plenary Session\, an interactive poster session\, an evening panel discussion\, and more. \nREGISTER HERE
URL:https://semiwiki.com/event/22nd-annual-device-packaging-conference-dpc-2026/
LOCATION:Sheraton Grand at Wild Horse Pass\, Sheraton Grand at Wild Horse Pass\, 5594 W Wild Horse Pass Blvd.\, Phoenix\, AZ\, 85226\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/imaps-DP-2026-logo.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T144804
CREATED:20251211T212817Z
LAST-MODIFIED:20251211T212817Z
UID:364624-1772409600-1772755199@semiwiki.com
SUMMARY:MWC 2026
DESCRIPTION:Making way for The IQ Era\n\nMuch can happen in a year within our ecosystem of innovation and connectivity. As we build on the success of MWC25 and engage with MWC26 to activate a new theme – The IQ Era – the world is already shifting to greater heights of digital awareness. \nIn this new age of intelligence\, the way to a better future is through smarter connection: human ideas leading technology\, commercial impact and societal progress. MWC is where leaders of nations\, business and technology assemble\, and collective knowledge collaborates – make your insight count in The IQ Era. \nWhy attend MWC Barcelona?\nFrom eye-opening innovation to mind-expanding ideas\, global policy to lasting partnerships\, it all starts here. Whether you’re a key player in the connectivity ecosystem\, adjacent industries or the wider world of tech\, you’ll find all you need and more at MWC. \n\nREGISTER HERE
URL:https://semiwiki.com/event/mwc-2026/
LOCATION:Fira Gran Via\, Barcelona\, Fira Gran Via\, Av. Joan Carles I\, 64\, Barcelona\, 08908\, Spain
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2025/12/MWC26_hero_Card_800x533.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T144804
CREATED:20250828T050601Z
LAST-MODIFIED:20251218T210957Z
UID:361044-1772409600-1772755199@semiwiki.com
SUMMARY:DVCON U.S. 2026
DESCRIPTION:DVCon is the premier conference on the application of languages\, tools\, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog\, Verilog\, VHDL\, PSS\, SystemC and e\, as well as general purpose languages such as C\, C++\, Python\, PERL and Tcl. Tools and methodologies include the use of artificial intelligence\, machine learning\, open-source software\, hardware and architecture\, testbench automation\, hardware-assisted verification\, hardware/software co-verification\, formal verification\, functional safety and security\, transaction-level system design\, high level synthesis\, low power design techniques\, 3D chip designs\, IP-based SoC design methods\, reference flows and Mixed Signal design and verification. \nREGISTER HERE
URL:https://semiwiki.com/event/dvcon-u-s-2026/
LOCATION:Hyatt Regency Hotel\, Santa Clara\, CA\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-220509.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T144804
CREATED:20250624T160157Z
LAST-MODIFIED:20250624T160157Z
UID:357520-1772409600-1772755199@semiwiki.com
SUMMARY:Semitracks Course: Failure and Yield Analysis
DESCRIPTION:Failure and Yield Analysis is an increasingly difficult and complex process. Today\, engineers are required to locate defects on complex integrated circuits. In many ways\, this is akin to locating a needle in a haystack\, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design\, testing\, technology\, processing\, materials science\, chemistry\, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. Failure and Yield Analysis is a 4-day course that offers detailed instruction on a variety of effective tools\, as well as the overall process flow for locating and characterizing the defect responsible for the failure. This course is designed for every manager\, engineer\, and technician working in the semiconductor field\, using semiconductor components or supplying tools to the industry. \nBy focusing on a Do It Right the First Time approach to the analysis\, participants will learn the appropriate methodology to successfully locate defects\, characterize them\, and determine the root cause of failure. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what tools and techniques should be applied\, and when they should be applied. This skill-building series is divided into three segments: \n\nThe Process of Failure and Yield Analysis. Participants will learn to recognize correct philosophical principles that lead to a successful analysis. This includes concepts like destructive vs. non-destructive techniques\, fast techniques vs. brute force techniques\, and correct verification.\nThe Tools and Techniques. Participants will learn the strengths and weaknesses of a variety of tools used for analysis\, including electrical testing techniques\, package analysis tools\, light emission\, electron beam tools\, optical beam tools\, decapping and sample preparation\, and surface science tools.\nCase Histories. Participants will identify how to use their knowledge through the case histories. They will learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the tools\, techniques and processes used in failure and yield analysis.\nParticipants will be able to determine how to proceed with a submitted request for analysis\, ensuring that the analysis is done with the greatest probability of success.\nThis course will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.\nThis course will offer a wide variety of video demonstrations of analysis techniques\, so the analyst can get an understanding of the types of results they might expect to see with their equipment.\nParticipants will be able to identify basic technology features on semiconductor devices.\nParticipants will be able to identify a variety of different failure mechanisms and how they manifest themselves.\nParticipants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-failure-and-yield-analysis-2/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260226T150000
DTEND;TZID=America/Los_Angeles:20260226T160000
DTSTAMP:20260403T144804
CREATED:20260217T205841Z
LAST-MODIFIED:20260217T205841Z
UID:366792-1772118000-1772121600@semiwiki.com
SUMMARY:GCU and TSMC’s MSI Pathway Webinar
DESCRIPTION:Description\nThis virtual session is your opportunity to explore Grand Canyon University and TSMC’s one-semester Manufacturing Specialist Intensive\, industry funded pathway. Join to find out how you can start building your future in semiconductor manufacturing trades. Whether you’re looking to upskill\, change career paths\, or take the first step toward hands-on training\, our team will walk you through program details and the enrollment process — all from the comfort of your home. \nBy clicking submit\, you give Grand Canyon University your consent to use automated technology to call and text you at the information above\, including your wireless number\, regarding educational services. You are not required to consent to receive educational services. GCU will never sell your information. By submitting this form\, you agree to GCU’s Privacy Policy located at https://www.gcu.edu/privacy-policy.php. \nREGISTER HERE
URL:https://semiwiki.com/event/gcu-and-tsmcs-msi-pathway-webinar/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/02/c6a6e7ff-26ac-43e0-befa-d87f76d02722.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260224
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T144804
CREATED:20260210T182526Z
LAST-MODIFIED:20260210T182526Z
UID:366572-1771891200-1772150399@semiwiki.com
SUMMARY:DesignCon 2026
DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers\n\n\n\n\nDesignCon is the premier high-speed communications and system design conference and exposition\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. \n\n\nThe Conference – A Systematic Approach to Learning & Discovery\n\n\n\n\nAttend the expertly curated 15-track conference created by engineers for engineers featuring technical paper sessions\, tutorials\, and industry panels covering all aspects of chip\, board\, and systems design. \n» View Full Conference Agenda\n» View All Speakers \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/designcon-2026/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/Screenshot-2026-02-10-102443.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260224
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T144804
CREATED:20250828T050143Z
LAST-MODIFIED:20250828T050143Z
UID:361040-1771891200-1772150399@semiwiki.com
SUMMARY:FLEX 2026 - Technology Summit
DESCRIPTION:FLEX 2026 | TECHNOLOGY SUMMIT | FEBRUARY 24-26\, 2026\nTHE WIGWAM ARIZONA RESORT | PHOENIX\, AZ\nA 25th Anniversary Celebration \nEscape the winter and celebrate 25 years of innovation with us at The Wigwam Arizona Resort in Phoenix\, AZ. \n\nFLEX—Technology Summit is a vibrant networking event designed to foster community building. Connect with like-minded professionals\, share ideas\, and forge lasting relationships that will drive the industry forward. \nAt FLEX\, you’ll experience high-quality technical sessions led by industry-leading speakers who are at the forefront of their fields. Sessions include topics on wearable and harsh environment technologies\, heterogeneous integration and advanced packaging\, flexible hybrid electronics\, printed electronics\, additive manufacturing\, integrated photonics\, flexible displays\, digital twins\, artificial intelligence\, and manufacturing. Additionally\, you’ll gain valuable business insights and market trends that provide a comprehensive view of the state of the industry. \nExplore the solution zone to see cutting-edge technologies and connect with innovations shaping the future. Don’t miss this chance to stay ahead in a rapidly evolving tech landscape. \nREGISTER HERE
URL:https://semiwiki.com/event/flex-2026-technology-summit/
LOCATION:The WIGWAM\, The Wigwam\, 300 E Wigwam Blvd\, Litchfield Park\, AZ\, 85340\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-220051.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260223
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T144804
CREATED:20250624T160729Z
LAST-MODIFIED:20250624T160729Z
UID:357524-1771804800-1772150399@semiwiki.com
SUMMARY:Semitracks Course: Wafer Fab Processing
DESCRIPTION:Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is a 4-day course that offers an in-depth look into the semiconductor manufacturing process\, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique\, and we delve into the current issues related to manufacturing the next generation devices. This course is a must for every manager\, engineer and technician working in the semiconductor industry\, using semiconductor components or supplying tools to the industry. \nBy focusing on the basics of each processing step and the issues surrounding them\, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn basic\, but powerful\, aspects about the semiconductor industry. This skill-building series is divided into three segments: \n\nBasic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. Participants will learn the fundamentals of each processing step and why they are used in the industry today.\nThe Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants will learn how each technique has evolved for use in previous and current generation ICs.\nCurrent Issues in Wafer Fab Processing. Participants will learn how many processing steps are increasingly constrained by physics and materials science. They will also learn about the impact of using new materials in the fabrication process\, and how those materials may create problems for the manufacturers in the future.\n\nThis course is a must for every manager\, engineer\, and technician working in the semiconductor industry\, using semiconductor components\, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline. \n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.\nParticipants will understand the basic concepts behind the fundamental wafer fab processing steps.\nThis course will identify the key issues related to each of the processing techniques\, and their impact on the continued scaling of the semiconductor industry.\nThis course will offer a wide variety of sample problems that participants will work to help them gain knowledge of the fundamentals of wafer fab processing.\nParticipants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition\, ion implantation\, lithography\, and etching.\nParticipants will understand how processing\, reliability\, power consumption and device performance are interrelated.\nParticipants will be able to make decisions about how to construct and evaluate processing steps for CMOS\, BiCMOS\, and bipolar technologies.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-wafer-fab-processing-2/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260223
DTEND;VALUE=DATE:20260226
DTSTAMP:20260403T144804
CREATED:20251219T205158Z
LAST-MODIFIED:20251219T205158Z
UID:364923-1771804800-1772063999@semiwiki.com
SUMMARY:2026 Florida Semiconductor Summit
DESCRIPTION:FSI presents the 4th annual Florida Semiconductor Summit in 2026. Join industry leaders\, innovators\, and exhibitioners as we explore groundbreaking developments and the evolving future of semiconductor manufacturing in Florida.\nYou’re invited to the 2026 Florida Semiconductor Summit! From February 23rd – 25th\, 2026\, the Florida Semiconductor Institute is hosting the fourth annual Florida Semiconductor Summit at the Rosen Shingle Creek. This year’s summit theme is “Semiconductor Manufacturing in Florida: Power. Progress. Possibilities.” This summit offers a unique opportunity to connect with industry leaders\, explore cutting-edge advancements\, and delve into the evolving role of semiconductor manufacturing in the state of Florida. \nWhat Makes this Year’s Summit the Biggest Yet?\nThis year\, we are taking the summit to the next level! Not only are we bringing together industry leaders from top CEOs to leading academics\, we are bringing together rising startups and industry pioneers who are shaping the future of semiconductor technology in our first ever interactive exposition hall. This is your chance to connect with key decision-makers\, gain insights from cutting-edge research\, and explore new business opportunities in one of Florida’s fastest-growing sectors. The summit offers invaluable networking\, knowledge-sharing\, and a front-row seat to innovations that will have deep impacts on the state of Florida. Don’t miss out\, register today! \nREGISTER HERE
URL:https://semiwiki.com/event/2026-florida-semiconductor-summit/
LOCATION:Rosen Shingle Creek\, Rosen Shingle Creek\, 9939 Universal Blvd\, Orlando\, FL\, 32819\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Outlook-3vvtmdsn.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260222
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T144804
CREATED:20250828T045847Z
LAST-MODIFIED:20250828T045847Z
UID:361037-1771718400-1772150399@semiwiki.com
SUMMARY:SPIE Advanced Lithography + Patterning 2026
DESCRIPTION:From materials to metrology: pushing the limits of lithography\nShare your research\, challenges\, and breakthroughs at this leading semiconductor conference in San Jose \nSubmit your abstract and connect with leading researchers advancing solutions in optical lithography\, EUVL\, patterning technologies\, metrology\, and process integration for semiconductor manufacturing and related applications. \nCall for papers is now open. \nREGISTER HERE
URL:https://semiwiki.com/event/spie-advanced-lithography-patterning-2026/
LOCATION:San Jose McEnery Convention Center\, San José McEnery Convention Center\, 150 W San Carlos St\, San Jose\, CA\, 95113\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-215756.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260219
DTEND;VALUE=DATE:20260221
DTSTAMP:20260403T144804
CREATED:20250624T160935Z
LAST-MODIFIED:20250624T160935Z
UID:357526-1771459200-1771631999@semiwiki.com
SUMMARY:Semitracks Course: Defect-Based Testing
DESCRIPTION:Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example\, today’s application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately\, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease\, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior\, fault models\, and test techniques. This course is a must for every manager\, engineer\, and technician working in IC test\, IC design\, or supplying test hardware and software tools to the industry. \nBy focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior\, participants will learn how to design\, write\, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn basic\, but powerful\, aspects about defect-based testing. This skill-building series is divided into four segments: \n\nElectrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits\, resistive vias\, shorts\, and transistor variations affect the electrical behavior of the individual transistor\, as well as gate elements and larger blocks.\nFault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models\, including IDDQ testing\, at-speed testing\, and delay testing.\nProduction Test Methods. Participants will learn about standard digital testing\, SAF testing\, IDDQ\, timing\, low voltage tests\, and other types of stress tests. They will explore the strengths and weaknesses of each test type.\nThe Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of defect-based testing and its technical issues.\nParticipants will understand the basic concepts of test economics\, yield\, test time\, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.\nThis course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.\nThis course will offer the opportunity to discuss specific test problems with our expert instructors.\nParticipants will be able to identify basic and advanced principles for defect-based test.\nParticipants will understand the difficulties in extending IDDQ testing to leading edge products\, and how to overcome some of these limitations.\nParticipants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.\nThis course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.\nParticipants will learn what tools are available today to implement defect-based testing.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-defect-based-testing/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260218
DTEND;VALUE=DATE:20260221
DTSTAMP:20260403T144804
CREATED:20250828T045643Z
LAST-MODIFIED:20250828T045643Z
UID:361034-1771372800-1771631999@semiwiki.com
SUMMARY:Wafer-Level Packaging Symposium 2026
DESCRIPTION:Formatting Advanced Packaging for the Next Generation\nThe evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically\, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless\, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package technologies beyond conventional limits. The Wafer-Level Packaging Symposium will bring together the foremost experts in the semiconductor industry to examine all aspects of wafer and panel-level packaging\, 3D device packaging\, advanced manufacturing\, and testing technologies. Positioned at the forefront of packaging technology evolution\, this conference offers global attendees the chance to engage with the latest technological and business trends in the heart of Silicon Valley. \nREGISTER HERE
URL:https://semiwiki.com/event/wafer-level-packaging-symposium-2026/
LOCATION:Hyatt Regency San Francisco Airport\, 1333 Bayshore Highway\, Burlingame\, CA\, 94010\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/WLPS_2026_Masthead.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260217T100000
DTEND;TZID=America/Los_Angeles:20260217T110000
DTSTAMP:20260403T144804
CREATED:20260113T043754Z
LAST-MODIFIED:20260113T043754Z
UID:365670-1771322400-1771326000@semiwiki.com
SUMMARY:Webinar: How Secure Are Your Critical Aerospace & Defense Systems?
DESCRIPTION:Aerospace\, defense\, and other mission-critical technologies face rapidly evolving hardware threats. A hobbyist can add a single board computer to a consumer device. A nation-state can scale an exploit across critical infrastructure. The attack surface widens fast\, and the security implications are real. \nAdversaries are continuously developing techniques that can compromise mission-critical components\, sometimes before they even reach deployment. From side-channel analysis to fault injection\, attackers are finding new ways to extract sensitive data\, disrupt operations\, and manipulate critical systems. \nJoin us for a technical deep dive into how modern hardware attacks work in practice and what engineering teams can do to build more resilient systems. \nIn this session\, we’ll cover: \n\nReal attack examples on complex systems\, like satellite terminals and commercial drones.\nHow side-channel analysis techniques reveal power\, electromagnetic\, and unintended RF leakage that expose cryptographic operations.\nHow fault injection induces glitches to bypass authentication and break security logic.\n\nYou’ll also see a demo of our Fault Injection Laser System with our Inspector software. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-secure-are-your-critical-aerospace-defense-systems/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203709.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260217
DTEND;VALUE=DATE:20260220
DTSTAMP:20260403T144804
CREATED:20250828T045454Z
LAST-MODIFIED:20250828T045454Z
UID:361030-1771286400-1771545599@semiwiki.com
SUMMARY:Chiplet Summit 2026
DESCRIPTION:All the Solutions for Developing Chiplets\n2025 Keynote Addresses from Industry Leaders: \nAlphawave Semi\, Arm\, Cadence Design Systems\, Keysight\, Open Compute Project\, Synopsys\, Teradyne \n2025’s Main Topics Included: \nAI/ML Acceleration\, Open Chiplet Economy\, Advanced Packaging Methods\, Die-to-die Interfaces\, Working with Foundries \nsignup to be a 2026 SPONSOR / Exhibitor \nREGISTER HERE
URL:https://semiwiki.com/event/chiplet-summit-2026/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/cropped-Chiplet-Logo.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260215
DTEND;VALUE=DATE:20260220
DTSTAMP:20260403T144804
CREATED:20250828T045208Z
LAST-MODIFIED:20250828T045208Z
UID:361021-1771113600-1771545599@semiwiki.com
SUMMARY:2026 IEEE International Solid-State Circuits Conference (ISSCC)
DESCRIPTION:About ISSCC\nThe International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts. \nWhat’s New\n\nDownload the ISSCC 2026 Plenary/Educational Events Flyer\nThe ISSCC 2026 paper submission site is now open\nDownload the ISSCC 2026 Call for Papers\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/2026-ieee-international-solid-state-circuits-conference-isscc/
LOCATION:San Francisco Marriott Marquis\, San Francisco Marriott Marquis\, 780 Mission Street\, San Francisco\, CA\, 94103\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-215048.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260211
DTEND;VALUE=DATE:20260214
DTSTAMP:20260403T144804
CREATED:20260107T031917Z
LAST-MODIFIED:20260107T031917Z
UID:365313-1770768000-1771027199@semiwiki.com
SUMMARY:SEMICON Korea 2026
DESCRIPTION:Date: Feburary 11-13\, 2026\nHours\n\nFebruary 11\, 2026 | 10:00-17:00 (Last entry 16:30)\nFebruary 12\, 2026 | 10:00-17:00 (Last entry 16:30)\nFebruary 13\, 2026 | 10:00-16:00 (Last entry 15:30)\n\nVenue\n\nCOEX (Hall A\, B\, C\, D\, E\, Grand Ballroom\, Platz and ASEM Ballroom)\nWestin Seoul Parnas\nGrand InterContinental Seoul Parnas\n\nScale\n\n550 Exhibitors\, 2411 booths (2025: 501 exhibitors\, 2301 booths)\n\nHighlights\nGlobal Supply Chain \nOver 550 semiconductor companies from around the world will participate with 2\,411 booths\, welcoming 70\,000 attendees. \nKeynote Speech \nLeaders in the semiconductor industry will provide valuable insights for the future. \nTech Conferences \nAt 30 technology programs\, 200 visionaries will share the most noteworthy tech trends shaping the industry. \nBusiness Programs \nInvestment forums will be held to explore investment opportunities in countries such as the United States and Netherlands. \nSupplier Search Program \nTo support the global expansion of Korea’s semiconductor materials\, components\, and equipment companies\, around 100 business meetings will be conducted with major chip makers. \nWorkforce Development \nMentoring programs for university students aspiring to pursue careers in the semiconductor industry will be offered. \n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semicon-korea-2026/
LOCATION:COEX Auditorium\, 513\, Yeongdong-daero\, Seoul\, Gangnam-gu\, 06164\, Korea\, Republic of
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/images.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260210T110000
DTEND;TZID=America/Los_Angeles:20260210T120000
DTSTAMP:20260403T144804
CREATED:20260107T111533Z
LAST-MODIFIED:20260107T111533Z
UID:365423-1770721200-1770724800@semiwiki.com
SUMMARY:Webinar: Meet Compact-Q DEER Spectrometer\, Your Gateway to Quantum Innovation
DESCRIPTION:Intro\n\n\n\n\n\n\n\nThe Compact-Q DEER Spectrometer is designed to support researchers in academia and industry to efficiently characterize quantum materials\, develop devices for quantum sensing\, advance and validate algorithms to control qubits\, and other applications in spin-based quantum technologies. The Compact-Q DEER system features a modern microwave architecture\, high-resolution AWG\, and digital signal processing schemes enabling high flexibility in addressing modern challenges of quantum technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\nWebinar Overview\n\n\n\n\n\n\n\nThe focus of this webinar will be to highlight the capabilities of the Compact-Q DEER spectrometer towards the characterization and coherent control of qubits for quantum technologies. Modern experiments in Quantum Information Science (QIS) demand a state-of-the-art microwave architecture\, fast\, high-memory\, high-resolution AWGs\, large transmission and detection bandwidths\, and modern digital signal processing features to create the most sophisticated pulse shapes\, quantum gates and read-out sequences. Having all of those features incorporated\, as well as operating at an intermediate frequency of 500 MHz\, and utilizing a cryogen-free 1.5 T magnet with integrated Variable Temperature Insert (iVTI) enabling temperatures from 2 K to RT\, the Compact-Q system meets modern demands and provides a versatile and high-fidelity platform for probing qubit properties and execution of quantum algorithms driving innovations in quantum technologies. \n\n\n\n\nWhat to Expect\n\n\n\n\n\n\n\nDuring this webinar\, we will demonstrate how the Compact-Q DEER is ideally suited for applications in QIS. We will show how broad-band echo sequences can be used to manipulate spin states and how electron spin coherences can be created and detected. We will explain the different spectrometer features\, the data acquisition platform along with different experiments\, highlighting how the Compact-Q can elevate your research in quantum information science (QIS). \n\n\n\n\n\n\n\n\n\n\n\n\n\nKey Learning Points\n\n\n\n\n\n\n\nVersatility\, high-performance\, and user-friendly operation of the Compact-Q DEER spectrometer will be highlighted along with: \n\nEasy to use resonator bandwidth control\nAWG generated pulses\, digital down conversion\, and FIR filtering\nPulse shaping and quantum gate optimization\nBroadband and selective inversion pulse schemes\nStudying spin dephasing mechanisms and materials characterization\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend?\n\n\n\n\n\n\n\n\nUndergraduate and graduate students in chemistry\, physics\, quantum information science\, material science\, and related fields\nEarly-career researchers\, postdoctoral fellows\, and instrument facility managers familiar or new to EPR spectroscopy\nProfessors and instructors teaching EPR spectroscopy or related courses\nSpectroscopy facility managers\nIndustry professionals\, scientists\, and engineers in materials science and quantum technologies industries\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-meet-compact-q-deer-spectrometer-your-gateway-to-quantum-innovation/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-031446.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260205T100000
DTEND;TZID=America/Los_Angeles:20260205T120000
DTSTAMP:20260403T144804
CREATED:20260113T043349Z
LAST-MODIFIED:20260113T043349Z
UID:365667-1770285600-1770292800@semiwiki.com
SUMMARY:Demo Day — Signal Generators
DESCRIPTION:Join us for Demo Day – Signal Generators and discover how to accelerate and optimize RF testing with the capabilities offered by these instruments in our test bench.  \nLearn how to perform power amplifier matching correction with a signal generator’s integrated reflectometer in minutes… not hours. No additional test equipment required. \nWe will also demonstrate how the multi-port capabilities of the generators enhance critical applications such as coexistence testing optimization\, beamforming \, and MIMO (multiple-input\, multiple-output) spatial multiplexing. The platform delivers precise signals synchronized in frequency\, phase\, and time\, reducing the required space by 75%. \nRegister today to watch these live demonstrations and chat with Keysight’s RF experts\, who will be available to answer your questions throughout the event. \nREGISTER HERE
URL:https://semiwiki.com/event/demo-day-signal-generators/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203246.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260205T090000
DTEND;TZID=America/Los_Angeles:20260205T100000
DTSTAMP:20260403T144804
CREATED:20260120T225257Z
LAST-MODIFIED:20260120T225257Z
UID:365903-1770282000-1770285600@semiwiki.com
SUMMARY:Webinar: Building Efficient\, Secure\, and Scalable AI Systems with UALink
DESCRIPTION:Date: Feb 05\, 2026 | 9:00 AM PST \n\n\nFeatured Speakers: \n\nVarun Agrawal\, Product Manager\, Synopsys\nJon Ames\, Product Manager\, Synopsys\n\nDiscover how UALink enables open\, scalable\, secure interconnects for AI workloads—and how Synopsys IP and VIP accelerate adoption. \nWhy You Should Attend: \n\nLearn about UALink advantages over proprietary interconnects for AI scalability and security.\nExplore open ecosystem benefits: multi-vendor interoperability and hyperscale efficiency.\nSee Synopsys solutions in action: IP\, VIP\, and transactors for streamlined design and verification.\nGain strategic insights for future-proofing AI infrastructure with open standards.\n\n\n\n\n\nFeatured Speakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nVarun Agrawal \nProduct Manager\, Synopsys \nVarun Agrawal is a product manager for verification IP\, virtual system adaptors\, and protocol solutions for hardware-assisted platforms at Synopsys. He has over 14 years of experience in functional verification with expertise in simulation\, emulation\, and virtualization domains. He holds a BTech in electronics and communications from NIT Hamirpur\, India\, and an MBA in marketing from India Institute of Foreign Trade (IIFT)\, New Delhi\, India \n\nJon Ames \nProduct Manager\, Synopsys \nJon Ames is a principal product manager for the Synopsys Ethernet IP portfolio. Jon has been working in the communications industry since 1988 and has led engineering and market activities from the early days of 10/100 Switched Ethernet through Metro and Transport variants to the latest Data Center and High-Performance Computing Ethernet technologies. Since graduating in Computer Science and Electronic Engineering the in UK\, Jon has worked at the leading companies in the networking and silicon solution industries. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-building-efficient-secure-and-scalable-ai-systems-with-ualink/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/varun-agrawal-headshot-2qlt82ampts1766427720820ampresponsiveampfitconstrainampdproff.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260204T090000
DTEND;TZID=America/Los_Angeles:20260204T100000
DTSTAMP:20260403T144804
CREATED:20260120T225747Z
LAST-MODIFIED:20260120T230339Z
UID:365917-1770195600-1770199200@semiwiki.com
SUMMARY:Webinar: Synopsys and TSMC Discuss Multi-Die Monitoring\, Embedded Test & Repair Flows
DESCRIPTION:Date: Feb 04\, 2026 | 9:00 AM PST \n\n\nFeatured Speakers: \n\nDr. Yervant Zorian \, Chief Architect and Fellow at Synopsys\, President of Synopsys Armenia\nDr. Sandeep K Goel\, Senior Director\, TSMC\n\nOur upcoming Synopsys webinar features an exciting real-world case study showcasing Synopsys IP and EDA tools with UCIe-based chiplets on advanced TSMC silicon and packaging technologies. See firsthand the silicon proof points for complete die-to-die interconnects\, embedded memory\, and logic monitoring\, test\, and repair. \nDiscover how 2.5D and 3D multi-die designs transform high-performance computing and AI. This webinar explores key challenges of monitoring\, embedded test and repair for multi-die designs\, including essential pre-stack and post-stack manufacturing flows\, in-field health monitoring\, and the role of the 3Dblox language (under IEEE P3537 Standardization) in enabling EDA tool interoperability. Learn about practical Silicon Lifecycle Management solutions that optimize quality\, yield\, reliability and manufacturing cost across advanced packaging configurations. \nWhat You Will Learn: \n\nSilicon proof points for monitoring\, test\, and repair across advanced packaging configurations\nKey embedded test & repair flows for multi-die designs\nIn-silicon health monitoring solutions for silicon lifecycle management\nPractical test cost minimization strategies for multi-die solutions\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nFeatured Speakers\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Yervant Zorian \nChief Architect\, Synopsys \nDr. Yervant Zorian is a chief architect and fellow at Synopsys\, as well as president of Synopsys Armenia. Yervant holds 35 U.S. patents\, has authored four books\, published over 350 refereed papers\, and received numerous best paper awards. He received an M.S. degree in Computer Engineering from the University of Southern California\, a PhD in Electrical Engineering from McGill University\, and an MBA from the Wharton School of Business\, University of Pennsylvania. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nDr. Sandeep K Goel \nSenior Director\, TSMC \nDr. Sandeep K Goel is an academician and senior director at Taiwan Semiconductor Manufacturing Company (TSMC)\, USA. He previously held research and management roles at LSI\, Magma Design Automation\, and Philips Research. Dr. Goel earned his M.Tech. in VLSI from IIT Delhi in 1999 and his Ph.D. in Electrical and Computer Engineering from the University of Twente in 2005. He has co-authored multiple book chapters\, published over 90 conference/journal papers\, and holds more than 100 US patents. He received the Most Significant Paper Award at ITC in 2010 and the Distinguished Contributor Award from the IEEE Computer Society in 2022. He is the chair of IEEE Std. P3537 standard for 3Dblox: Chiplet connectivity and physical properties description language. His research focuses on design verification\, testing\, diagnosis\, and defect modeling of 2D/3D SOCs. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-synopsys-and-tsmc-discuss-multi-die-monitoring-embedded-test-repair-flows/
LOCATION:Virtual
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/Synopsys-multie-die-TSMC-webinar-1200x628px-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260203T090000
DTEND;TZID=America/Los_Angeles:20260203T100000
DTSTAMP:20260403T144804
CREATED:20260114T022128Z
LAST-MODIFIED:20260114T022128Z
UID:365706-1770109200-1770112800@semiwiki.com
SUMMARY:Webinar: From C++ to Silicon: Fast\, Physically Aware\, AI-Driven Exploration with Rise Design Automation and Precision Innovations
DESCRIPTION:As hardware designs grow more complex\, architectural exploration is increasingly critical to delivering differentiated silicon. Teams frequently develop promising architectures only to discover late in the cycle that physical implementation is too costly or fails to meet key specifications. This challenge intensifies as designers integrate new accelerators — video\, audio\, ML\, or custom datapaths — rapidly expanding the search space. \nAI-based automation can help\, but only when each exploration trial provides cost metrics (area\, timing\, power) that are both fast and credible. Traditional parameter sweeps are slow. Full physical analysis is expensive. And without correlation to real implementation costs\, AI-guided exploration can simply produce the wrong answers faster. \nRise Design Automation and Precision Innovations are partnering to change this dynamic. Together\, they deliver fast\, accurate\, physically aware exploration loops — ideal for reinforcement learning\, iterative refinement\, and high-volume experimentation. \nRise Design Automation provides 10× faster High-Level Synthesis (HLS) with timing and area correlation within a few percent of downstream RTL-synthesis results. The Rise toolchain can also execute downstream tools “under the hood” and incorporate their feedback directly into HLS. Integrating Precision Innovations’ industry ready OpenROAD-based RTL→GDSII flow and OpenROAD Flow Scripts adds production-grade physical estimation with strong area and timing accuracy validated down to advanced nodes (including 2–3nm). \nCombined\, this integrated flow enables rapid exploration from high-level C++/SystemC/SystemVerilog through synthesized RTL to physically correlated PPA — supporting hundreds or thousands of trials without licensing barriers. \nThis session demonstrates how an integrated\, AI-driven architectural exploration solution from Rise Design Automation and Precision Innovations provides rapid\, actionable feedback to guide design decisions\, and how you benefit from these capabilities in your own design flow. \n\n\n\n\n\n\n\n\nWhat You’ll Learn\n\n\n\n\nIn this technical deep dive\, you’ll see how Rise Design Automation and Precision Innovations help you: \n\nRun AI-guided architectural exploration with fast\, physically grounded cost metrics\nModel and explore designs in C++\, SystemC\, or SystemVerilog and automatically generate multiple RTL variants\nUse Rise’s fast\, correlated HLS engine to accelerate exploration with credible RTL-level PPA\nLeverage Precision’s OpenROAD-based RTL→GDSII flow for production-grade physical estimation — enabling early visibility into area\, timing\, and implementation feasibility\nApply reinforcement learning and design agents to guide the search toward optimal architectures\nScale exploration across hundreds or thousands of trials without restrictive per-run licensing\n\nThis webinar highlights practical techniques to accelerate exploration\, increase confidence\, and improve architectural decisions earlier in the design process. \n\n\n\n\nLive Demonstration\n\n\n\n\nSee a complete exploration loop from high-level behavioral model through Rise Design Automation’s HLS\, through RTL synthesis\, and into Precision Innovations’ OpenROAD-based physical estimator — with AI-guided refinement driven by real PPA feedback \n\n\n\n\nWho Should Attend:\n\n\n\n\nHardware architects\, design engineers\, verification leads\, and research teams who want to: \n\nAccelerate architectural exploration for complex accelerators\nApply AI/ML or reinforcement-learning workflows to silicon design\nImprove correlation between high-level design\, RTL\, and physical estimates\nConfidently explore many architectural options without slow iteration loops\nShift verification and physical awareness earlier in the flow\nDeploy scalable exploration without restrictive per-run licensing\n\nWhether you’re adding a new accelerator to an SoC or exploring ML-driven design automation\, this session provides a practical foundation for leveraging Rise + Precision. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-from-c-to-silicon-fast-physically-aware-ai-driven-exploration-with-rise-design-automation-and-precision-innovations/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-13-181938.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260128T100000
DTEND;TZID=America/Los_Angeles:20260128T110000
DTSTAMP:20260403T144804
CREATED:20251211T205410Z
LAST-MODIFIED:20251211T205410Z
UID:364596-1769594400-1769598000@semiwiki.com
SUMMARY:Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
DESCRIPTION:In this webinar\, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks. \nWe will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout. \nWe will show you how these tools work on real designs as well. \nWHO SHOULD ATTEND THIS WEBINAR?\nIf you are designing chips to deploy in networked environments\, you need to understand the risks ahead and how to minimize them. \nIf you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions. \nSPEAKERS\nBeau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies \nDr. Paul Calzada will take you through a live demonstration of CODAx\, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions. \n* This webinar is in partnership with SemiWiki and Caspia Technologies \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-why-ai-assisted-security-verification-for-chip-design-is-so-important/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/12/background.jpeg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260128T090000
DTEND;TZID=America/Los_Angeles:20260128T170000
DTSTAMP:20260403T144804
CREATED:20260113T042846Z
LAST-MODIFIED:20260113T042846Z
UID:365659-1769590800-1769619600@semiwiki.com
SUMMARY:Power Seminar - Burnaby
DESCRIPTION:About this event\nAs power levels rise and systems scale\, high-power testing becomes more complex and time-consuming. This hands-on Power Solutions Seminar focuses on practical test strategies for batteries\, fuel cells\, green energy\, and power conversion. \nYou will experience expert-led technical sessions with hands-on\, real-world application insights. Explore Keysight’s three new High-Power ATE System Supplies and demos across our power portfolio to improve test efficiency\, accuracy\, and development speed. \n\n\n\n\n\n\n\nWho should attend this event?\nThis event is designed for development engineers in power electronics\, battery systems\, and green energy. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/power-seminar-burnaby/
LOCATION:Burnaby\, BC\, Burnaby\, British Columbia\, Canada
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260128
DTEND;VALUE=DATE:20260129
DTSTAMP:20260403T144804
CREATED:20260113T043124Z
LAST-MODIFIED:20260113T043124Z
UID:365664-1769558400-1769644799@semiwiki.com
SUMMARY:Webinar: Powering the Future: Megawatt Charging Solutions for Heavy-Duty Electrification
DESCRIPTION:About this event\nJoin our upcoming webinar to discover how Keysight is powering the future of heavy-duty electric transportation with advanced megawatt-charging test solutions. \nLearn how to validate ultra-high-power delivery beyond 3 MW\, ensure compliance with MCS and ISO 15118-20\, and streamline interoperability testing\, all within a single\, fully controllable platform designed for both compliance and development debugging. \nWe’ll explore how seamless integration of software\, hardware\, and project services accelerates the deployment of safe\, scalable\, and standards-driven charging infrastructure for trucks\, ships\, and heavy machinery. \n\n\n\n\n\n\n\nWho should attend this event?\nThose involved in the shift towards a future-proven transportation\, logistics\, and construction ecosystem. Specific titles: OEM Electrification Leaders; EVSE Manufacturers & Charging Infrastructure Developers; Compliance & Standards Specialists; Fleet Electrification Managers: Grid Integration & Energy Management Specialists. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-powering-the-future-megawatt-charging-solutions-for-heavy-duty-electrification/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203022.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260127T090000
DTEND;TZID=America/Los_Angeles:20260127T100000
DTSTAMP:20260403T144804
CREATED:20251217T021629Z
LAST-MODIFIED:20251217T021629Z
UID:364770-1769504400-1769508000@semiwiki.com
SUMMARY:Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)
DESCRIPTION:Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process\, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process. \nWhat you will learn \n\nThe breadth of the entire Gencellicon portfolio\nHow timing closure solutions can alleviate your design process using Siemens tools\n\nWho should attend \n\nImplementation engineers\nSoC architects\nDesign Verification teams\nTest engineers\nPower architects\nPhysical designers\n\n\n\n\nSpeaker: \n\n\n\n\nHimanshu Bhatnagar \nSenior Director\, Siemens EDA \n\n\n\nHimanshu brings over 20 years of expertise in chip design\, having developed complex SoCs across networking\, communications\, imaging\, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis\, a practical guide to synthesis and static timing analysis. Before founding Excellicon\, now Gencellicon\, Himanshu held key positions at leading semiconductor companies\, including Mindspeed Technologies\, Conexant Systems\, and ST Microelectronics. At Conexant Systems\, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally\, Himanshu has served as an advisor to various EDA companies. \n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-solving-timing-closure-challenges-using-gencellicon-previously-excellicon/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Screenshot-2025-12-16-181547.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260127T083000
DTEND;TZID=America/Los_Angeles:20260127T170000
DTSTAMP:20260403T144804
CREATED:20260107T031557Z
LAST-MODIFIED:20260107T031557Z
UID:365310-1769502600-1769533200@semiwiki.com
SUMMARY:Semiconductor Traceability and Provenance Workshop
DESCRIPTION:The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday\, January 27\, 2026\, at the NIST National Cybersecurity Center of Excellence (NCCoE) conference facility\, in Rockville\, Maryland. This in-person\, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain\, which identified traceability as the top priority of semiconductor industry stakeholders. \nAs semiconductor devices grow more complex and globally distributed\, the risks from counterfeit components\, malicious tampering\, and opaque sourcing threaten the security\, reliability\, and resilience of critical systems. Strengthening traceability and provenance is essential to mitigating supply chain threats\, supporting national security imperatives\, and addressing the grand challenges in secure microelectronics (https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000.pdf). \nThe workshop will convene technical leaders across the semiconductor ecosystem (e.g.\, hyperscalers\, auto and semiconductor companies\, federal agencies\, academia) to address the practical challenges and opportunities for implementing traceability in semiconductor chips. This one-day event will feature plenary\, panel\, and interactive breakout sessions. Participants will be encouraged to collaborate and discuss key questions and topics that will identify short-term (<1 year) and longer-term (2028-2029 time frame) activities related to semiconductor traceability and provenance. The topics that will be considered include but are not limited to: \n\nExisting solutions\nTechnical\, operational challenges to traceability adoption\nOpportunities for public-private collaboration (e.g.\, hyperscalers\, automobile\,\nsemiconductor companies\, government agencies\, academia)\nRoadblocks to alignment and paths to overcoming them\nEconomic drivers and pilot use cases for traceability\nFrameworks for joint standards development and implementation\nRoadmap for collaboration and path to success\n\n\nOutcomes from the workshop will include a published roadmap and post-workshop report that advances shared goals in securing semiconductor supply chains. \nRegistration Info\nThe registration fee for this event is $97.00 and includes AM/PM breaks and lunch. \nRegistration closes on Tuesday\, January 20\, 2026. \nRegistration Contact for Additional Information or Questions:\nCarol L. Shibley\ncarol.shibley@nist.gov\n(301) 975-8302 \nTECHNICAL CONTACT:\nKostas Amberiadis\nkostas.amberiadis@nist.gov \nREGISTER HERE
URL:https://semiwiki.com/event/semiconductor-traceability-and-provenance-workshop-2/
LOCATION:NIST’s National Cybersecurity Center of Excellence (NCCoE)\, 9700 Great Seneca Highway\, Rockville\, MD\, 20850\, United States
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