SemiWiki

Webinar: Advanced Packaging and Material Characterization for Microelectronics: SEMI Training
2025-11-03 08:30 - 17:00 (America/Los_Angeles) | Online
Strengthen your knowledge and skills by learning about new packaging technologies in Fan-in, Fan-out WLP, Embedded packaging technology, System on Chip (SOC), System in Package (SiP), 3D IC, WLP, TSV, etc. Packaging knowledge is a must for professionals in the semiconductor industry. The first part of this course dives deep into advanced packaging. Part 2 of this course focuses on the design in electrical and thermal which are used to enhance the electrical, thermal, and reliability performance of the package.

Pricing

Members: $599
Non-Members: $649

* For group orders with 10+ attendees, and for Students/Veterans discounted pricing, please contact semiu-support@semi.org.
REGISTER HERE

Semitracks Course: Wafer Fab Processing
2025-11-03 - 2025-11-06 | Phoenix, AZ, Phoenix, AZ, United States
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is a 4-day course that offers an in-depth look into the semiconductor manufacturing process, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique, and we delve into the current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.
By focusing on the basics of each processing step and the issues surrounding them, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about the semiconductor industry. This skill-building series is divided into three segments:

Basic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. Participants will learn the fundamentals of each processing step and why they are used in the industry today.
The Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants will learn how each technique has evolved for use in previous and current generation ICs.
Current Issues in Wafer Fab Processing. Participants will learn how many processing steps are increasingly constrained by physics and materials science. They will also learn about the impact of using new materials in the fabrication process, and how those materials may create problems for the manufacturers in the future.

This course is a must for every manager, engineer, and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

Course Objectives

This course will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.
Participants will understand the basic concepts behind the fundamental wafer fab processing steps.
This course will identify the key issues related to each of the processing techniques, and their impact on the continued scaling of the semiconductor industry.
This course will offer a wide variety of sample problems that participants will work to help them gain knowledge of the fundamentals of wafer fab processing.
Participants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition, ion implantation, lithography, and etching.
Participants will understand how processing, reliability, power consumption and device performance are interrelated.
Participants will be able to make decisions about how to construct and evaluate processing steps for CMOS, BiCMOS, and bipolar technologies.

REGISTER HERE

Webinar: 5 Expectations for the Memory Market in 2026
2025-10-29 11:00 - 12:00 | Online
October 29, 2025 – 11:00 AM EST
October 30, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026
AI workloads, HBM4 adoption, and 3D NAND scaling—what’s next for the memory industry in 2026.
The memory semiconductor industry is entering a critical inflection point. Explosive AI workloads are pushing traditional architectures beyond their limits, creating both breakthrough opportunities and severe supply constraints across the DRAM and NAND markets.
By 2026, the next wave of memory innovation will determine which companies lead in performance and profitability—and which fall behind. From HBM4 and FinFET base dies to 3D NAND scaling with hybrid bonding, technology and market shifts are reshaping the competitive landscape.
In this live TechInsights webinar, our experts will explore five expectations shaping the memory markets in 2026, highlighting the implications for leading players and global strategies.
Key Topics You’ll Learn

Samsung’s D1c HBM4 adoption – 16Hi stacks with 1.5 TB/s bandwidth.
Foundry FinFET base dies – TSMC and the evolution of HBM integration.
KIOXIA’s HBF potential – A high-bandwidth Flash alternative for edge AI.
3D NAND scaling – 300+ layers, hybrid bonding, molybdenum wordlines, and stairless contacts.
Market & geopolitical dynamics – Revenue acceleration and U.S. export controls impacting YMTC, CXMT, and JHICC.

REGISTER HERE

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration
2025-10-29 11:00 - 12:00 | Online
Description
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to learn about network time synchronization, publisher-subscriber communication, and time-aware shaping for TSN traffic using Wireshark. By the end, you’ll be equipped to effectively utilize the AMD Kria SOM’s configurability for innovative designs. This interactive session is ideal for developers aiming to deepen their TSN knowledge and streamline their workflows.
This webinar includes a live demonstration and Q&A.
If you are unable to attend, a recording will be sent one week after the live event.
To see our complete list of webinars, visit our website: www.bltinc.com.
REGISTER HERE

Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System
2025-10-29 09:00 - 10:00 | Online
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines machine learning, reinforcement learning, generative, and agentic AI across the entire EDA workflow. This session showcases how Siemens is realizing this vision in the RTL-to-GDS space with the newly launched Aprisa AI: a fully integrated, AI-powered solution working in concert with the Siemens EDA AI System.
Aprisa AI delivers a 10x boost in engineering productivity, a 3x compute-time efficiency improvement, and 10% better PPA results compared to conventional workflows. Aprisa AI intelligently optimizes digital implementation flows to provide the best PPA for any given design. It also includes a generative and agentic AI assistant capable of answering questions about documentation and designs, launching commands, and running tools within Aprisa. This assistant is powered by the Siemens EDA AI System—an open, customizable, and secure platform that extends agentic AI capabilities across the entire EDA workflow. The system is designed to increase overall chip designer productivity through agentic automation, smart design queries, accelerated learning, and unlocking valuable insights from a centralized multimodal EDA data lake.
What you will learn:

Powerful AI/ ML digital implementation features like Aprisa’s design explorer for rapid and intelligent exploration of the design space
The role of machine learning, reinforcement learning, generative AI, and AI agents, in automating and scaling RTL-to-GDS methodologies
How the Siemens EDA AI system helps accelerate learning, performing EDA workflows, and more

Topics include:

An Introduction to Aprisa AI and the Siemens EDA AI System.
Overview of different features and workflows of Aprisa AI
Insightful demonstrations of Aprisa AI and Siemens EDA AI system
Summary & Q&A

Products Featured:

Aprisa AI
Siemens EDA AI System

Speakers:

Janet Attar
Principal Product Manager, Aprisa, Siemens EDA

Janet Attar is Principal Product Manager at Siemens EDA for the Aprisa RTL-to-GDS digital implementation solution, including responsibility for Aprisa AI planning and development. Prior to Siemens, she was a Staff Applications Engineer at Cadence, where she worked with customers to develop silicon chips for consumer electronics, and a Senior Physical Design Engineer for International Rectifier (now Infineon) where she worked on digital controllers. Janet holds a B.Eng in Electrical Engineering from Carleton University.

Niranjan Sitapure, PhD
Central AI Product Manager, Siemens EDA, Siemens EDA

Niranjan Sitapure, PhD, is the Central AI Product Manager at Siemens EDA. He oversees road mapping, development, strategic AI initiatives, and product marketing for the Siemens EDA AI portfolio. With a PhD in Engineering from Texas A&M University, Niranjan has honed his expertise in advanced AI/ML technologies, including time-series transformers, LLMs, and digital twins for engineering applications. Previously, Niranjan was a consultant at Bain & Company, where he advised Fortune 500 clients on digitization strategies, operating model redesigns, and due diligence.

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CadenceCONNECT: Jasper User Group 2025
2025-10-29 - 2025-10-30 | San Jose Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The Jasper User Group Conference is the premier industry event for formal experts and beginners alike to learn from each other how to effectively accelerate their design and validation processes by applying formal methods.

Conference Highlights

User presentations on core technologies, applications, and flows
– Roadmap discussions
– New technology demos
– Executive keynotes

REGISTER HERE

Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis
2025-10-28 09:00 - 10:00 | Online
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL, and performing verification. An agile workflow requires being able to iterate through the architecture and implementation phases quickly to converge towards an efficient design. This is especially true for designing low footprint hardware accelerators on FPGAs, where architectural choices directly impact resource fit feasibility and performance.
Join us as we discuss architectural and microarchitectural design space exploration focusing on the SoftMax function—a key component in many neural networks. We showcase how SoftMax can be targeted on FPGA, balancing performance within tight area and resource budgets for edge deployments. We will use Catapult High-Level Synthesis as we discover its capabilities for data path-oriented hardware designs encountered in vision systems and edge inference engines.

Speakers:

Shreedutt Hedge
Senior ML RTL Engineer, Lattice Semiconductor

Technical lead on the FPGA acceleration of SensAI ML solution stack. Designing accelerated ML pipelines for low power edge devices, with focus on low resource footprint. Lead accelerator architecture study, own and develop RTL microarchitecture for implementing ML operators as soft logic in FPGA.
Work with the compiler team to support YOLO series CNN model on the accelerator.

Cameron Villone
High-Level Synthesis Technologist, Siemens EDA

Cameron Villone is a High-Level Synthesis Technologist working with the Catapult High-Level Synthesis product management and marketing team, focusing on AI hardware deployment. He previously worked as a product marketing engineer for PowerPro, Siemens’ power optimization and analysis product. He held previous roles at Texas Instruments and General Motors. Cameron studied and graduated from Rochester Institute of Technology, obtaining both a bachelor’s and master’s degree in electrical engineering, focusing on Robotics, Embedded Systems, and Computer Vision.

Sivasankar Palaniappan
High-Level Synthesis Technologist, Siemens EDA

Sivasankar currently works as a High-Level Synthesis Technologist in the Marketing division of the Catapult team. He joined Siemens in July 2020 as an Associate Rotation Engineer and migrated to the new role a year later. Sivasankar has a MS in Electrical and Computer Engineering, focusing on Computer Engineering from University of California San Diego.

REGISTER HERE

ICCAD 2025
2025-10-26 - 2025-10-30 | Munich, Germany, Munich, Germany
The 2025 International Conference on Computer-Aided Design

Call For Papers

Jointly sponsored by IEEE and ACM, IEEE ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. IEEE ICCAD covers the full range of CAD topics – from device and circuit level up through system level, as well as post-CMOS design. IEEE ICCAD has a long-standing tradition of producing cutting-edge, innovative technical program for attendees.

REGISTER HERE

2025 TSMC Open Innovation Platform Ecosystem Forum - Tokyo
2025-10-24 | Grand Hyatt Tokyo, 6 Chome-10-3 Roppongi, Minato City, Tokyo, 106-0032, Japan
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM
Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event; it’s a dynamic hub where the brightest minds converge to ignite the next wave of innovation.
As the AI revolution proliferates from the data center to the edge and becomes integrated into every application, the need for high-performance and energy-efficient designs is becoming paramount. Through a series of compelling, multi-track presentations, you’ll gain a firsthand understanding of how the ecosystem is collaboratively tackling these critical design requirements.
AI is also transforming how chip and multi-die designs are done. This year, the forum will highlight how the ecosystem is harnessing the immense potential of AI in next generation of design solutions for TSMC’s advanced process and packaging technologies. Prepare to be immersed in a wealth of knowledge as industry trailblazers and TSMC’s ecosystem partners offer valuable insights into the latest breakthroughs.
The event provides a unique opportunity for you to engage with thought leaders and innovators, whether you join in-person at locations across North America, Japan, Taiwan, China, and Europe, or participate online.
Don’t miss this opportunity to connect with the leading players of semiconductor technology and be part of shaping tomorrow’s innovations, today!
Opportunity to gain insights into

Solutions needed to address energy efficiency and other challenges impacting the next-generation AI chips and corresponding design flows and methodologies for TSMC A16™, N2, and N3 processes
Consistent progress in design enablement and solution development for TSMC’s advanced processes including A14, TSMC A16™ and N2
Latest advancements in design solutions on TSMC 3DFabric® chip stacking (including InFO, CoWoS®, TSMC-SoIC®, TSMC-SoW™), as well as updates on the TSMC 3DFabric Alliance
AI-assisted design flows for 2D and 3DIC design productivity and optimization
Design enablement technologies, IPs, and solutions targeting the latest HPC, AI/ML, automotive, mobile/5G and IoT applications
Comprehensive design solutions for specialty technologies including ultra-low power, ultra-low voltage, analog migration, RF, and mmWave
Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market

REGISTER HERE

Webinar: IP Design Considerations for Real-Time Edge AI Systems
2025-10-23 10:00 - 11:00 | Online
*Work Email Required*
Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support real-time AI workloads at the edge. We’ll cover:
• Memory and compute efficiency: Techniques for optimizing on-chip memory architectures and compute pipelines to deliver high throughput and low energy consumption.
• Low-latency inference: Design considerations to meet stringent latency targets through local processing and effective dataflow management.
• Power and area optimization: Strategies for balancing compute capability with ultra-low power operation and minimal silicon area.
• Multi-die considerations: Ways to approach multi-die design for advanced Edge AI applications.
• IP risk mitigation and integration: Best practices for modular, verifiable IP reuse that accelerates first-silicon success and manages integration risk.
• Evolving Edge AI requirements: Insights into how emerging architectures are shaping IP trends enabling smarter, adaptive edge devices.

Attendees will gain a detailed understanding of how IP selection, memory/compute co-design, and hardware optimization directly impact the scalability, reliability, and deployment speed of next-generation Edge AI solutions.
Speaker: Hezi Saar is a senior director of product line management for mobile, automotive, and consumer IP for the Synopsys Solutions Group. He brings more than 20 years of experience in the semiconductor and embedded systems industries.
*This webinar is in partnership with Synopsys and SemiWiki*
REGISTER HERE

EU Chips Act 2.0 Webinar
2025-10-23 | Online
Europe’s Role & Chips Act 2.0 Priorities

The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative to strengthen the European semiconductor ecosystem.
Building on the original Chips Act adopted in 2023, this updated framework aims to address emerging technologies such as Artificial Intelligence, supply chain needs, and geopolitical challenges while fostering innovation, research, and production capacity within Europe, as well as support to start-ups in order to foster scaling-up.
As GSA encompasses the entire semiconductor value chain, its members are optimally positioned to understand the ecosystem needs to evolve and grow.
In this webinar, we will present the main objectives, challenges and opportunities of this EU effort, very timely in these challenging times.

REGISTER HERE

Webinar: 5 Expectations for the Power Market in 2026
2025-10-22 11:00 - 12:00 | Online
October 22, 2025 – 11:00 AM EST
October 23, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Power Market Trends Reshaping Semiconductors in 2026
Wide-bandgap disruption, PMIC innovation, and datacenter power demand, what’s next for power semiconductors.
The rise of AI datacenters is driving unprecedented demand for power, creating both massive opportunities and major challenges for the power semiconductor industry. As computing power doubles nearly every six months, new technologies and global competition are reshaping the market faster than ever.
By 2026, datacenter power conversion markets are projected to reach nearly $4 billion, while silicon carbide (SiC) oversupply and intensifying Chinese competition will redefine strategies for global players. At the same time, the GaN industry faces transformation with TSMC’s exit, opening the door for new foundry opportunities, while China accelerates its self-sufficiency goals for wide-bandgap technologies by 2027.
In this live TechInsights webinar, our experts will break down five key developments that will define who leads, and who falls behind in the next two years.
Key Topics You’ll Learn

Datacenter power conversion – $4B market growth by 2026 as AI accelerates.
SiC oversupply & Chinese competition – How strategies must adapt.
The GaN transition – TSMC exits, new foundry opportunities emerge.
China’s wide-bandgap drive – Strategic self-sufficiency by 2027.
PMIC evolution – Higher integration, intelligence, and co-design.

REGISTER HERE

Achieving Timing Closure in FPGA Designs Workshop
2025-10-22 10:00 - 15:00 | Online
Achieving Timing Closure in FPGA Designs Workshop
Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure.
Gain hands-on experience with timing closure techniques and learn strategies to improve design performance and meet timing requirements efficiently.
Gain experience with:

Understanding basic Static Timing Analysis (STA)
Reading timing report
Applying techniques to reduce delay and to improve clock skew and clock uncertainty
Resolving timing violations
Using the Timing Constraints Wizard

This course focuses on the UltraScale, UltraScale+ and Versal architectures.
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
REGISTER HERE

Webinar: Pushing more power with CoolGaN™: design, layout and thermal management
2025-10-22 09:00 - 10:00 | Online
Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST

Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems.
You will gain a deep understanding of gate drive circuit design, layout steps, and thermal management guidelines for GaN transistors and applications in high-switching frequency topologies.
Attending the webinar will help you gain a deeper understanding of the design principles and best practices for working with GaN power devices. You will learn how to design and optimize gate drive circuits for GaN power applications, including the selection of suitable components. In addition to gate drive circuit design, the webinar will also cover the essential layout steps for maximizing GaN design performance. You will learn how to create a layout that minimizes parasitic inductance and capacitance, and how to optimize the placement of components to ensure optimal thermal performance.
The webinar will provide essential thermal management guidelines for GaN transistors and their applications in high-switching frequency topologies to achieve the highest efficiency.

You will learn about:

How to design and optimize gate drive circuits for Gallium Nitride (GaN) power applications
Layout steps for maximizing GaN design performance
Essentials of thermal management guidelines.

REGISTER HERE

CadenceCONNECT: Photonics and Quantum Technologies
2025-10-22 - 2025-10-23 | San Jose, CA
Event Summary

The year 2025 is both a turning point for integrated photonics as a key enabler for AI, physical and infrastructure interconnect, and the International Year of Quantum (IYQ). In our event, we are going to explore the enabling technologies shared by these two exciting fields. While these systems need to exist in a broader ecosystem, we will focus on the technologies required to enable the creation and analysis of the devices, the ICs, and the full system.
Join Cadence for one or both days of the 9th annual CadenceCONNECT photonics event and workshop on October 22-23 in San Jose, California. On day one, we’re featuring presentations from industry and academic experts, and on day two, you will have the opportunity to learn hands-on with photonics experts.
Who should attend?
– Photonics and quantum IC designers and architects
– Photonics and quantum design project leads
– Photonics and quantum design managers
– CAD and PDK managers
Don’t miss this opportunity to learn about solutions for your design challenges and network with other expert users during lunch and social hours.
Seating is limited. If you register and are unable to attend, please let us know.
Agenda at-a-Glance
*Subject to change
Day 1: October 22, in-person and virtual
8:30-9:00am – Registration, light breakfast
9:00-5:00pm – Sessions/Lunch/Breaks
5:00 – 7:00pm – Reception
Day 2: October 22, in-person only
8:30-9:00am – Registration, light breakfast
9:00-5:00pm – Workshop/Lunch/Breaks
Bring your laptops
REGISTER HERE

RISC-V Summit North America 2025
2025-10-22 - 2025-10-23 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive, data center, space, IoT, embedded and more. Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly, enjoy a new level of design freedom, and substantially reduce the cost of innovation. Anyone, anywhere can benefit from these contributions.

This October, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies, as well as to network and build relationships. Come be part of the RISC-V movement.

The festivities kick off with RISC-V Member Day, where technical and industry working groups meet in person to share updates on the status of various efforts.
Next, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions, paired with an expo featuring dozens of community members showcasing their the latest solutions.

It’s community-curated content, research and innovation driving the next wave of growth for RISC-V.
Learn about software, systems, development tools, security, the latest use cases in key markets and more. It’s all here.
Define the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us!
REGISTER HERE

Semiconductor Traceability and Provenance Workshop
2025-10-21 08:30 - 17:00 | NIST Gaithersburg, NIST Gaithersburg, 100 Bureau Drive, Gaithersburg, MD, 20899, United States
The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday, October 21, 2025, at its campus in Gaithersburg, Maryland. This in-person, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain, which identified traceability as the top priority of semiconductor industry stakeholders.
As semiconductor devices grow more complex and globally distributed, the risks from counterfeit components, malicious tampering, and opaque sourcing threaten the security, reliability, and resilience of critical systems. Strengthening traceability and provenance is essential to mitigating supply chain threats, supporting national security imperatives, and addressing the grand challenges in secure microelectronics (https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000.pdf).
The workshop will convene technical leaders across the semiconductor ecosystem (e.g., hyperscalers, auto and semiconductor companies, federal agencies, academia) to address the practical challenges and opportunities for implementing traceability in semiconductor chips. This one-day event will feature plenary, panel, and interactive breakout sessions. Participants will be encouraged to collaborate and discuss key questions and topics that will identify short-term (<1 year) and longer-term (2028-2029 time frame) activities related to semiconductor traceability and provenance. The topics that will be considered include but are not limited to:

Existing solutions
Technical, operational challenges to traceability adoption
Opportunities for public-private collaboration (e.g., hyperscalers, automobile,
semiconductor companies, government agencies, academia)
Roadblocks to alignment and paths to overcoming them
Economic drivers and pilot use cases for traceability
Frameworks for joint standards development and implementation
Roadmap for collaboration and path to success

Outcomes from the workshop will include a published roadmap and post-workshop report that advances shared goals in securing semiconductor supply chains.
REGISTER HERE

SPIE Optifab 2025
2025-10-20 - 2025-10-23 | Joseph A. Floreano Rochester Riverside Convention Center, Joseph A. Floreano Rochester Riverside Convention Center, 123 East Main Street, Rochester, NY, 14604, United States
Join colleagues at the largest optical manufacturing conference and exhibition in North America

SPIE Optifab is the premier event to meet with top companies and learn about the latest optical fabrication technologies. Organized jointly by SPIE and APOMA, Optifab is the largest optical manufacturing conference and exhibition held in North America.
In 2025 the meeting will be co-located with SPIE Laser Damage in Rochester, New York.
Enjoy four days of connecting with your community

Meet suppliers at the exhibition
Hear technical presentations
Enjoy invited speakers
Get training while onsite
Enjoy networking events

We look forward to gathering these two important communities in one location.
Exhibition: 21 – 23 October 2025
Technical program: 20 – 23 October 2025

REGISTER HERE

MICRO 2025 - 58th IEEE/ACM International Symposium on Microarchitecture
2025-10-18 - 2025-10-22 | Seoul, Korea, Seoul, Korea, Republic of
The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and we aim to continue this tradition at MICRO-58. In 2025, MICRO goes to Seoul, Korea.
REGISTER HERE

2025 Embedded World China
2025-10-16 - 2025-10-17 | Shanghai World Expo Exhibition and Convention Center China, 1099 Guozhan Rd, Shanghai, Pudong, 200126
Conference Profile
The embedded world China Conference will take place on October 16 and 17, 2025 at the Shanghai World Expo Exhibition and Convention Centre.
The main topics of this year’s conference are：
· Embedded Technology & Applications
· Vehicle Electronic / Electrical Architecture & Technologies
· Embedded Vision Technologies Innovation and Development Conference using Edge AI
Check the Conference brochure here.
Interested speakers for all three tracks are invited to submit their proposals to contribute to the 3rd edition of the conference with a technical presentation or paper. The embedded world China Conference 2025 calls for future-oriented technologies and solutions, best practices, new ideas and smart concepts for efficient development and lifecycle processes. The presentations will be used to initiate discussions and help other engineers and managers to benefit from shared experiences.
Experts with insight into the embedded systems industry is given an equal opportunity to participate, whether through in-depth academic discussions, technological show cases or best practice studies from research and development.
Acceptance Criteria
Papers will be selected based on the following criteria:
· novelty
· technological soundness
· technological significance
· experience of the speaker
The selection will be made by a programme committee. The members of the programme committee are independent senior engineers and researchers with excellent scientific and business experience.
REGISTER HERE

Webinar: ML-Enhanced TCAD Calibration With 10x Reduction in Time to Results
2025-10-15 17:00 - 18:00 | Online
Date: Oct 15, 2025 | 5:00 PM PST

Featured Speakers:

Saurabh Suryavanshi, Product Manager, Synopsys
Youngkwon Cho, Senior Staff Engineer, Synopsys
Dipanjan Basu, Principal Engineer, Synopsys

Calibration is an essential part of enabling TCAD products usages inside Semiconductor fab. Synopsys has been leading the development of ML-enhanced calibration that reduce the time to results by 10x while improve the quality of results. In this Synopsys Webinar, our team will provide overview of TCAD calibration and recent advances in ML-based calibration.
Why You Should Attend:

Cut TCAD calibration time and accelerate project delivery by 10x.
Overcome accuracy challenges in semiconductor manufacturing.
Streamline calibration workflows for better efficiency.

REGISTER HERE

Featured Speakers

Saurabh Suryavanshi
Product Manager, Synopsys
Saurabh is a Product Manager in the Manufacturing Solutions group at Synopsys, specializing in Digital Twin, machine learning, and GenAI technologies to accelerate semiconductor innovation. He holds a PhD in Electrical Engineering from Stanford University. Saurabh is a recognized expert with over 30 publications, multiple patents, and a strong track record of helping engineers improve productivity and reduce R&D costs.

Youngkwon Cho
Senior Staff Engineer, Synopsys
Youngkwon Cho is a Senior Staff Engineer at Synopsys, leading development of machine learning-based calibration solutions for TCAD simulation. He holds a PhD in applied physics from Ajou University and has deep expertise in optical simulation, process optimization, and AI/ML tools.

Dipanjan Basu
Principal Engineer, Synopsys
Dipanjan is a technology evangelist dedicated to enhancing semiconductor manufacturing productivity through modeling and simulation. He has extensive experience in device physics, compact modeling, and quantum transport simulation, and leads initiatives to accelerate technology development using TCAD and DTCO strategies.

REGISTER HERE

Webinar: 5 Expectations for the AI Market in 2026
2025-10-15 11:00 - 12:00 | Online
October 15, 2025 – 11:00 AM EST
October 16, 2025 – 10:00 AM JST/KST
Discover the 5 Critical AI Market Trends Reshaping Semiconductors in 2026
From datacenter accelerators to 2nm process technology, learn what’s next for AI and the semiconductor industry.
The acceleration of artificial intelligence (AI) adoption is fueling one of the most transformative periods in the history of semiconductors. As AI workloads expand across datacenters, edge devices, and consumer applications, they are driving new requirements in process technology, advanced packaging, and global market dynamics.
By 2026, datacenter accelerator markets alone are projected to exceed $300 billion, creating massive opportunities across the semiconductor value chain. But the implications go far beyond datacenters, shaping how AI models evolve, how power demands drive innovation, and how geopolitics will impact global supply chains.
In this webinar, TechInsights experts will share their perspectives on five critical expectations for AI markets in 2026 and what they mean for your strategy, designs, and investments.
Key Topics You’ll Learn

AI model evolution – Where are workloads heading in 2026?
Edge AI vs. datacenter AI – The hidden opportunities beyond the headlines.
Power demand & technology innovation – How 2nm and co-packaged optics will reshape performance.
Geopolitical dynamics – US-China competition and its impact on the AI chip ecosystem.
Market outlook – What industry leaders need to anticipate now to stay ahead.

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Andes RISC-V CON Munich
2025-10-14 13:00 - 17:00 | Smartvillage Bogenhausen, Smartvillage Bogenhausen, Rosenkavalierpl. 13, Munich, 81925, Germany
Andes RISC-V CON Munich
Smartvillage Bogenhausen
REGISTER HERE

IEEE International Conference on PHYSICAL ASSURANCE and INSPECTION of ELECTRONICS (PAINE)
2025-10-14 - 2025-10-16 | Denver, CO, Denver, CO, United States
ABOUT PAINE
Physical inspection of electronics has grown significantly over the past decade and is becoming a major focus for the chip designers, original equipment manufacturers, and system developers. The complex long life of the electronic devices coupled with their diverse applications is making them increasingly vulnerable to various forms of threats and inspection. Large industry and government efforts have been put in place across the globe to address related supply chain security problems to offer solutions, training, and services. The number of programs introduced by the US government has increased over the years to analyze and develop relevant solutions. Although much focus is given to the digital domain, physical assurance and inspection of electronics as well as physical fingerprinting based on analog parameters are rapidly providing opportunities for unique countermeasures.
PAINE conference provides a unique venue for all researchers and practitioners from academia, industry, and government to have productive dialog on such topics. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. PAINE covers the broad topic of hardware security and trust; example topics of interest include but are not limited to:
Topics to be Covered:

New metrologies for characterization and assurance
Advanced packaging and heterogenous integration
Emerging topics in physical inspection and assurance
Image analysis and artificial intelligence for assurance and inspection
Metrologies characterization
Automated inspection and metrology for advanced packaging
Security primitives: Novel devices, materials, and systems
Test vehicles and performance quantification
Additive manufacturing assurance for electronics
Physical and design interface assurance
Trojans and backdoors: Detection and prevention

Workforce Development
Fault injection assessment and countermeasures
Side channel assessment (power, timing, EM) for assurance and countermeasures
Analog & mixed-signal circuits and systems security
FPGA Bitstream protection and vulnerabilities
Counterfeit Detection and Anti-Counterfeit Technique
Novel material and devices for assurance
Sample Preparation
PCB trust and assurance
Chip and PCB level decomposition for assurance
FIB/SEM for assurance

Electro-optical probing using PEM, EOP, EOFM, etc.
Physical/side channel fingerprinting
Mod-chip on PCB
Microprobing and nanoprobing
Bus-snooping
Field-based weakness
Countermeasures against tampering and decomposition
Functionality validation
Process improvements
Failure analysis and fault isolation
Physical/logical shielding etc.
Photonics Assurance

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2025 OCP Global Summit
2025-10-13 - 2025-10-16 | San Jose Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights, foster partnerships and showcase cutting-edge advancements in open hardware and software.
*Join us in San Jose October 13-16 for the 2025 OCP Global Summit.
REGISTER HERE

Connected Equipment Summit
2025-10-09 09:00 - 17:30 | Hilton Phoenix Chandler, Hilton Phoenix Chandler, 2929 W Frye Road, Chandler, AZ, 85224, United States
Join us for our inaugural Connected Equipment Summit!
Register here: Connected Equipment Summit
October 9, 2025 | 9AM PT
This summit will take place at the Hilton Phoenix Chandler and will bring together industry leaders from across the semiconductor ecosystem—including fabs, equipment OEMs, and fabless companies. This premier event will showcase PDF Solutions’ latest innovations in equipment connectivity, secure remote access and monitoring, and the transformative applications of AI and digital twin technology in semiconductor equipment management.
What you’ll experience:

Strategic Insights & Product Innovation
Real-World Applications & Success Stories
Technology Leadership & Future Vision.

Sign up to join us today!
REGISTER HERE

CadenceCONNECT: CFD Innovations for the Marine Industry
2025-10-07 08:30 - 18:30 | Cadence Design Systems Belgium, Cadence Design Systems Belgium, Chau. de la Hulpe 189, Bruxelles, 1170, Belgium
What does the future hold for marine CFD simulation? Join us at the CadenceCONNECT: CFD Innovations for Marine Applications seminar to find out!
Historic software uses methods for solving that simply do not have the scalability to meet the needs of marine evolution. Cadence CFD analysis gives you an automatic and efficient computation setup. Additionally, our adaptive grid refinement allows for the constant improvement of simulation accuracy in an already highly capable solver environment.

Here are some of the topics we will cover:

What’s New and What’s Next: Cadence and Fine Marine: Latest developments and roadmap highlights.
Meshing Innovations in Fidelity CFD Software for Marine Applications: Explore V2S updates, S2V without far field, and other meshing enhancements.
C-Wizard and Automation in Fidelity: Streamlining workflows and boosting productivity.
Universal Setup for Ship Simulations in All Wave Conditions: Standardizing simulation setups for consistency and efficiency.
Coupling with MoorDyn: Simulating Cable Dynamics in Interaction with Ships: Integrating open-source tools for advanced marine simulations.
Optimization for Marine Applications with Optimality Intelligent Explorer: Leveraging optimization to improve design and performance.
Accelerating Mono-Fluid Simulations: Techniques and tools to reduce turnaround time.
PLUS User Sessions that discuss real-life case studies and success stories.
Plenty of opportunities to network during the happy hour.

Chau. de la Hulpe 189, 1170 Bruxelles, Belgium

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AutoSens Europe 2025
2025-10-07 - 2025-10-09 | Palau de Congressos, Palau de Congressos, Av. de la Reina Maria Cristina, s/n, Sants-Montjuïc, Barcelona, 08004, Spain
We’re back in the vibrant city of Barcelona, bringing together experts from across the industry

From 7th-9th October 2025, we’re reuniting the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV.
With over 60 expert speakers, engaging panels, technical case studies, and exploration of 12 key themes, we delved into an exhibition with cutting-edge demos from sensor and computer vision leaders.

Why Attend?

Access to an expert community of over 500 experts and engineers
Extensive exhibition with over 50 stands showcasing the latest technology
Vehicle demos from leading Tier 1 and systems companies
High quality technical presentations from genuine experts
Thought-leader panel discussions that shape the industry’s future direction

REGISTER HERE

SEMICON West 2025
2025-10-07 - 2025-10-09 | Phoenix Convention Center, 100 N 3rd St, Phoenix, AZ, 85004, United States
SEMICON West 2025 makes its debut in Phoenix, October 7–9—positioning the city as a key hub for innovation and industry growth. This milestone event gathers global leaders across the microelectronics supply chain to explore transformative technologies, develop the future workforce, and drive strategic collaboration. Now more than ever, we are STRONGER TOGETHER.

Programs + Events
-CEO Summit/Keynotes
-Cybersecurity
-Design
-EHS & Sustainability
-Heterogeneous Integration
-Market Trends
-SEMI U Training Workshops
-SEMICON West’ern
-Smart Data/AI
-Smart Manufacturing
-Smart MedTech
-Smart Mobility
-Supply Chain
-TechTALKS
-Test Vision Symposium
-Workforce Development
-Networking Events
And More!

REGISTER HERE

it-sa Expo & Congress
2025-10-07 - 2025-10-09 | Nuremberg, Germany, Nuremburg, Germany
it-sa Expo&Congress in Nuremberg is Europe’s largest trade fair for IT security…
…and one of the most important dialogue platforms for IT security solutions.
The trade fair covers the entire range of products and services in the field of cybersecurity: hardware, software, training and consulting services as well as Security as a Service. Important topics at it-sa are cloud and mobile security, data and network security, the protection of critical infrastructures, and industrial Security.
Since 2009, it-sa Expo&Congress in Nuremberg has been the meeting place for decision-makers, experts and IT security officers from all sectors of the economy. Whether they represent industry, the service sector or public administration, the exhibitors at it-sa offer customised and individual solutions. On the exhibitor side, it-sa addresses the entire IT security market, including physical IT security. The event thus offers trade visitors a showcase of the IT security industry from Germany and abroad that is unique in Europe. Outstanding innovations by young companies in the field of cyber security will be honoured with the ATHENE Startup Award UP@it-sa.
The freely accessible lecture programme and product-neutral contributions and discussion panels from the it-sa insights series provide trade fair visitors to it-sa with the latest expertise in the industry. In addition, the congress programme Congress@it-sa, organised in cooperation with renowned associations and organisations, offers an intensive dialogue on current topics in IT security.

Welcome to the world of IT security.
REGISTER HERE
