Silicon Catalyst 2025 Semi Industry Forum
2025-11-05 17:00 - 19:30 (America/Los_Angeles) | Computer History Museum, Computer History Museum, 1401 N Shoreline Blvd, Mountain View, CA, 94043, United States
On-the-Road to a $1 Trillion Industry

Reaching $1 trillion in annual semiconductor sales by 2030 presents both significant challenges and offers compelling opportunities.

About this event

Reaching $1 trillion in annual semiconductor sales by 2030 presents both significant challenges and offers compelling opportunities. Demand is accelerating, driven by AI, automotive, data centers, and IoT – but scaling to meet this demand requires massive investments in manufacturing capacity, talent, and R&D.
The global supply chain must become more resilient and geographically diversified, especially amid export control and tariffs. Advanced nodes, chiplets, and new materials promise performance gains but add design and integration complexity. Sustainability is another growing concern, with energy consumption and water usage drawing regulatory and public scrutiny.
Yet, the pathway to $1 trillion is feasible. Public-private partnerships, continued innovation, and strong end-market growth can unlock the next era of expansion. Strategic collaboration across the ecosystem—from startups to foundries—will be essential. Companies that adapt quickly and invest wisely will help shape a more connected, intelligent, and prosperous future for the semiconductor industry.

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Electronic Packaging Days 2025
2025-11-06 - 2025-11-07 | Fraunhofer Institute for Reliability and Microintegration IZM, Gustav-Meyer-Allee 25, Building 17/3, Berlin, 13355, Germany
On 6 and 7 November, Fraunhofer IZM is inviting customers and partners from industry to Berlin for its “Electronic Packaging Days”. The event is designed to facilitate direct exchange between IZM researchers and companies. The aim is to present current research work and technological developments in the field of microelectronic packaging and heterogeneous system integration and to discuss these with partners.
During the coffee and lunch breaks, participants will be spoilt for choice – a total of 12 IZM laboratories and the clean room will open their doors for half-hour tours. At the same time, expert sessions will offer the opportunity to talk to IZM experts about the institute’s technological services and learn more about the APECS pilot line.
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Archetype: Conversations with Silicon Edition
2025-11-06 17:30 - 21:30 | Ferry Building, Ferry Building, 1 Ferry Building, San Francisco, CA, 94105, United States
Archetype, a global tech communications consultancy, is co-hosting, with GV (fka Google Ventures) an exec, media and comms networking event in San Francisco on Thursday, November 6, from 5:30 to 9:30 p.m. at GV’s office in the Ferry Building. We’re bringing together well-respected observers and founders in the semiconductor and computing industries for an evening of discussion about the past, present and future of computing, with ample time for networking before and after.
The first panel will focus on what has happened in chips over the past two decades to explore how we ended up where we are today. Participants include:

Ashlee Vance, Founder and CEO, Core Memory, formerly of the NYT, Economist and Bloomberg
Don Clark, The New York Times, formerly of the Wall Street Journal
John Markoff, former The New York Times journalist
Moderator: Leslie Berlin, historian and Executive Director, Steve Jobs Archive

The second panel will focus on what computing paradigms are poised to win in the decades to come, and will feature:

Nicholas Harris, Founder and CEO, Lightmatter
Tim Davis, Co-Founder and President, Modular
Dave Munichiello, Managing Partner, GV
Dr. Pete Shadbolt, Co-Founder and Chief Scientific Officer, PsiQuantum
Moderator: Lauren Goode, WIRED

Contact Archetype

Phil Kaufman Award Ceremony and Banquet
2025-11-06 18:30 - 21:00 | Hayes Mansion, Hayes Mansion, 200 Edenvale Ave, San Jose, CA, 95136, United States
The Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations, education/mentoring, or business or industry leadership. The award was established as a tribute to Phil Kaufman, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers.
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SEMIEXPO Vietnam 2025
2025-11-07 - 2025-11-08 | Hanoi, Vietnam, Hanoi, Viet Nam
As the global semiconductor landscape continues to evolve, Vietnam is positioning itself for a promising future in the semiconductor industry.
SEMIEXPO Vietnam will be a pivotal event, exploring opportunities for businesses across the semiconductor value chain, from assembly and testing, to fabless/design. This premier event will highlight how local players can elevate Vietnam’s position in the global semiconductor supply chain. Attendees can look forward to a comprehensive 2-day event, including conferences, exhibitions, workshops, business matching programs, and industry networking sessions. Don’t miss this opportunity to be part of Vietnam’s semiconductor revolution and connect with key players in the industry.
More details for SEMIEXPO Vietnam will be available in Q3 2025. Stay tuned for updates!
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SemIsrael Expo 2025
2025-11-11 | Avenue Convention Center, Airport City, Israel
Connecting the Dots: Empowering the Semiconductor Community
SemIsrael Expo 2025 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry.

The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design houses, labs and universities.​

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Webinar: From RTL to Silicon: Qualcomm Closes the Power Gap with Module-Level Insights
2025-11-11 09:00 - 10:30 | Online
Traditional RTL low power design techniques such as sequential clock gating are widely deployed across the industry. Yet, even after multiple RTL revisions, residual power inefficiencies often remain undetected until silicon, resulting in missed optimization opportunities.
This seminar presents a refined approach to conventional methodologies: a reporting and opportunity identification layer that sits atop clock gating strategies. By prioritizing RTL changes that yield cascading power reductions and exposing hidden savings deep within fan-in and fan-out paths, this approach enables RTL designers to maximize power savings with minimal effort.
We will explore how PowerPro’s module-based reporting framework empowers RTL designers to systematically identify and eliminate power reduction opportunities across all modules in a design. This methodology not only facilitates low-power RTL sign-off but also delivers superior return on investment, measured in watts saved per engineering hour compared to traditional techniques.
Join us to learn how this framework can transform your low power design flow and help you achieve efficient, silicon-proven results.

Speakers:

Suseela Budi
Staff Engineer, Qualcomm

Suseela Budi is a Staff Engineer in the Modem team at Qualcomm, based in Bangalore. She joined the company as a New College Graduate after completing her Master’s degree from the Indian Institute of Science (IISc). Over the past eight years, she has worked extensively across modem implementation and power optimization.
Her recent focus has been on modem power, covering the full workflow from high-level power projections to post-silicon power correlation. Prior to this, she led implementation efforts involving front-end synthesis, formal verification, Conformal Low Power (CLP), and static timing analysis. Suseela brings deep technical expertise and hands-on experience in building efficient and high-performance wireless systems.

Qazi Faheem Ahmed
Principal Product Manager for PowerPro, Siemens EDA

Qazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 20 years of experience spanning across ASIC/FPGA design and EDA.
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Webinar: Don't Let VHDL Debugging Slow You Down! Use Questa One Sim
2025-11-12 08:00 - 09:00 | Online
Join us for this essential webinar where we’ll explore how  Questa One Sim empowers VHDL designers to dramatically enhance their debugging productivity. We’ll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively, and streamline your entire VHDL RTL debug workflow.
This webinar is Part 1 of a two-part series on VHDL debugging with Questa One Sim. Be sure to look out for Part 2, where we’ll dive into VHDL Test Bench Debugging!
What You Will Learn:

Streamline Design Exploration: effortlessly navigate even the most intricate VHDL codebases, making sense of new or legacy designs with unparalleled ease.
Accelerate Waveform Analysis: Leverage powerful waveform debug capabilities like Biometric Search, Expression Builder, and Custom Radix to quickly visualize, filter, and interpret your simulation results, cutting down on analysis time.
Pinpoint Root Causes Rapidly: Utilize advanced techniques such as Driver Tracing, Time Cone analysis, and X-debug to swiftly identify the origin of bugs and understand signal propagation, leading to quicker resolutions.
Visualize and Debug State Machines: Gain a clear understanding of sequential logic by learning how to intuitively visualize and “step through” Finite State Machines, making it simpler to debug complex control logic.

Who Should Attend:

Design Engineers using VHDL

Products Covered:

Questa One Sim

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Speaker:

Nicole Munson
Product Engineer, Siemens EDA

Nicole Munson is a Product Engineer at Siemens EDA supporting Questa One Sim.
She holds a Master’s degree in Electrical Engineering from Case Western Reserve University and specializes in functional design verification techniques for VHDL users and the Aerospace and Defense industry.

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Webinar: AI/ML Algorithm Design and Testing Toward 6G
2025-11-12 10:00 - 11:00 | Online
AI and machine learning (AI/ML) are reshaping wireless communications, promising faster, more efficient, and more intelligent networks. But bringing these algorithms into real-world environments isn’t simple — validation and testing remain major hurdles.
In this webinar, industry expert Abhinav Mahadevan shares how to bridge that gap.
You’ll learn:
• How AI/ML can unlock smarter signal processing and optimized performance.
• The toughest challenges in validating AI/ML for wireless networks — and how to overcome them.
• Practical strategies to ensure accuracy, reliability, and scalability in AI-driven systems.
With real-world case studies and research insights, you’ll walk away with actionable approaches to harness AI/ML for your next-generation wireless designs — helping you accelerate innovation while reducing risk.
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Presenters

Abhinav Mahadevan
AI Technologist, R&D Manager
Abhinav leads the development of advanced machine learning solutions for wireless and RF applications. With over a decade of experience, he has driven the growth of a new product line, served as the lead R&D engineer for the Keysight over the air (OTA) project, contributed to the Keysight 6G Program Office and is now manager in Keysight Labs leading the effort in building machine learning solutions for physical AI.
Abhinav is passionate about integrating artificial intelligence and machine learning with wireless technologies toward 6G.

Nancy Friedrich
Keysight 6G Solutions Expert
Nancy Friedrich is the 6G Thought Leadership Global Development Lead at Keysight covering 6G research and development, use cases, and standard evolution. Previously, she led marketing efforts for Keysight’s RF and industry solutions in the aerospace and defense sector. Prior to joining Keysight, Friedrich served as executive director and editor-in-chief of media brands including Electronic Design, Microwaves & RF, Design News, Power Electronics, and Machine Design.

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Webinar: 5 Expectations for the Compute Market in 2026
2025-11-12 11:00 - 12:00 | Online
November 12, 2025 – 11:00 AM EST
November 13, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Compute Market Trends Reshaping Semiconductors in 2026
Datacenter accelerators, advanced nodes, and geopolitical tensions—what’s next for compute semiconductors.
The compute semiconductor market is entering a transformative period. While datacenter accelerators drive rapid growth, traditional PC and mobile markets face challenges from potential tariffs and economic uncertainties. Advanced node transitions, chiplet architectures, and geopolitical factors are reshaping strategies for manufacturers and designers alike.
In this live TechInsights webinar, our compute experts will highlight five critical developments shaping the compute markets in 2026, providing actionable insights for architects, strategists, and executives navigating this dynamic landscape.
Key Topics You’ll Learn

Custom Silicon & Arm Expansion – Driving IP and ASIC growth in datacenters.
AI-PC & Smartphone Refresh Risks – Navigating uncertain tariffs and market headwinds.
FinFET → Gate-All-Around Transition – Intel’s disruptive backside power delivery vs TSMC leadership at 2nm.
SoC Disaggregation & Chiplets – Reducing costs and increasing design flexibility.
China’s Strategic Independence – Technology and processor self-sufficiency amid US export restrictions.

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Aerospace and Defense Symposium 2025 — El Segundo
2025-11-13 08:30 - 15:30 | DoubleTree by Hilton Hotel LAX – El Segundo, DoubleTree by Hilton Hotel LAX - El Segundo, 1985 E Grand Ave, El Segundo, CA, 90245, United States
Join Chris Johnston, Keysight’s Director of Radar and EW, alongside other Keysight experts, at this year’s Aerospace and Defense Symposium in El Segundo. Gain practical insights, see live demonstrations, and take part in engaging discussions designed to help you stay ahead in our rapidly evolving industry. You’ll walk away ready to accelerate mission-critical product development across the entire lifecycle.
Power up your day with breakfast, where we’ll fuel both your morning and your innovation with the exciting announcement of our latest product launch.
Hands-on sessions will help you:

Understand the technological and financial challenges of advancing Electronic Warfare (EW) test and evaluation.
Explore how LIBERTY’s field programmable gate array (FPGA) processing and modular design deliver fast, scalable, and adaptive test solutions.
Capture and analyze mission-critical signals.
Perform high-speed phased array calibration and beamforming in a compact antenna test range.
Use a high-bandwidth oscilloscope for multi-channel, coherent measurements.

Don’t miss this opportunity to connect with peers and industry experts, explore the latest products, and enjoy a complimentary lunch. Save your seat today.
REGISTER HERE

Webinar: Accelerating Product Development with Computational Materials Engineering
2025-11-13 11:00 - 12:00 | Online
Discover how companies are leveraging ICME to enhance outcomes in consumer goods, fluids manufacturing, optics, and polymer development.
Learn how your R&D team can accelerate the process from materials design to product design and manufacturing.

DATE/TIME:
November 13, 2025
11 AM EST / 5 PM CET / 9:30 PM IST
Venue:
Virtual

Overview
Ansys and Schrödinger are transforming product design and development through Integrated Computational Materials Engineering (ICME).
Materials properties and materials engineering used to be treated as separate domains—molecular-level behavior was disconnected from product-level design and performance, with limited insight into how material choices influence outcomes. The ICME approach bridges this gap by connecting molecular-scale insights with continuum-level simulations and enables engineers and scientists to design not only the structure but also the material itself. This integrated approach accelerates innovation and leads to more efficient, high-performance solutions across industries like consumer goods, automotive, and electronics.
This powerful partnership enables a holistic approach to materials and product development, allowing R&D teams to:
Identify key material requirements:
Use continuum simulation to evaluate the performance-specific material properties and help guide material development process (top-down approach)
Accelerate material discovery:
Screen across chemical libraries and inform continuum simulations with precise molecular data (bottom-up approach)
Optimize performance:
Evaluate variations in product performance originating from uncertainties in synthesized material and design variables to perform robust material and design optimization loops
Discover how companies are leveraging ICME to enhance outcomes in consumer goods, fluids manufacturing, optics, and polymer development.
Learn how your R&D team can accelerate the process from materials design to product design and manufacturing.

What Attendees Will Learn

Integrated Computational Materials Engineering (ICME) in action
Speeding up materials discovery using molecular simulation
Linking molecular properties to product performance
Smarter, faster materials selection for R&D
Real-world applications in consumer good, optics, polymers, and manufacturing

Who Should Attend and Why
Chemists, Engineers, Simulation Engineers, R&D managers, Executives
Bridge the Gap Between Molecular and Engineering Design: Learn how Ansys and Schrödinger’s ICME approach connects molecular-level insights with continuum simulations to unlock breakthrough innovations.
Accelerate Material Innovation: See how R&D teams are reducing time and cost in material discovery by integrating computational chemistry with simulation-driven design.
Improve Product Performance: Understand how to optimize both materials and product design together to achieve superior performance and reliability in real-world conditions.
Explore Real-World Applications: Discover how leading companies are applying ICME in areas like fluids manufacturing, consumer goods, optics, and polymer development to gain a competitive edge.
Enable Smarter Materials Decisions: Learn how to identify performance-critical material properties early in the design cycle to guide development and reduce downstream risks.

Speakers

Adarsh Chaurasia, Team Lead Application Engineering ,Ansys/Synopsys
David Nicholson, Applications Scientist at Schrödinger

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ISTFA 2025
2025-11-16 - 2025-11-20 | Pasadena Convention Center, Pasadena Convention Center, 300 E Green St, Pasadena, CA, 91101, United States
Plan today to attend and participate at ISTFA 2025!
Join us for the 51st International Symposium for Testing and Failure Analysis (ISTFA) is set to take place in Pasadena, California, from November 16-20, 2025. As the premier event for the microelectronics failure analysis community, ISTFA brings together leading experts, industry professionals, and researchers to share insights, innovations, and methodologies in the field. This year’s theme, “Scaling Beyond Moore’s Law: Heterogeneous Computing and Advanced Packaging,” reflects the industry’s evolving landscape, where traditional scaling approaches are being challenged by the integration of diverse technologies and packaging strategies. Attendees will engage in a comprehensive program that includes keynote presentations, technical sessions, workshops, and networking opportunities, all designed to foster collaboration and knowledge exchange.
The symposium will explore cutting-edge topics such as the challenges and solutions in heterogeneous integration, advanced packaging techniques, and the role of failure analysis in ensuring the reliability of next-generation microelectronics. Participants can expect to gain valuable perspectives on how to navigate the complexities of these advanced technologies, enabling them to drive innovation in their respective fields. With a focus on both theoretical and practical applications, ISTFA 2025 promises to be an invaluable platform for professionals looking to enhance their expertise and stay at the forefront of microelectronics testing and failure analysis.
Don’t miss out on the 51st International Symposium for Testing and Failure Analysis (ISTFA) in Pasadena, California!
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SC25
2025-11-16 - 2025-11-21 | America’s Center, America’s Center, 701 Convention Plaza, St. Louis, MO, 63101, United States
The International Conference for High Performance Computing, Networking, Storage, and Analysis
HPC Ignites.
St. Louis is the place to be this fall as the high performance computing community convenes for an exhilarating week of sessions, speakers, and networking at its finest. SC is an unparalleled mix of thousands of scientists, engineers, researchers, educators, programmers, and developers who intermingle to learn, share, and grow.
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Hardwear.io Security Trainings and Conference Netherlands 2025
2025-11-17 - 2025-11-21 | Amsterdam Marriott Hotel, Stadhouderskade 12, Amsterdam, 1054 ES, Netherlands
The Netherlands has been the home for Hardwear.io since 2015.
We are very excited to host the industry from automotive, healthcare, semiconductor, IoT, industrial control systems and Govt/Defences Institutes to join us for Hardwear.io NL scheduled on 17th Nov to 21st Nov 2025 at Amsterdam Marriott Hotel
Learn, share, build, collaborate with 100+ companies attending Hardwear.io NL from around the globe to examine the current and future challenges in hardware security.
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2025 TSMC Open Innovation Platform Ecosystem Forum - Taiwan
2025-11-18 | Sheraton Hsinchu Hotel, Sheraton Hsinchu Hotel, No. 265號, E Section 1, Guangming 6th Rd, Zhubei City, Hsinchu County, 302, Taiwan
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM
Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event; it’s a dynamic hub where the brightest minds converge to ignite the next wave of innovation.
As the AI revolution proliferates from the data center to the edge and becomes integrated into every application, the need for high-performance and energy-efficient designs is becoming paramount. Through a series of compelling, multi-track presentations, you’ll gain a firsthand understanding of how the ecosystem is collaboratively tackling these critical design requirements.
AI is also transforming how chip and multi-die designs are done. This year, the forum will highlight how the ecosystem is harnessing the immense potential of AI in next generation of design solutions for TSMC’s advanced process and packaging technologies. Prepare to be immersed in a wealth of knowledge as industry trailblazers and TSMC’s ecosystem partners offer valuable insights into the latest breakthroughs.
The event provides a unique opportunity for you to engage with thought leaders and innovators, whether you join in-person at locations across North America, Japan, Taiwan, China, and Europe, or participate online.
Don’t miss this opportunity to connect with the leading players of semiconductor technology and be part of shaping tomorrow’s innovations, today!
Opportunity to gain insights into

Solutions needed to address energy efficiency and other challenges impacting the next-generation AI chips and corresponding design flows and methodologies for TSMC A16™, N2, and N3 processes
Consistent progress in design enablement and solution development for TSMC’s advanced processes including A14, TSMC A16™ and N2
Latest advancements in design solutions on TSMC 3DFabric® chip stacking (including InFO, CoWoS®, TSMC-SoIC®, TSMC-SoW™), as well as updates on the TSMC 3DFabric Alliance
AI-assisted design flows for 2D and 3DIC design productivity and optimization
Design enablement technologies, IPs, and solutions targeting the latest HPC, AI/ML, automotive, mobile/5G and IoT applications
Comprehensive design solutions for specialty technologies including ultra-low power, ultra-low voltage, analog migration, RF, and mmWave
Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market

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MASTER CLASS: Component-based transfer path analysis and virtual prototyping
2025-11-18 - 2025-11-20 | Leuven, Belgium, Leuven, Belgium
The Component-based TPA and Virtual Prototyping Master Class is a 3-day live training event that brings together the NVH community at the NVH facility in Leuven, Belgium. This immersive program features theoretical lectures and insights from industry leaders, supported by live demonstrations, interactive sessions, and more than 9 hours of hands-on workshops in small groups.
The master class offers a comprehensive learning experience, providing insights and best practices for transitioning from physical prototype troubleshooting to virtual prototype prediction.

Why Attend?

Historically, NVH validation has relied on physical prototypes, but the growing number of vehicle variants has made this approach unsustainable within reasonable budgets and timelines. The shift to electrified vehicles has also introduced new noise sources that require attention.
To address these challenges, the industry is embracing modular development methods, creating invariant component models through simulations or tests. These models contain the necessary data to predict NVH performance when assembled in virtual environments. This Siemens educational master class is designed to equip you with the knowledge and tools to navigate this transition towards zero physical prototypes for NVH development.

What’s new?

This edition of the master class places a stronger emphasis on hands-on learning, with more than 9 hours of workshops in small groups. This format allows you to experience the software firsthand and gain practical insights you can immediately apply to your NVH engineering workflows.
Additionally, the event will introduce a new, patented technology called AutoCMX. This revolutionary solution enables the construction of fully automated blocked force test benches, empowering your organization to take the next step in putting this cutting-edge technology into practice.

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SEMICON Europa 2025
2025-11-18 - 2025-11-21 | Messe Munchen, Munich, Germany
SEMICON Europa 2025 is co-located with productronica and will take place in November 18-21, 2025 in Munich, Germany. This year’s theme Global Collaborations for European Economic Resilience expresses that global collaborations are not just beneficial for Europe’s resilience, they are essential. In today’s interconnected world, Europe cannot afford to operate in isolation. By working closely with other nations, Europe can safeguard its prosperity, sustainability, and security for future generations.
This approach will enable the industry to create a future where technological innovations and environmental sustainability thrive together.
We are thrilled to meet you this year!
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Webinar: Power Supply ICs for efficient computing & networking
2025-11-18 09:00 - 10:00 | Online
The importance of second-stage optimization in power delivery for data centers and high-performance computing cannot be overstated. With the potential to increase energy efficiency from an average of 85% to approximately 90%,
Infineon is at the forefront of developing innovative solutions to meet the rapidly growing demands of advanced computing. In this session we will explore the role of multiphase controllers, power stages, and point of loads in powering high-current GPUs/SoCs in next-gen data centers (servers and networking).
Our expert will delve into Infineon’s innovations in this area, showcasing our comprehensive portfolio and highlighting its unique value proposition, which is specifically designed to optimize our customers’ TCO.
Agenda:

Market trends and requirements
Why Infineon?
Multiphase controllers
Power stages
Analog and digital Point of Loads

Event details

Session 1 – Asia focus
18th November, 2025: 9 am (CET) – 12.30 pm (IST) – 3 pm (CST) – 4 pm (JST)
Session 2 – US focus
18th November, 2025: 6 pm (CET) – 12 pm (EST) – 9 am (PST)

Speaker

Vijay Viswanathan

Director of product marketing for low voltage POL regulators
Over the past 24 years, Vijay has been working in various roles including R&D (MOSFET design), multiphase DC-DC product marketing for server, AI, networking, telecom, and high-end consumer applications. Vijay received his Ph.D. & M.S degree in Electrical Engineering from University of South Florida (USA) and B.S. degree from University of Madras (India) in Electronics and Communications Engineering.

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Webinar: How PCIe Multistream Architecture is enabling AI Connectivity at 64 GT/s and 128 GT/s
2025-11-18 09:00 - 10:00 | Online
Featured Speakers:

Diwakar Kumaraswamy, Sr. Staff Technical Product Manager, Synopsys

AI and HPC workloads push fabric speeds to deliver higher parallelism and utilization at extreme data rates. To support these higher rates, the controller architecture needs to be completely redefined resulting in the new PCIe controller Multistream architecture where multiple TLP streams to be serialized over the link. This shift from the single-stream model of prior generations impacts how application interfaces and user logic are designed.
In this webinar, we will examine the architectural differences compared to controller’s architecture limited to 32GT/s or less, focusing on how multiple application interfaces are supported, their effect on link utilization, and the mechanisms for maintaining ordering across streams.
We will also analyze the implications for FLIT versus Non-FLIT mode, along with practical considerations for AXI bridge configuration under the new architecture.
Why You Should Attend:

Understand Industry Bottlenecks
Explore Practical Integration Solutions
Gain Design-Level Insights

Register now to deepen your understanding of PCIe Multistream operation and make informed design choices for AI and HPC SoCs at the interface and system levels.

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Featured Speakers

Diwakar Kumaraswamy
Sr. Staff Technical Product Manager, Synopsys
Diwakar is a Technical Product Manager at Synopsys with over 15 years of experience in SoC design and high-speed interconnects. He specializes in PCIe architecture for AI and HPC, supporting next-generation connectivity solutions for advanced infrastructure.

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Advanced Measurements Seminar - Chandler
2025-11-18 09:00 - 15:30 | DoubleTree by Hilton Phoenix Chandler, DoubleTree by Hilton Phoenix Chandler, 7475 W Chandler Blvd, Chandler, AZ, 85226, United States
Join Suren Singh, Application Engineer for Emerging Technologies, and fellow Keysight experts for a hands-on seminar that will help you do what you couldn’t before in RF measurement. Whether you’re looking to advance your expertise or stay ahead of emerging technologies, this hands-on seminar will equip you with the practical tools and skills you need to push your capabilities further.
Start your day with a networking breakfast to power up both your morning and your innovation, where you will hear the exciting announcement of our latest product launch.
Then, join us to discover:

The latest PNA-X Pro Vector Network Analyzer capabilities and applications.
Phase-coherent pulse techniques using vector signal generators.
Signal analysis with advanced error vector magnitude (EVM) measurements and capabilities.
Our new power supply and electronic load solutions.

Take this opportunity to explore new measurement techniques, connect with peers, and get a firsthand look at where RF measurement is headed.
Lunch is on us. Register now to save your spot!
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Sensing (R)evolution: Sustaining Europe's Leadership
2025-11-19 - 2025-11-20 | ICM – International Congress Center Messe München, Messe München GmbH, Messegelände, München, 81823, Germany
Discover how the latest MEMS and imaging technologies are enabling next-level value creation across industries. Explore cutting-edge AI-enhanced sensing, data fusion, and their transformative impact on automotive, healthcare, and smart systems. Learn how these technologies are driving Europe’s leadership in the sensor revolution while shaping a more intelligent, interconnected future.
Join us in Sensing (R)evolution: Sustaining Europe’s Leadership!
REGISTER HERE

MEMS & Imaging Sensors Summit 2025
2025-11-19 - 2025-11-20 | ICM – International Congress Center Messe München, Messe München GmbH, Messegelände, München, 81823, Germany
Discover how the latest MEMS and imaging technologies are enabling next-level value creation across industries. Explore cutting-edge AI-enhanced sensing, data fusion, and their transformative impact on automotive, healthcare, and smart systems. Learn how these technologies are driving Europe’s leadership in the sensor revolution while shaping a more intelligent, interconnected future.
Join us in to Sensing (R)evolution: Sustaining Europe’s Leadership!
REGISTER HERE

Webinar: Advancing NTN: Challenges and Opportunities in 6G
2025-11-19 10:00 - 11:00 | Online
NTNs extend coverage everywhere; 6G delivers the tools to optimize, scale, and seamlessly integrate them.
Join our expert roundtable for a high-impact discussion on today’s NTN landscape. Discover how 6G will accelerate their evolution. Learn about the engineering challenges and opportunities shaping the future. You’ll walk away with insights into real-world deployments, emerging use cases, and the innovations driving NTN adoption.
In this session, you’ll explore:

Key 6G NTN enablers driving smarter networks.
Steps toward a fully integrated 3D network.
New services unlocked — from IoT to broadband.
Benefits and challenges for satellite communications.
Expanded coverage powering future machine-type communication.

This is where cutting-edge theory meets real-world deployment. Secure your spot today and stay ahead of the curve.

Presenters

Richard Soden
Director, Space and Satellite Solutions
As Director for Keysight’s Space and Satellite Solutions, Richard leads solution and application engineers, workflow architects, and other technical staff to help customers succeed with mission-critical projects and programs. He guides the development of software, hardware, and services solutions for the space and satellite industry, including terrestrial to non-terrestrial communications evolving from 5G to 6G. Richard holds a bachelor’s degree in optoelectronics and laser systems and a PhD in optical based nondestructive testing techniques. He joined Keysight in 2004.
Richard is an enthusiastic advocate for fostering collaboration between the space industry and Keysight, driving innovation and solutions to aid the advancement of space technology.

Jani Tolonen
Product Manager, Channel Emulation Solutions
Jani Tolonen, Product Manager at Keysight Finland, focuses on developing advanced channel emulation solutions for areas including 5G NTN and 6G. His work involves integrating various use cases, such as satellite link modeling, network integration, and interconnectivity.
Jani began his career in the wireless industry in 2000 and earned a master’s degree in engineering in 2003. He has a strong interest in space and satellite technologies, particularly following the introduction of 3GPP standards on 5G NTN.

Nancy Friedrich
Keysight 6G Solutions Expert
Nancy Friedrich is Keysight’s 6G solution expert, covering 6G research and development, use cases, and standards evolution. Previously, she led marketing efforts for Keysight’s RF and industry solutions in the aerospace and defense sector. Prior to joining Keysight, Friedrich served as executive director and editor in chief of media brands including Electronic Design, Microwaves & RF, Design News, Power Electronics, and Machine Design.

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From Theory to Practice: Applying Timing Constraints Workshop
2025-11-19 10:00 - 16:00 | Online
From Theory to Practice: Applying Timing Constraints Workshop
Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices.
This workshop provides experience with understanding timing constraints for adaptive SoCs and strategies to improve design performance.
Gain experience with:

Applying basic timing constraints
Understanding virtual clocks
Performing timing analysis
Applying timing exception constraints
Reviewing timing reports

This course focuses on the Versal architecture.
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
REGISTER HERE

Webinar: 5 Expectations for the Connectivity Market in 2026
2025-11-19 11:00 - 12:00 | Online
Discover the 5 Critical Connectivity Market Trends Reshaping Semiconductors in 2026
5G, ambient computing, and RF innovation—what’s next for connectivity semiconductors.
The connectivity semiconductor industry is evolving rapidly as 5G matures, geopolitical shifts influence supply chains, and ambient/always-on computing paradigms drive next-generation RF architectures. From smartphones to IoT, wearables, and satellite networks, the connectivity landscape is transforming at an unprecedented pace.
In this live TechInsights webinar, our connectivity experts will outline five critical developments shaping the $75 billion RF semiconductor market in 2026, providing actionable insights for designers, module suppliers, and strategists.
Key Topics You’ll Learn

5G Device RF Densification (Sub-3 GHz) – Advanced Phase 8 architectures, new RF IC processes (GF, UMC, TowerSemiconductor, X-Fab), engineered low-loss substrates, RF SOI, POI, and high-efficiency GaAs/SiGe PA designs.
China Mobile RF Leadership – Huawei’s portfolio expansion (Phase 7 FEMs, BAW filters), 5G-Advanced dominance, 6G R&D, and implications for Western RF vendors amid state subsidies and US tariffs.
Evolved Smartphone & Ambient Compute Era – Growth in 5G/5G-A SA devices, AI-driven services, Edge AI/IoT, automotive connectivity, wearables, and AR glasses; opportunities in BT/Wi-Fi/UWB, V2X, Wi-Fi HaLow, 5G RedCap, and Matter over Thread.
Satellite NTN & D2C Expansion – Integration of satellite coverage into mobile networks (T-Mobile/Starlink), implications for smartphone OEMs and RF Front End design for 3GPP NTN compliance.
“Always ON” Connectivity as a Differentiator – Modem-embedded AI for seamless cellular/Wi-Fi switching, enhanced RF FE requirements, new RF filters, antenna tuners, and potential consolidation of smartphone radio module suppliers.

REGISTER HERE

2025 ICCAD
2025-11-20 - 2025-11-21 | Chengdu, China, Chengdu, China
About ICCAD-Expo

In the development of China’s integrated circuit design industry, the China Integrated Circuit Design Industry Exhibition (ICCAD-Expo) has consistently played a vital role in promoting industrial clustering, connecting industry resources, and identifying industry trends. Since its inception in 1994, ICCAD-Expo has been successfully held for 30 sessions in Shenzhen, Hangzhou, Chengdu, Wuhan, Shanghai, Zhuhai, Dalian, Beijing, Xiamen, Wuxi, Xi’an, Hefei, Hong Kong, Tianjin, Changsha, Nanjing, Chongqing, and Guangzhou, becoming one of the most influential industry events in China’s semiconductor industry. Over the years, ICCAD-Expo ‘s themes have been aligned with the development of the electronic information industry in the host cities, promoting the synchronized development of related industries in each host city and the national integrated circuit industry.
ICCAD-Expo 2025 , themed “Chengdu and Chongqing, One Core, One Screen,” will explore in depth the opportunities and challenges facing the integrated circuit industry, particularly the integrated circuit design industry, and enhance innovation capabilities and strengthen the comprehensive capabilities of China’s integrated circuit industry chain to meet market demand and improve international competitiveness. The conference will create a platform for communication and cooperation for enterprises in all links of the integrated circuit industry chain, and build a platform for communication and cooperation in technology, market, application, investment and other fields for integrated circuit design companies.

REGISTER HERE

Webinar: Powering the heart of AI - 48 V to core optimization
2025-11-20 09:00 - 10:00 | Online
This webinar provides an in-depth discussion about the challenges posed by AI’s increasing power requirements to voltage regulation, more specifically physical limitations such as power distribution losses, thermal and cooling limitations, and power density issues.
It then explores innovative technologies designed to address these challenges, for example chip-embedded modules, thermally efficient inductors, and novel power module designs.
Lastly, our expert will delve into novel system-level architectures, discussing the pros and cons of discrete vs module voltage regulation, and vertical vs later power flow, to offer comprehensive solutions for efficiently powering AI core.
Agenda:

AI’s growing power hunger and implications
Physical challenges in powering the processor
Innovative technologies in powering AI (including power modules deep dive)
Innovative system-level architectures to boost efficiency & power density

Event details

Session 1 – Asia focus
20th November, 2025: 9 am (CET) – 12.30 pm (IST) – 3 pm (CST) – 4 pm (JST)
Session 2 – US focus
20th November, 2025: 6 pm (CET) – 12 pm (EST) – 9 am (PST)

Speaker

Paul Yeaman

Director of power module design engineering
Paul boasts over 28 years of experience in the power engineering, the last three of which as director of engineering at Infineon. With a strong background in high-current, multi-phase DC/DC, and point-of-load (PoL) solutions targeting data centers and high-end computing/AI applications, he helps customers architect and design next-generation AI power solutions, unlocking their full potential.

REGISTER HERE

Webinar: Wireless Coexistence Testing for Medical Devices
2025-11-20 10:00 - 10:30 | Online
Wireless connectivity is the backbone of modern medical technology, but it is also one of its greatest vulnerabilities. In connected hospitals and operating rooms, dozens of devices share a limited spectrum. Even minor interference can disrupt data, delay critical responses, and threaten patient safety.
Regulators now require proof that devices coexist reliably in complex RF environments. Achieving this goes beyond compliance, calling for early validation, realistic simulation, and a deep understanding of real-world performance.
Join this online event to learn how to design and validate wireless coexistence for connected medical devices, with practical strategies to:

Uncover vulnerabilities early by simulating realistic RF conditions.
Identify performance degradation thresholds and mitigate interference risk.
Apply standards such as ANSI C63.27 and AAMI TIR 69.
Learn how to protect patients with medical devices that perform flawlessly in even the most crowded wireless environments.

Presenter

Bill Koerner
Senior Application Engineer, General Electric Measurement Solutions (GEMS) group
Bill is a Senior Application Engineer with Keysight’s General Electric Measurement Solutions group. He is responsible for the development and support of opportunities for the wireless regulatory test solutions and an active member in the FCC Telecommunication Certification Bodies (TCB) group and the ETSI Broadband Radio Access Network (BRAN) working group. Prior to joining Keysight, Bill worked as a RF/Microwave Systems Engineer with Hewlett-Packard for over ten years. In that role, he focused on satellite, aerospace and cable TV applications, covering vector network analyzers, frequency agile signal simulators, phase noise, spectrum analysis, and cable TV proof of performance measurements.

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Webinar: Sensing the 6G Future: Insight from the Wireless Channel
2025-11-20 10:00 - 11:00 | Online
6G is transforming wireless networks from a channel for communication into a powerful tool for sensing the world around us. Beyond connecting people and devices, 6G opens the door to applications such as gesture recognition, object detection, and location awareness — capabilities that demand new approaches to modeling, simulation, and testing.
In this webinar, our experts will share how next-generation wireless systems are being engineered to both communicate and perceive. You’ll learn:

How wireless signals measure distance, speed, and objects.
How channel state information (CSI) enables sensing.
The key differences between Integrated Sensing and Communication (ISAC) vs. Joint Communication and Sensing (JCAS) — and why they matter.
Use cases, architectures, and waveform innovations for 6G sensing.
Tools for channel emulation, artificial intelligence (AI) detection, and orthogonal frequency-division multiplexing (OFDM) radar.

Reserve your seat today and discover how 6G sensing can unlock new possibilities for innovation, efficiency, and connectivity.

Presenters

Nancy Friedrich
6G Solutions Expert
Nancy Friedrich is Keysight’s 6G solution expert, covering 6G research and development, use cases, and standards evolution. Previously, she led marketing efforts for Keysight’s RF and industry solutions in the aerospace and defense sector. Prior to joining Keysight, Friedrich served as executive director and editor in chief of media brands including Electronic Design, Microwaves & RF, Design News, Power Electronics, and Machine Design.

Michael Millhaem
6G Technical Architect
Michael Millhaem has been Keysight’s 5G / 6G Technical Architect since 2015. In this position, Mike has worked to develop new test architectures for emerging test requirements for infrastructure and user equipment. Prior to his current position, Mike has worked in engineering for test systems targeted at communications and aerospace defense systems and components. Mike holds a BSEE from the University of Illinois, Champaign-Urbana.

REGISTER HERE
