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DTSTART;VALUE=DATE:20260322
DTEND;VALUE=DATE:20260327
DTSTAMP:20260403T104312
CREATED:20260107T033853Z
LAST-MODIFIED:20260107T033853Z
UID:365339-1774137600-1774569599@semiwiki.com
SUMMARY:APEC 2026
DESCRIPTION:Focusing on the practical and applied aspects of the power electronics business. This is not just a designer’s conference; APEC has something of interest for anyone involved in power electronics. \n\nDear Colleagues\,\nIt is my great honor to welcome you to San Antonio for the 41st IEEE Applied Power Electronics Conference and Exposition (APEC). Serving as the General Chair of APEC 2026 is both a privilege and a personal milestone in my journey in the power electronics community. \nMy first APEC was in 2003 when I was a Ph.D. student\, presenting my first conference paper at an international venue. I still remember the excitement of meeting researchers\, engineers\, and industry leaders who shaped the field. That experience inspired me to continue my path in power electronics and has guided my career ever since. After becoming a professor myself\, I have encouraged my students to present their work at APEC\, and I am especially proud that they have received 12 Outstanding Presentation Awards. These achievements reflect both their dedication and the supportive environment of the conference. Together\, these experiences have deepened my connection to APEC and strengthened my belief in its role in nurturing talent and advancing the field. \nAfter 41 years\, APEC has grown into one of the largest technical conferences in North America\, with more than 5\,000 participants from over 50 countries each year. The scale of the conference reflects the energy and innovation of the power electronics community. Here\, engineers\, researchers\, students\, and business leaders come together to learn\, share\, and build the future of power electronics. \nThe technical program at APEC spans the entire landscape of power electronics\, from milliwatts to megawatts\, and from low voltage to high voltage. Applications range from consumer electronics to data centers\, electric vehicles\, the modern power grid\, electrified aircraft\, space exploration\, and many more. \n\nThe Technical Sessions at APEC feature more than 570 high-quality papers\, making the APEC Proceedings the most valuable conference collection in power electronics\, as reflected in the Scientific Journal Ranking (SJR).\nThe Industry Sessions are a unique strength of APEC. With more than 180 presentations\, they provide insights from industry researchers and leading academic experts\, bridging the gap between research and practice and highlighting the real-world impact of power electronics.\nAPEC also offers 18 in-depth\, 3.5-hour Professional Education Seminars\, delivered by renowned speakers who are leading researchers in both academia and industry.\nThe plenary keynotes at APEC deliver vision and inspiration from global leaders who are shaping the future of the field.\n\nThe Exhibition at APEC is the largest power electronics showcase in North America\, featuring around 300 companies as exhibitors. It offers an unmatched opportunity to explore the latest products\, solutions\, and technologies shaping the future of our field. \nThis year we have invested significantly in student activities. The Student Mentorship Program\, the Student Travel Award\, the Student Job Fair\, and the Student Session Assistance Program will provide opportunities for students to grow and engage. We are also excited to introduce the Student Demonstration Competition for the first time at APEC\, creating a new platform for students to showcase their talents and connect with industry. \nAt APEC 2026\, we continue to support professional development for all. The Young Professionals program and the Women in Engineering events provide valuable opportunities to learn\, connect\, and grow. \nI invite you to take full advantage of all that APEC 2026 offers\, whether it is the technical sessions\, the industry presentations\, the exhibition\, or the networking opportunities. I hope you will leave San Antonio with new ideas\, new collaborations\, and renewed energy for the work ahead. \nThank you for being part of APEC 2026. Together\, we will continue to advance the field of power electronics. \nSincerely\, \n\nJin Wang\nGeneral Chair\, APEC 2026\nIEEE Fellow\, Distinguished Professor of Engineering\nThe Ohio State University \n\nREGISTER HERE
URL:https://semiwiki.com/event/apec-2026/
LOCATION:Henry B. González Convention Center\, 900 E Market St\, San Antonio\, TX\, 78205\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-06-193758.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260322
DTEND;VALUE=DATE:20260327
DTSTAMP:20260403T104312
CREATED:20250828T054310Z
LAST-MODIFIED:20250828T054310Z
UID:361067-1774137600-1774569599@semiwiki.com
SUMMARY:IRPS 2026
DESCRIPTION:About IRPS\nFor over 60 years\, IRPS has been the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States\, Europe\, Asia\, and all other parts of the world\, IRPS seeks to understand the reliability of semiconductor devices\, integrated circuits\, and microelectronic systems through an improved understanding of both the physics of failure as well as the application environment. \nIRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world. \nIRPS 2026 focus topics:\n\nNew materials: 2D transition metal dichalcogenides (TMDs)\, (semi)conducting oxides (IGZO\, ITO\, IWO\, InOx\, others)\, (anti)ferroelectrics\, low-k dielectrics\, reliability of capacitors\, junctions\, FETs\n3D packaging and heterogeneous integration: Reliability of 3D\, enhanced 2D\, chiplets\, Si bridge\, interposer\, RDL technology\, hybrid bonding\, micro-bump\, Cu-pillar and other interconnects\nData Center Reliability: Emerging trends in Reliability/Availability/Serviceability\, silent data corruption\, reliability at scale\, AI and HPC workloads\, On-chip telemetry\, thermals\, SER\n\nREGISTER HERE
URL:https://semiwiki.com/event/irps-2026/
LOCATION:Loews Ventana Canyon Resort\, Loews Ventana Canyon Resort\, 7000 N Resort Dr\, Tuscon\, AZ\, 85750\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/ieee_international_reliability_physics_symposium_irps_cover.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260317T090000
DTEND;TZID=America/Los_Angeles:20260317T170000
DTSTAMP:20260403T104312
CREATED:20260107T033429Z
LAST-MODIFIED:20260107T033429Z
UID:365336-1773738000-1773766800@semiwiki.com
SUMMARY:Wide-Bandgap Developer Forum 2026
DESCRIPTION:Join us again this year as our experts spend a whole day sharing their technical knowledge and expertise in SiC and GaN technology and in a wide range of applications. \nFor those who attend every year\, it will once again be an exciting\, technically challenging day focused on wide-bandgap technology. \nFor newcomers\, it marks the start of a new series of events that has been growing in popularity for years. \nThe keynote speech by our division presidents Dr. Peter Wawer (Green Industrial Power) and Adam White (Power & Sensor Systems) will open the event live from our studio in Munich. \nRegistration begins in early February. \nIn the meantime\, we invite you to join the Infineon Developer Community and reach out to our experts. Simply post your questions in the dedicated SiC or GaN forums and our community around the world will get back to you with answers. \n\n\n\n\n\n\n\n\nWho should attend\n\n\n\n\n\n\n\n\nThis forum is ideal for: \n\nR&D Engineers\nDesign Engineers\nPre-development Engineers\nApplication Engineers\nProduct Designers\nTechnical Researchers\nDesign Houses\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/wide-bandgap-developer-forum-2026/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-06-193300.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260316
DTEND;VALUE=DATE:20260320
DTSTAMP:20260403T104312
CREATED:20260107T033143Z
LAST-MODIFIED:20260107T033143Z
UID:365333-1773619200-1773964799@semiwiki.com
SUMMARY:2026 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN)
DESCRIPTION:Overview\n\n\n\nThe 2026 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN) will be held at the Monterey Marriott in Monterey\, CA from March 16-19\, 2026. \nThe FCMN will bring together scientists and engineers interested in all aspects of the characterization technology needed for nanoelectronic materials and device research\, development\, integration\, and manufacturing. All approaches are welcome: chemical\, physical\, electrical\, magnetic\, optical\, in situ\, and real-time control and monitoring. The semiconductor industry is evolving rapidly:  the conference will highlight major issues and provide critical reviews of important materials and structure characterization and nearline/inline metrology methods\, including hardware\, data analysis\, and AI and machine learning\, as the industry both extends the technology deep into the nanoscale and increases the diversity of devices and systems. \nThe conference consists of formal invited presentation sessions and poster sessions for contributed papers. The poster papers cover new developments in materials and structure characterization/metrology down to the nanoscale. The conference began in 1995\, and this meeting is the 15th in the series. \n\n\n\nTestimonials\n“There were a total of 34 talks and 81 poster presentations that summarized major issues and provided critical reviews of crucial semiconductor developments and techniques needed as the industry evolves to silicon nanoelectronics and beyond.”\n-Alex Braun\, “A Jaunt Through Nanotechnopolis\,” Semiconductor International. \n“If you want to meet\, greet\, and learn from the world‘s experts in metrology\, this is the place to be.”\n-Dan Hutcheson\, The Chip Insider. \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/2026-international-conference-on-frontiers-of-characterization-and-metrology-for-nanoelectronics-fcmn/
LOCATION:Monterey Marriott\, 350 Calle Principal\, Monterey\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-06-193036.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260316
DTEND;VALUE=DATE:20260320
DTSTAMP:20260403T104312
CREATED:20260107T032935Z
LAST-MODIFIED:20260107T032935Z
UID:365330-1773619200-1773964799@semiwiki.com
SUMMARY:NVIDIA GTC AI Conference
DESCRIPTION:NVIDIA GTC is the premier global AI conference\, where developers\, researchers\, and business leaders come together to explore the next wave of AI innovation. From physical AI and AI factories to agentic AI and inference\, GTC 2026 will showcase the breakthroughs shaping every industry. \nJoin us in venues throughout downtown San Jose for inspiring sessions\, hands-on training\, and opportunities to connect with experts and peers—and be part of the unique GTC experience.  \nREGISTER HERE
URL:https://semiwiki.com/event/nvidia-gtc-ai-conference/
LOCATION:San Jose Convention Center\, 150 W San Carlos St\, San Jose\, CA\, 95113\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-06-192900.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260316
DTEND;VALUE=DATE:20260318
DTSTAMP:20260403T104312
CREATED:20260122T224011Z
LAST-MODIFIED:20260122T224011Z
UID:366015-1773619200-1773791999@semiwiki.com
SUMMARY:The Samson International Smart Mobility Summit
DESCRIPTION:Experience:\n\nTech exhibition featuring 100+ groundbreaking mobility startups\nKeynote speakers\, Panels and Robust discussions on emerging themes\nTailored satellite events\, B2B engagements\, site visits and curated forums\nWelcoming remarks by the Minister of Transport & Road Safety\nA global audience of mobility movers and shakers for immersive networking and business opportunities\n\nStep into the mobility Revolution with AI\, sustainability and the changing economics of movement. \nFrom cutting-edge startups to industry giants\, global investors to policymakers — this is where the smart mobility ecosystem comes together to connect\, showcase new technologies\, and drive revolutionary collaborations in the land of innovation. \nAbout the Samson International Smart Mobility Summit\n\n\n\n\nThe 9th Annual Sheila and Eric Samson International Smart Mobility Summit will take place on 16-17 March 2026 in Tel Aviv – Israel. \nThe Samson Smart Mobility Summit is one of the leading global platforms for discussion on the future of mobility. It gathers the most distinguished decision-makers\, preeminent business leaders\, innovators\, policymakers\, and academia to explore the trends shaping mobility in the 21st century. \nThe Summit will highlight the themes of innovation in transportation and the evolution of smart mobility solutions and business models. We will explore the challenges\, opportunities\, and implications of efforts worldwide\, examining research and innovation and discussing how policymaking\, global coalitions\, and smart investments can create value for the smart mobility ecosystem worldwide. \nThe core issues that will be discussed this year will be:\n\nRevolutionizing Traffic Management: Harnessing Innovative Technologies to Reduce Congestion and Road Accidents\nInnovative Sustainable Sources of Energy for Mobility: The Road Ahead to Level 5 Autonomy\nTaking to the Skies: The Promise and Challenges of Urban Air Mobility\nEfficient and Connected: The Role of Intelligent Mobility in Building Smarter Cities\nCyber Security for Intelligent Mobility Systems\nBig Data: Accelerating the Transition to Intelligent Transportation\nHow Public Policy Can Foster Innovation and Drive the Adoption of New Mobility Technologies\nScaling Up and Going Global: A Peak into Leading Israeli Companies’ Successes and Challenges\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/the-samson-international-smart-mobility-summit/
LOCATION:Expo Tel Aviv\, Expo Tel Aviv\, Rokach Blvd 101\, Tel Aviv-Yafo\, Israel
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-22-143928.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260316
DTEND;VALUE=DATE:20260318
DTSTAMP:20260403T104312
CREATED:20250624T161345Z
LAST-MODIFIED:20250624T161345Z
UID:357530-1773619200-1773791999@semiwiki.com
SUMMARY:Semitracks Course: EOS\, ESD and How to Differentiate
DESCRIPTION:Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the field failures observed in the electronics industry. Although EOS and ESD damage can at times look quite similar to each other\, the source each and the solution can be quite different. Therefore\, it is important to be able to distinguish between the two mechanisms. The semiconductor industry needs knowledgeable engineers and scientists to understand these issues. EOS\, ESD and How to Differentiate is a 2-day course that offers detailed instruction on EOS\, ESD and how to distinguish between them. This course is designed for every manager\, engineer\, and technician concerned with EOS\, ESD\, analyzing field returns\, determining impact\, and developing mitigation techniques. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what constitutes good EOS and ESD design\, how to recognize devices that can reduce EOS and ESD susceptibility\, and how to design new EOS and ESD structures for a variety of technologies. This skill-building series is divided into five segments: \n\nOverview of the EOS Failure Mechanism. Participants will learn the fundamentals of EOS\, the physics behind overstress conditions\, sources of EOS\, test equipment\, and the results of failure.\nOverview of the ESD Failure Mechanism. Participants will learn the fundamentals of ESD\, the physics behind static generation and discharge\, test equipment\, test protocols\, and the results of failure.\nESD Circuit Design Issues. Participants will learn how designers develop circuits to protect against ESD damage. This includes MOSFETs\, diodes\, off-chip driver circuits\, receiver circuits\, and power clamps.\nHow to Differentiate. Participants will learn how to tell the difference between EOS and ESD. They will learn how to simulate damage and interpret pulse widths\, amplitudes and polarity.\nResolving EOS and ESD on the Manufacturing Floor. Participants will see a number of common problems and their origins.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of electrical overstress\, the models used for EOS\, and the manifestation of the mechanism.\nParticipants will be able to understand the ESD failure mechanism\, test structures\, equipment\, and testing methods used to achieve robust ESD resistance in today’s components.\nThis course will identify the major issues associated with ESD\, explain how they occur\, how they are modeled\, and how they are mitigated.\nParticipants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.\nParticipants will be able to distinguish between EOS and ESD when performing a failure analysis.\nParticipants will be able to estimate a pulse width\, pulse amplitude\, and determine the polarity of an EOS or ESD event.\nParticipants will see examples of common problems that result in EOS and ESD in the manufacturing environment.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-eos-esd-and-how-to-differentiate/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260315
DTEND;VALUE=DATE:20260320
DTSTAMP:20260403T104312
CREATED:20251202T192905Z
LAST-MODIFIED:20251202T192905Z
UID:364227-1773532800-1773964799@semiwiki.com
SUMMARY:OFC 2026
DESCRIPTION:Explore the Ever-Expanding Optical Networking and Communications Industry\nPlenary Session\nEsteemed industry luminaries from Coherent\, NVIDIA and Tesat-Spacecom will headline the event Tuesday\, 17 March. These distinguished speakers will explore cutting-edge technologies\, and provide invaluable insights into the evolving landscape of optical networking and communications. Learn more. \nThe Exhibition\nThe exhibition features more than 700 industry-leading companies representing the entire ecosystem of optical networking and communications. At OFC\, attendees have the opportunity to explore groundbreaking technologies\, innovative optical networking solutions\, specialty fiber products\, optical components\, devices\, systems\, test equipment and software. \nAs a global event\, OFC provides startups with the opportunity to debut while industry leaders set the pace for the future. It includes unveiling pioneering trends that will define the industry’s trajectory and offer solutions to critical global issues such as quantum networking\, artificial intelligence (AI)\, space optics and data center connectivity. View the exhibition floorplan. \nTheater Programs\nThe business of networking-focused programming provides valuable insights into current market trends and emerging technologies. Market Watch\, Network Operator Summit and the Data Center Summit offer perspectives from industry leaders and experts in the field\, highlighting the industry’s current environment and its future. View the theater program listings. \nThe Conference\nOFC’s technical conference has something for everyone. From interactive workshops to symposia\, from special sessions to tutorials. OFC offers an array of industry discussions around hot topics like generative AI and ML for optical networking\, subsea networks\, data center architectures\, space optics\, quantum communications and more. \nThere has been a notable emphasis on energy efficiency to address the escalating power consumption challenges in data centers\, particularly due to the increased capacity needs and the expansion of AI-driven applications. Look for special sessions\, workshops\,  tutorials and invited speaker discussions that explore innovative technologies such as linear drive pluggable optics (LPO)\, co-packaged optics (CPO)\, optical switching and other emerging solutions aimed at reducing power consumption in optical interfaces within the network. View the conference program listings. \nOnline Access to Content\nOFC is held in-person but offers on-demand content at the conclusion of the conference. All technical program sessions will be available on-demand to Full Conference registrants. View the OFC archives. \nFuture Dates\n07 – 11 March 2027 | Los Angeles Convention Center | Los Angeles\, California\, USA \n26 – 30 March 2028 | Los Angeles Convention Center | Los Angeles\, California\, USA \nREGISTER HERE
URL:https://semiwiki.com/event/ofc-2026-2/
LOCATION:Los Angeles Convention Center\, 1201 S Figueroa St\, Los Angeles\, 90015
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Untitled-500-x-550-px.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260312
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T104312
CREATED:20260205T211857Z
LAST-MODIFIED:20260205T211857Z
UID:366410-1773273600-1773359999@semiwiki.com
SUMMARY:LID Silicon Valley 2026
DESCRIPTION:Why you should attend\n\n\n\n\nStep into the future of industry at “The Semiconductor Revolution Behind AI Factories”. Hear from CEA-Leti and global experts on AI chip architectures\, 3D ICs\, optical sensing\, and silicon photonics. \n\nGain insights that could shape your company’s next big move. Don’t miss the chance to connect with the minds driving the next industrial revolution. \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/lid-silicon-valley-2026/
LOCATION:SEMI World Headquarters\, 673 South Milpitas Blvd\, Milpitas\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/Screenshot-2026-02-05-131725.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260311T080000
DTEND;TZID=America/Los_Angeles:20260311T090000
DTSTAMP:20260403T104312
CREATED:20260309T224642Z
LAST-MODIFIED:20260309T224642Z
UID:367313-1773216000-1773219600@semiwiki.com
SUMMARY:Webinar: Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP
DESCRIPTION:Wednesday\, March 11 – 8:00 AM Pacific \nDesign and verification teams consistently tell us that compute subsystems require software bring up much earlier than ever before. They need UEFI and Linux to run in simulation\, they need protocol accuracy from day one\, and they need a predictable path to signoff while integration risks rise every quarter. This struggle has become a shared industry reality. \nIn this session we present a scalable methodology to accelerate the development and verification of Compute Subsystems such as Arm® Neoverse™ V3 Compute Subsystem (CSS)-based designs\, with a shift-left in simulation and signoff using Avery Protocol VIP\, CSS VIP\, Software Aware VIP\, Arm Fast Models and QEMU models. \nThis methodology helps teams reduce integration risks\, shorten turnaround time\, and gain system level confidence long before moving to emulation or prototypes. If you are a design or verification engineer\, a firmware engineer or if you manage a team building next generation compute platforms\, this is an event that will strengthen your technical path forward. \nWhat You Will Learn:  \n\nSoftware Aware Verification IP and applications.\nBlock level / Subsystem Compliance Testing with Software Aware VIP.\nFull CSS HW/FW/SW bring up and UEFI Bootup.\nAdvanced debug of Hardware/Firmware/Software.\n\nWho Should Attend: \n\nVerification Managers and Directors.\nDesign and Verification Engineers.\nFirmware/Software Engineers.\n\nProducts Covered: \n\nAvery Verification IP.\nSoftware Aware VIP.\nSystem VIP (CSS).\n\nSpeakers:\n\n\n\n\n\nLuis E. Rodriguez \nTechnical Product Manager\, Siemens EDA \n\n\n\nLuis E. Rodriguez is a Technical Product Manager at Siemens EDA. \nLuis has 17+ years of experience in SoC and IP functional verification\, specializing in developing market‑leading Verification IP. \nHe has contributed to protocol workgroups including PCIe\, CCIX\, Gen‑Z\, and CXL\, where he helped define CXL 2.0 compliance testing. \nAt Siemens\, he focuses on partnerships and solutions for Software‑Aware VIP and supports cross‑functional integration of Verification IP with Siemens EDA tools and emerging Agentic AI. \nHe holds his master’s degree in computer science from National Taiwan University. \n\n\n\n\n\n\nAmit Tanwar \nSoftware Architect\, Siemens EDA \n\n\n\nAmit Tanwar is a Software Architect at Siemens EDA. \nAmit has 18 years of experience in PCI Express and UVM/SystemVerilog‑based Verification IP development. \nHe specializes in building high‑performance\, scalable\, and software‑aware VIP solutions\, and has contributed to multiple generations of advanced verification architectures across the semiconductor industry. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-shift-left-compute-subsystem-rtl-sign-off-with-software-aware-vip/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-09-154557.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260311
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T104312
CREATED:20260107T032755Z
LAST-MODIFIED:20260220T191555Z
UID:365327-1773187200-1773359999@semiwiki.com
SUMMARY:SNUG Silicon Valley
DESCRIPTION:For more than three decades\, SNUG Silicon Valley has connected engineers\, designers\, and thought leaders with technical experts to network and share best practices for tackling design and verification challenges using Synopsys technologies. The Call for Content invites you to showcase how you are developing tomorrow’s products today with Synopsys solutions. \nThis year\, in addition to our traditional SNUG program\, we are excited to welcome Ansys users to the March 2026 event\, which will also feature topics aligned with Simulation World as part of our expanding content offerings and growing community. \nREGISTER HERE
URL:https://semiwiki.com/event/snug-silicon-valley/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/400x400-v2.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260310T093000
DTEND;TZID=America/Los_Angeles:20260310T160000
DTSTAMP:20260403T104312
CREATED:20260309T223026Z
LAST-MODIFIED:20260309T223026Z
UID:367308-1773135000-1773158400@semiwiki.com
SUMMARY:Silicon Chip Industry Workshop
DESCRIPTION:Join Us At The Next Silicon Chip Industry Workshop\n10 March 2026 9:30-16:00. Registration from 9am.\nPlease see our brochure for further information.  \nPlease register me for the Silicon Chip Industry Awareness Workshop: \nEmail: mail@futurehorizons.com \nTel: +44 1732 740440 \nHoliday Inn\, Kensington High Street\, Wrights Lane\, London\, W8 5SP \nAbout the Workshop\nThis one-day semiconductor workshop provides delegates with a grounding in the basic fundamentals of the Integrated Circuit industry\, its workings\, technology\, markets and importance. \nWorkshop Benefits\n\nWe guarantee you will leave the workshop with a greater understanding of the IC industry\, increasing your industry ‘know-how’ and efficiency levels\nYou will gain a comprehensive understanding of industry terminology\, enabling you to talk the industry language\nIncreased confidence levels allows you to execute day-to-day operations with finesse\nRenews enthusiasm & increases staff morale\nEmployees will have a greater understanding of supplier jargon & can negotiate better deals\nClient’s needs are successfully met resulting in repeat business and referrals\n\nFor further benefits of attending the forecast\, click here. \n“It was great! I can’t remember a seminar of a similar density”.\nEuropean Commission \nBook Your Place\nEmail \nCall: +44 1732 740440 \nPay by PayPal \nWhat Will I Learn?\nPresented in layman terms\, the one day Silicon Chip Industry Workshop provides delegates with: \n\nA grounding in the basic fundamentals of the electronics and Integrated Circuit industry\, from theory to market application.\nAn insight into the semiconductor manufacturing process\, semiconductor technology and equipment\, the industry economics and an understanding of the IT revolution and industry trends.\nA comprehensive understanding of industry terminology\, enabling you to talk the industry talk.\nTo enhance delegate understanding audience interaction is encouraged and semiconductor devices\, material samples and other visual aids are used throughout the workshop.\n\nWho Should Attend?\nThe workshop is aimed at individuals working within the semiconductor and information technology (IT) industries.  It is suitable for those looking for an introduction to the semiconductor industry\, to those with a specialist focus needing an industry overview. \nFor added convenience all our semiconductor workshops and forecast events are still available in-house\, please call +44 1732 740440 or >email  us today. \nREGISTER HERE
URL:https://semiwiki.com/event/silicon-chip-industry-workshop/
LOCATION:Holiday Inn – Kensington High Street\, Holiday Inn - Kensington High\, Wrights LaneStreet\,\, London\, W8 5SP\, United Kingdom
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/03/Screenshot-2026-03-09-152949.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260310
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T104312
CREATED:20250828T050840Z
LAST-MODIFIED:20250828T050840Z
UID:361050-1773100800-1773359999@semiwiki.com
SUMMARY:embedded world 2026
DESCRIPTION:Global platform for the embedded community\nThe embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community\, including leading experts\, key players and industry associations. It offers unprecedented insight into the world of embedded systems\, from components and modules to operating systems\, hardware and software design\, M2M communication\, services\, and various issues related to complex system design. \nIts expertise and sharp focus on technologies\, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers\, system architects\, product managers and technical management. \n\nThe No. 1 hub for the international embedded community\n\n\n\nAs the global platform and the industry place to meet for the embedded community\, embedded world attracts the top experts\, key players and industry associations from all over the world. \nBecome part of the community and use THE industry platform to network and make valuable business contacts! \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/embedded-world-2026/
LOCATION:Exhibition Centre Nuremberg\, Exhibition Centre Nuremberg\, Messezentrum 1\, Nürnberg\, 90471\, Germany
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/145-embedded-world-2026.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260309
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T104312
CREATED:20260107T032607Z
LAST-MODIFIED:20260107T032607Z
UID:365322-1773014400-1773359999@semiwiki.com
SUMMARY:GOMACTech 2026
DESCRIPTION:GOMACTech (Government Microcircuit Applications & Critical Technology Conference)\n“Beyond the Noise”\n\n\n\nGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968\, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC\, and provides a forum for government reviews. \n\nREGISTER HERE
URL:https://semiwiki.com/event/gomactech-2026/
LOCATION:New Orleans Ernest N. Morial Convention Center\, New Orleans Ernest N. Morial Convention Center\, 900 Convention Center Blvd\, New Orleans\, LA\, 70130\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-06-192512.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260309
DTEND;VALUE=DATE:20260313
DTSTAMP:20260403T104312
CREATED:20250624T161151Z
LAST-MODIFIED:20250624T161151Z
UID:357528-1773014400-1773359999@semiwiki.com
SUMMARY:Semitracks Course: Semiconductor Reliability and Product Qualification
DESCRIPTION:Product reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past\, reliability meant discovering\, characterizing and modeling failure mechanisms\, and determining their impact on the reliability of the circuit. Today\, reliability can involve tradeoffs between performance and reliability; assessing the impact of new materials; dealing with limited margins\, and other factors. This requires information on subjects like: statistics\, testing\, technology\, processing\, materials science\, chemistry\, and customer expectations. While customers expect high reliability levels\, incorrect testing\, calculations\, and qualification procedures can severely impact reliability. Semiconductor Reliability and Product Qualification is a 4-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and qualification. This course is designed for every manager\, engineer\, and technician concerned with reliability in the semiconductor field\, qualifying semiconductor components\, or supplying tools to the industry. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what failure mechanisms might occur\, and how to test for them\, develop models for them\, and eliminate them from the product. This skill building series is divided into four segments: \n\nOverview of Reliability and Statistics. Participants will learn the fundamentals of statistics\, sample sizes\, distributions and their parameters.\nFailure Mechanisms. Participants will learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die and at the package level. These include: time-dependent dielectric breakdown\, hot carrier degradation\, electromigration\, stress-induced voiding\, moisture\, corrosion\, contamination\, thermomechanical effects\, interfacial fatigue\, and others.\nQualification Principles. Participants will learn how test structures can be designed to help test for a particular failure mechanism.\nTest Strategies. Participants will learn about the JEDEC test standards\, how to design screening tests\, and how to perform burn-in testing effectively.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the failure mechanisms\, test structures\, equipment\, and testing methods used to achieve today’s high reliability components.\nParticipants will be able to gather data\, determine how best to plot the data and make inferences from that data.\nThis course will identify the major failure mechanisms\, explain how they are observed\, how they are modeled\, and how they are eliminated.\nThis course will offer a variety of video demonstrations of analysis techniques\, so the participants can get an understanding of the types of results they might expect to see with their equipment.\nParticipants will be able to identify the steps and create a basic qualification process for semiconductor devices.\nParticipants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.\nParticipants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-semiconductor-reliability-and-product-qualification/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260303T100000
DTEND;TZID=America/Los_Angeles:20260303T110000
DTSTAMP:20260403T104312
CREATED:20260210T181806Z
LAST-MODIFIED:20260212T175607Z
UID:366569-1772532000-1772535600@semiwiki.com
SUMMARY:Webinar: Intelligent Networks: Power\, Reliability & Maintenance in Telecom
DESCRIPTION:About\nAs global connectivity demands surge\, network infrastructure hardware is under unprecedented pressure to deliver higher performance\, lower latency\, and greater energy efficiency\, while remaining cost-effective and reliable. This challenge is compounded with the explosive growth of AI applications\, emerging 5G and 6G architectures\, virtualization and open interfaces\, adding further strain on legacy systems and supply chains that were never built for this pace of evolution. As reliability remains the primary KPI\, providers must shift from a reactive replacement model to a predictive maintenance model. \nJoin our panel of industry experts as they explore the multidimensional challenges of designing\, deploying\, and maintaining network infrastructure in this new era\, focusing on: \n• Power efficiency and thermal optimization across silicon\, networks\, and data centers\n• Proactive monitoring and predictive analytics\n• Requirements for HW and SW co design in next generation architectures\n• Balancing sustainability goals with total cost of ownership \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intelligent-networks-power-reliability-maintenance-in-telecom/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/1770674564867.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T104312
CREATED:20260107T032340Z
LAST-MODIFIED:20260107T032340Z
UID:365317-1772409600-1772755199@semiwiki.com
SUMMARY:22nd Annual Device Packaging Conference (DPC 2026)
DESCRIPTION:The 22nd Annual Device Packaging Conference (DPC 2026) will be held in Phoenix\, Arizona\, on March 2-5\, 2026. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS). The conference is a major forum for the exchange of knowledge and provides numerous technical\, social and networking opportunities for meeting leading experts in these fields. People who will benefit from this conference include: scientists\, process engineers\, product engineers\, manufacturing engineers\, professors\, students\, business managers\, and sales & marketing professionals. The 2026 conference will feature 4 keynote presentations\, an embedded Global Business Council Plenary Session\, an interactive poster session\, an evening panel discussion\, and more. \nREGISTER HERE
URL:https://semiwiki.com/event/22nd-annual-device-packaging-conference-dpc-2026/
LOCATION:Sheraton Grand at Wild Horse Pass\, Sheraton Grand at Wild Horse Pass\, 5594 W Wild Horse Pass Blvd.\, Phoenix\, AZ\, 85226\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/imaps-DP-2026-logo.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T104312
CREATED:20251211T212817Z
LAST-MODIFIED:20251211T212817Z
UID:364624-1772409600-1772755199@semiwiki.com
SUMMARY:MWC 2026
DESCRIPTION:Making way for The IQ Era\n\nMuch can happen in a year within our ecosystem of innovation and connectivity. As we build on the success of MWC25 and engage with MWC26 to activate a new theme – The IQ Era – the world is already shifting to greater heights of digital awareness. \nIn this new age of intelligence\, the way to a better future is through smarter connection: human ideas leading technology\, commercial impact and societal progress. MWC is where leaders of nations\, business and technology assemble\, and collective knowledge collaborates – make your insight count in The IQ Era. \nWhy attend MWC Barcelona?\nFrom eye-opening innovation to mind-expanding ideas\, global policy to lasting partnerships\, it all starts here. Whether you’re a key player in the connectivity ecosystem\, adjacent industries or the wider world of tech\, you’ll find all you need and more at MWC. \n\nREGISTER HERE
URL:https://semiwiki.com/event/mwc-2026/
LOCATION:Fira Gran Via\, Barcelona\, Fira Gran Via\, Av. Joan Carles I\, 64\, Barcelona\, 08908\, Spain
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2025/12/MWC26_hero_Card_800x533.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T104312
CREATED:20250828T050601Z
LAST-MODIFIED:20251218T210957Z
UID:361044-1772409600-1772755199@semiwiki.com
SUMMARY:DVCON U.S. 2026
DESCRIPTION:DVCon is the premier conference on the application of languages\, tools\, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog\, Verilog\, VHDL\, PSS\, SystemC and e\, as well as general purpose languages such as C\, C++\, Python\, PERL and Tcl. Tools and methodologies include the use of artificial intelligence\, machine learning\, open-source software\, hardware and architecture\, testbench automation\, hardware-assisted verification\, hardware/software co-verification\, formal verification\, functional safety and security\, transaction-level system design\, high level synthesis\, low power design techniques\, 3D chip designs\, IP-based SoC design methods\, reference flows and Mixed Signal design and verification. \nREGISTER HERE
URL:https://semiwiki.com/event/dvcon-u-s-2026/
LOCATION:Hyatt Regency Hotel\, Santa Clara\, CA\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-220509.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260302
DTEND;VALUE=DATE:20260306
DTSTAMP:20260403T104312
CREATED:20250624T160157Z
LAST-MODIFIED:20250624T160157Z
UID:357520-1772409600-1772755199@semiwiki.com
SUMMARY:Semitracks Course: Failure and Yield Analysis
DESCRIPTION:Failure and Yield Analysis is an increasingly difficult and complex process. Today\, engineers are required to locate defects on complex integrated circuits. In many ways\, this is akin to locating a needle in a haystack\, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design\, testing\, technology\, processing\, materials science\, chemistry\, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. Failure and Yield Analysis is a 4-day course that offers detailed instruction on a variety of effective tools\, as well as the overall process flow for locating and characterizing the defect responsible for the failure. This course is designed for every manager\, engineer\, and technician working in the semiconductor field\, using semiconductor components or supplying tools to the industry. \nBy focusing on a Do It Right the First Time approach to the analysis\, participants will learn the appropriate methodology to successfully locate defects\, characterize them\, and determine the root cause of failure. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn to develop the skills to determine what tools and techniques should be applied\, and when they should be applied. This skill-building series is divided into three segments: \n\nThe Process of Failure and Yield Analysis. Participants will learn to recognize correct philosophical principles that lead to a successful analysis. This includes concepts like destructive vs. non-destructive techniques\, fast techniques vs. brute force techniques\, and correct verification.\nThe Tools and Techniques. Participants will learn the strengths and weaknesses of a variety of tools used for analysis\, including electrical testing techniques\, package analysis tools\, light emission\, electron beam tools\, optical beam tools\, decapping and sample preparation\, and surface science tools.\nCase Histories. Participants will identify how to use their knowledge through the case histories. They will learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the tools\, techniques and processes used in failure and yield analysis.\nParticipants will be able to determine how to proceed with a submitted request for analysis\, ensuring that the analysis is done with the greatest probability of success.\nThis course will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.\nThis course will offer a wide variety of video demonstrations of analysis techniques\, so the analyst can get an understanding of the types of results they might expect to see with their equipment.\nParticipants will be able to identify basic technology features on semiconductor devices.\nParticipants will be able to identify a variety of different failure mechanisms and how they manifest themselves.\nParticipants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-failure-and-yield-analysis-2/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260226T150000
DTEND;TZID=America/Los_Angeles:20260226T160000
DTSTAMP:20260403T104312
CREATED:20260217T205841Z
LAST-MODIFIED:20260217T205841Z
UID:366792-1772118000-1772121600@semiwiki.com
SUMMARY:GCU and TSMC’s MSI Pathway Webinar
DESCRIPTION:Description\nThis virtual session is your opportunity to explore Grand Canyon University and TSMC’s one-semester Manufacturing Specialist Intensive\, industry funded pathway. Join to find out how you can start building your future in semiconductor manufacturing trades. Whether you’re looking to upskill\, change career paths\, or take the first step toward hands-on training\, our team will walk you through program details and the enrollment process — all from the comfort of your home. \nBy clicking submit\, you give Grand Canyon University your consent to use automated technology to call and text you at the information above\, including your wireless number\, regarding educational services. You are not required to consent to receive educational services. GCU will never sell your information. By submitting this form\, you agree to GCU’s Privacy Policy located at https://www.gcu.edu/privacy-policy.php. \nREGISTER HERE
URL:https://semiwiki.com/event/gcu-and-tsmcs-msi-pathway-webinar/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/02/c6a6e7ff-26ac-43e0-befa-d87f76d02722.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260224
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T104312
CREATED:20260210T182526Z
LAST-MODIFIED:20260210T182526Z
UID:366572-1771891200-1772150399@semiwiki.com
SUMMARY:DesignCon 2026
DESCRIPTION:The Must Attend Event for Chip\, Board\, and Systems Design Engineers\n\n\n\n\nDesignCon is the premier high-speed communications and system design conference and exposition\, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley. \n\n\nThe Conference – A Systematic Approach to Learning & Discovery\n\n\n\n\nAttend the expertly curated 15-track conference created by engineers for engineers featuring technical paper sessions\, tutorials\, and industry panels covering all aspects of chip\, board\, and systems design. \n» View Full Conference Agenda\n» View All Speakers \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/designcon-2026/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/Screenshot-2026-02-10-102443.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260224
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T104312
CREATED:20250828T050143Z
LAST-MODIFIED:20250828T050143Z
UID:361040-1771891200-1772150399@semiwiki.com
SUMMARY:FLEX 2026 - Technology Summit
DESCRIPTION:FLEX 2026 | TECHNOLOGY SUMMIT | FEBRUARY 24-26\, 2026\nTHE WIGWAM ARIZONA RESORT | PHOENIX\, AZ\nA 25th Anniversary Celebration \nEscape the winter and celebrate 25 years of innovation with us at The Wigwam Arizona Resort in Phoenix\, AZ. \n\nFLEX—Technology Summit is a vibrant networking event designed to foster community building. Connect with like-minded professionals\, share ideas\, and forge lasting relationships that will drive the industry forward. \nAt FLEX\, you’ll experience high-quality technical sessions led by industry-leading speakers who are at the forefront of their fields. Sessions include topics on wearable and harsh environment technologies\, heterogeneous integration and advanced packaging\, flexible hybrid electronics\, printed electronics\, additive manufacturing\, integrated photonics\, flexible displays\, digital twins\, artificial intelligence\, and manufacturing. Additionally\, you’ll gain valuable business insights and market trends that provide a comprehensive view of the state of the industry. \nExplore the solution zone to see cutting-edge technologies and connect with innovations shaping the future. Don’t miss this chance to stay ahead in a rapidly evolving tech landscape. \nREGISTER HERE
URL:https://semiwiki.com/event/flex-2026-technology-summit/
LOCATION:The WIGWAM\, The Wigwam\, 300 E Wigwam Blvd\, Litchfield Park\, AZ\, 85340\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-220051.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260223
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T104312
CREATED:20250624T160729Z
LAST-MODIFIED:20250624T160729Z
UID:357524-1771804800-1772150399@semiwiki.com
SUMMARY:Semitracks Course: Wafer Fab Processing
DESCRIPTION:Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is a 4-day course that offers an in-depth look into the semiconductor manufacturing process\, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique\, and we delve into the current issues related to manufacturing the next generation devices. This course is a must for every manager\, engineer and technician working in the semiconductor industry\, using semiconductor components or supplying tools to the industry. \nBy focusing on the basics of each processing step and the issues surrounding them\, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn basic\, but powerful\, aspects about the semiconductor industry. This skill-building series is divided into three segments: \n\nBasic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. Participants will learn the fundamentals of each processing step and why they are used in the industry today.\nThe Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants will learn how each technique has evolved for use in previous and current generation ICs.\nCurrent Issues in Wafer Fab Processing. Participants will learn how many processing steps are increasingly constrained by physics and materials science. They will also learn about the impact of using new materials in the fabrication process\, and how those materials may create problems for the manufacturers in the future.\n\nThis course is a must for every manager\, engineer\, and technician working in the semiconductor industry\, using semiconductor components\, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline. \n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.\nParticipants will understand the basic concepts behind the fundamental wafer fab processing steps.\nThis course will identify the key issues related to each of the processing techniques\, and their impact on the continued scaling of the semiconductor industry.\nThis course will offer a wide variety of sample problems that participants will work to help them gain knowledge of the fundamentals of wafer fab processing.\nParticipants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition\, ion implantation\, lithography\, and etching.\nParticipants will understand how processing\, reliability\, power consumption and device performance are interrelated.\nParticipants will be able to make decisions about how to construct and evaluate processing steps for CMOS\, BiCMOS\, and bipolar technologies.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-wafer-fab-processing-2/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260223
DTEND;VALUE=DATE:20260226
DTSTAMP:20260403T104312
CREATED:20251219T205158Z
LAST-MODIFIED:20251219T205158Z
UID:364923-1771804800-1772063999@semiwiki.com
SUMMARY:2026 Florida Semiconductor Summit
DESCRIPTION:FSI presents the 4th annual Florida Semiconductor Summit in 2026. Join industry leaders\, innovators\, and exhibitioners as we explore groundbreaking developments and the evolving future of semiconductor manufacturing in Florida.\nYou’re invited to the 2026 Florida Semiconductor Summit! From February 23rd – 25th\, 2026\, the Florida Semiconductor Institute is hosting the fourth annual Florida Semiconductor Summit at the Rosen Shingle Creek. This year’s summit theme is “Semiconductor Manufacturing in Florida: Power. Progress. Possibilities.” This summit offers a unique opportunity to connect with industry leaders\, explore cutting-edge advancements\, and delve into the evolving role of semiconductor manufacturing in the state of Florida. \nWhat Makes this Year’s Summit the Biggest Yet?\nThis year\, we are taking the summit to the next level! Not only are we bringing together industry leaders from top CEOs to leading academics\, we are bringing together rising startups and industry pioneers who are shaping the future of semiconductor technology in our first ever interactive exposition hall. This is your chance to connect with key decision-makers\, gain insights from cutting-edge research\, and explore new business opportunities in one of Florida’s fastest-growing sectors. The summit offers invaluable networking\, knowledge-sharing\, and a front-row seat to innovations that will have deep impacts on the state of Florida. Don’t miss out\, register today! \nREGISTER HERE
URL:https://semiwiki.com/event/2026-florida-semiconductor-summit/
LOCATION:Rosen Shingle Creek\, Rosen Shingle Creek\, 9939 Universal Blvd\, Orlando\, FL\, 32819\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/12/Outlook-3vvtmdsn.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260222
DTEND;VALUE=DATE:20260227
DTSTAMP:20260403T104312
CREATED:20250828T045847Z
LAST-MODIFIED:20250828T045847Z
UID:361037-1771718400-1772150399@semiwiki.com
SUMMARY:SPIE Advanced Lithography + Patterning 2026
DESCRIPTION:From materials to metrology: pushing the limits of lithography\nShare your research\, challenges\, and breakthroughs at this leading semiconductor conference in San Jose \nSubmit your abstract and connect with leading researchers advancing solutions in optical lithography\, EUVL\, patterning technologies\, metrology\, and process integration for semiconductor manufacturing and related applications. \nCall for papers is now open. \nREGISTER HERE
URL:https://semiwiki.com/event/spie-advanced-lithography-patterning-2026/
LOCATION:San Jose McEnery Convention Center\, San José McEnery Convention Center\, 150 W San Carlos St\, San Jose\, CA\, 95113\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-215756.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260219
DTEND;VALUE=DATE:20260221
DTSTAMP:20260403T104312
CREATED:20250624T160935Z
LAST-MODIFIED:20250624T160935Z
UID:357526-1771459200-1771631999@semiwiki.com
SUMMARY:Semitracks Course: Defect-Based Testing
DESCRIPTION:Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example\, today’s application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately\, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease\, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior\, fault models\, and test techniques. This course is a must for every manager\, engineer\, and technician working in IC test\, IC design\, or supplying test hardware and software tools to the industry. \nBy focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior\, participants will learn how to design\, write\, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn basic\, but powerful\, aspects about defect-based testing. This skill-building series is divided into four segments: \n\nElectrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits\, resistive vias\, shorts\, and transistor variations affect the electrical behavior of the individual transistor\, as well as gate elements and larger blocks.\nFault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models\, including IDDQ testing\, at-speed testing\, and delay testing.\nProduction Test Methods. Participants will learn about standard digital testing\, SAF testing\, IDDQ\, timing\, low voltage tests\, and other types of stress tests. They will explore the strengths and weaknesses of each test type.\nThe Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of defect-based testing and its technical issues.\nParticipants will understand the basic concepts of test economics\, yield\, test time\, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.\nThis course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.\nThis course will offer the opportunity to discuss specific test problems with our expert instructors.\nParticipants will be able to identify basic and advanced principles for defect-based test.\nParticipants will understand the difficulties in extending IDDQ testing to leading edge products\, and how to overcome some of these limitations.\nParticipants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.\nThis course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.\nParticipants will learn what tools are available today to implement defect-based testing.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-defect-based-testing/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260218
DTEND;VALUE=DATE:20260221
DTSTAMP:20260403T104312
CREATED:20250828T045643Z
LAST-MODIFIED:20250828T045643Z
UID:361034-1771372800-1771631999@semiwiki.com
SUMMARY:Wafer-Level Packaging Symposium 2026
DESCRIPTION:Formatting Advanced Packaging for the Next Generation\nThe evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically\, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless\, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package technologies beyond conventional limits. The Wafer-Level Packaging Symposium will bring together the foremost experts in the semiconductor industry to examine all aspects of wafer and panel-level packaging\, 3D device packaging\, advanced manufacturing\, and testing technologies. Positioned at the forefront of packaging technology evolution\, this conference offers global attendees the chance to engage with the latest technological and business trends in the heart of Silicon Valley. \nREGISTER HERE
URL:https://semiwiki.com/event/wafer-level-packaging-symposium-2026/
LOCATION:Hyatt Regency San Francisco Airport\, 1333 Bayshore Highway\, Burlingame\, CA\, 94010\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/WLPS_2026_Masthead.png
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DTSTART;TZID=America/Los_Angeles:20260217T100000
DTEND;TZID=America/Los_Angeles:20260217T110000
DTSTAMP:20260403T104312
CREATED:20260113T043754Z
LAST-MODIFIED:20260113T043754Z
UID:365670-1771322400-1771326000@semiwiki.com
SUMMARY:Webinar: How Secure Are Your Critical Aerospace & Defense Systems?
DESCRIPTION:Aerospace\, defense\, and other mission-critical technologies face rapidly evolving hardware threats. A hobbyist can add a single board computer to a consumer device. A nation-state can scale an exploit across critical infrastructure. The attack surface widens fast\, and the security implications are real. \nAdversaries are continuously developing techniques that can compromise mission-critical components\, sometimes before they even reach deployment. From side-channel analysis to fault injection\, attackers are finding new ways to extract sensitive data\, disrupt operations\, and manipulate critical systems. \nJoin us for a technical deep dive into how modern hardware attacks work in practice and what engineering teams can do to build more resilient systems. \nIn this session\, we’ll cover: \n\nReal attack examples on complex systems\, like satellite terminals and commercial drones.\nHow side-channel analysis techniques reveal power\, electromagnetic\, and unintended RF leakage that expose cryptographic operations.\nHow fault injection induces glitches to bypass authentication and break security logic.\n\nYou’ll also see a demo of our Fault Injection Laser System with our Inspector software. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-secure-are-your-critical-aerospace-defense-systems/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203709.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260217
DTEND;VALUE=DATE:20260220
DTSTAMP:20260403T104312
CREATED:20250828T045454Z
LAST-MODIFIED:20250828T045454Z
UID:361030-1771286400-1771545599@semiwiki.com
SUMMARY:Chiplet Summit 2026
DESCRIPTION:All the Solutions for Developing Chiplets\n2025 Keynote Addresses from Industry Leaders: \nAlphawave Semi\, Arm\, Cadence Design Systems\, Keysight\, Open Compute Project\, Synopsys\, Teradyne \n2025’s Main Topics Included: \nAI/ML Acceleration\, Open Chiplet Economy\, Advanced Packaging Methods\, Die-to-die Interfaces\, Working with Foundries \nsignup to be a 2026 SPONSOR / Exhibitor \nREGISTER HERE
URL:https://semiwiki.com/event/chiplet-summit-2026/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/cropped-Chiplet-Logo.jpg
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