SemiWiki

SPIE Advanced Lithography + Patterning 2026
2026-02-22 - 2026-02-26 | San Jose McEnery Convention Center, San José McEnery Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
From materials to metrology: pushing the limits of lithography
Share your research, challenges, and breakthroughs at this leading semiconductor conference in San Jose
Submit your abstract and connect with leading researchers advancing solutions in optical lithography, EUVL, patterning technologies, metrology, and process integration for semiconductor manufacturing and related applications.
Call for papers is now open.
REGISTER HERE

Semitracks Course: Defect-Based Testing
2026-02-19 - 2026-02-20 | Munich, Germany, Munich, Germany
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior, fault models, and test techniques. This course is a must for every manager, engineer, and technician working in IC test, IC design, or supplying test hardware and software tools to the industry.
By focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior, participants will learn how to design, write, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about defect-based testing. This skill-building series is divided into four segments:

Electrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits, resistive vias, shorts, and transistor variations affect the electrical behavior of the individual transistor, as well as gate elements and larger blocks.
Fault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models, including IDDQ testing, at-speed testing, and delay testing.
Production Test Methods. Participants will learn about standard digital testing, SAF testing, IDDQ, timing, low voltage tests, and other types of stress tests. They will explore the strengths and weaknesses of each test type.
The Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.

Course Objectives

This course will provide participants with an in-depth understanding of defect-based testing and its technical issues.
Participants will understand the basic concepts of test economics, yield, test time, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.
This course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.
This course will offer the opportunity to discuss specific test problems with our expert instructors.
Participants will be able to identify basic and advanced principles for defect-based test.
Participants will understand the difficulties in extending IDDQ testing to leading edge products, and how to overcome some of these limitations.
Participants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.
This course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.
Participants will learn what tools are available today to implement defect-based testing.

REGISTER HERE

Wafer-Level Packaging Symposium 2026
2026-02-18 - 2026-02-20 | Hyatt Regency San Francisco Airport, 1333 Bayshore Highway, Burlingame, CA, 94010, United States
Formatting Advanced Packaging for the Next Generation
The evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package technologies beyond conventional limits. The Wafer-Level Packaging Symposium will bring together the foremost experts in the semiconductor industry to examine all aspects of wafer and panel-level packaging, 3D device packaging, advanced manufacturing, and testing technologies. Positioned at the forefront of packaging technology evolution, this conference offers global attendees the chance to engage with the latest technological and business trends in the heart of Silicon Valley.
REGISTER HERE

Webinar: How Secure Are Your Critical Aerospace & Defense Systems?
2026-02-17 10:00 - 11:00 (America/Los_Angeles) | Virtual
Aerospace, defense, and other mission-critical technologies face rapidly evolving hardware threats. A hobbyist can add a single board computer to a consumer device. A nation-state can scale an exploit across critical infrastructure. The attack surface widens fast, and the security implications are real.
Adversaries are continuously developing techniques that can compromise mission-critical components, sometimes before they even reach deployment. From side-channel analysis to fault injection, attackers are finding new ways to extract sensitive data, disrupt operations, and manipulate critical systems.
Join us for a technical deep dive into how modern hardware attacks work in practice and what engineering teams can do to build more resilient systems.
In this session, we’ll cover:

Real attack examples on complex systems, like satellite terminals and commercial drones.
How side-channel analysis techniques reveal power, electromagnetic, and unintended RF leakage that expose cryptographic operations.
How fault injection induces glitches to bypass authentication and break security logic.

You’ll also see a demo of our Fault Injection Laser System with our Inspector software.
REGISTER HERE

Chiplet Summit 2026
2026-02-17 - 2026-02-19 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
All the Solutions for Developing Chiplets
2025 Keynote Addresses from Industry Leaders:
Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne
2025’s Main Topics Included:
AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries
signup to be a 2026 SPONSOR / Exhibitor
REGISTER HERE

2026 IEEE International Solid-State Circuits Conference (ISSCC)
2026-02-15 - 2026-02-19 | San Francisco Marriott Marquis, San Francisco Marriott Marquis, 780 Mission Street, San Francisco, CA, 94103, United States
About ISSCC
The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts.
What’s New

Download the ISSCC 2026 Plenary/Educational Events Flyer
The ISSCC 2026 paper submission site is now open
Download the ISSCC 2026 Call for Papers

REGISTER HERE

SEMICON Korea 2026
2026-02-11 - 2026-02-13 | COEX Auditorium, 513, Yeongdong-daero, Seoul, Gangnam-gu, 06164, Korea, Republic of
Date: Feburary 11-13, 2026
Hours

February 11, 2026 | 10:00-17:00 (Last entry 16:30)
February 12, 2026 | 10:00-17:00 (Last entry 16:30)
February 13, 2026 | 10:00-16:00 (Last entry 15:30)

Venue

COEX (Hall A, B, C, D, E, Grand Ballroom, Platz and ASEM Ballroom)
Westin Seoul Parnas
Grand InterContinental Seoul Parnas

Scale

550 Exhibitors, 2411 booths (2025: 501 exhibitors, 2301 booths)

Highlights
Global Supply Chain
Over 550 semiconductor companies from around the world will participate with 2,411 booths, welcoming 70,000 attendees.
Keynote Speech
Leaders in the semiconductor industry will provide valuable insights for the future.
Tech Conferences
At 30 technology programs, 200 visionaries will share the most noteworthy tech trends shaping the industry.
Business Programs
Investment forums will be held to explore investment opportunities in countries such as the United States and Netherlands.
Supplier Search Program
To support the global expansion of Korea’s semiconductor materials, components, and equipment companies, around 100 business meetings will be conducted with major chip makers.
Workforce Development
Mentoring programs for university students aspiring to pursue careers in the semiconductor industry will be offered.

REGISTER HERE

Webinar: Meet Compact-Q DEER Spectrometer, Your Gateway to Quantum Innovation
2026-02-10 11:00 - 12:00 | Virtual
Intro

The Compact-Q DEER Spectrometer is designed to support researchers in academia and industry to efficiently characterize quantum materials, develop devices for quantum sensing, advance and validate algorithms to control qubits, and other applications in spin-based quantum technologies. The Compact-Q DEER system features a modern microwave architecture, high-resolution AWG, and digital signal processing schemes enabling high flexibility in addressing modern challenges of quantum technologies.

Webinar Overview

The focus of this webinar will be to highlight the capabilities of the Compact-Q DEER spectrometer towards the characterization and coherent control of qubits for quantum technologies. Modern experiments in Quantum Information Science (QIS) demand a state-of-the-art microwave architecture, fast, high-memory, high-resolution AWGs, large transmission and detection bandwidths, and modern digital signal processing features to create the most sophisticated pulse shapes, quantum gates and read-out sequences. Having all of those features incorporated, as well as operating at an intermediate frequency of 500 MHz, and utilizing a cryogen-free 1.5 T magnet with integrated Variable Temperature Insert (iVTI) enabling temperatures from 2 K to RT, the Compact-Q system meets modern demands and provides a versatile and high-fidelity platform for probing qubit properties and execution of quantum algorithms driving innovations in quantum technologies.

What to Expect

During this webinar, we will demonstrate how the Compact-Q DEER is ideally suited for applications in QIS. We will show how broad-band echo sequences can be used to manipulate spin states and how electron spin coherences can be created and detected. We will explain the different spectrometer features, the data acquisition platform along with different experiments, highlighting how the Compact-Q can elevate your research in quantum information science (QIS).

Key Learning Points

Versatility, high-performance, and user-friendly operation of the Compact-Q DEER spectrometer will be highlighted along with:

Easy to use resonator bandwidth control
AWG generated pulses, digital down conversion, and FIR filtering
Pulse shaping and quantum gate optimization
Broadband and selective inversion pulse schemes
Studying spin dephasing mechanisms and materials characterization

Who Should Attend?

Undergraduate and graduate students in chemistry, physics, quantum information science, material science, and related fields
Early-career researchers, postdoctoral fellows, and instrument facility managers familiar or new to EPR spectroscopy
Professors and instructors teaching EPR spectroscopy or related courses
Spectroscopy facility managers
Industry professionals, scientists, and engineers in materials science and quantum technologies industries

REGISTER HERE

Demo Day — Signal Generators
2026-02-05 10:00 - 12:00 | Virtual
Join us for Demo Day – Signal Generators and discover how to accelerate and optimize RF testing with the capabilities offered by these instruments in our test bench.
Learn how to perform power amplifier matching correction with a signal generator’s integrated reflectometer in minutes… not hours. No additional test equipment required.
We will also demonstrate how the multi-port capabilities of the generators enhance critical applications such as coexistence testing optimization, beamforming , and MIMO (multiple-input, multiple-output) spatial multiplexing. The platform delivers precise signals synchronized in frequency, phase, and time, reducing the required space by 75%.
Register today to watch these live demonstrations and chat with Keysight’s RF experts, who will be available to answer your questions throughout the event.
REGISTER HERE

Webinar: Building Efficient, Secure, and Scalable AI Systems with UALink
2026-02-05 09:00 - 10:00 | Online
Date: Feb 05, 2026 | 9:00 AM PST

Featured Speakers:

Varun Agrawal, Product Manager, Synopsys
Jon Ames, Product Manager, Synopsys

Discover how UALink enables open, scalable, secure interconnects for AI workloads—and how Synopsys IP and VIP accelerate adoption.
Why You Should Attend:

Learn about UALink advantages over proprietary interconnects for AI scalability and security.
Explore open ecosystem benefits: multi-vendor interoperability and hyperscale efficiency.
See Synopsys solutions in action: IP, VIP, and transactors for streamlined design and verification.
Gain strategic insights for future-proofing AI infrastructure with open standards.

Featured Speakers

Varun Agrawal
Product Manager, Synopsys
Varun Agrawal is a product manager for verification IP, virtual system adaptors, and protocol solutions for hardware-assisted platforms at Synopsys. He has over 14 years of experience in functional verification with expertise in simulation, emulation, and virtualization domains. He holds a BTech in electronics and communications from NIT Hamirpur, India, and an MBA in marketing from India Institute of Foreign Trade (IIFT), New Delhi, India

Jon Ames
Product Manager, Synopsys
Jon Ames is a principal product manager for the Synopsys Ethernet IP portfolio. Jon has been working in the communications industry since 1988 and has led engineering and market activities from the early days of 10/100 Switched Ethernet through Metro and Transport variants to the latest Data Center and High-Performance Computing Ethernet technologies. Since graduating in Computer Science and Electronic Engineering the in UK, Jon has worked at the leading companies in the networking and silicon solution industries.

REGISTER HERE

Webinar: Synopsys and TSMC Discuss Multi-Die Monitoring, Embedded Test & Repair Flows
2026-02-04 09:00 - 10:00 | Virtual
Date: Feb 04, 2026 | 9:00 AM PST

Featured Speakers:

Dr. Yervant Zorian , Chief Architect and Fellow at Synopsys, President of Synopsys Armenia
Dr. Sandeep K Goel, Senior Director, TSMC

Our upcoming Synopsys webinar features an exciting real-world case study showcasing Synopsys IP and EDA tools with UCIe-based chiplets on advanced TSMC silicon and packaging technologies. See firsthand the silicon proof points for complete die-to-die interconnects, embedded memory, and logic monitoring, test, and repair.
Discover how 2.5D and 3D multi-die designs transform high-performance computing and AI. This webinar explores key challenges of monitoring, embedded test and repair for multi-die designs, including essential pre-stack and post-stack manufacturing flows, in-field health monitoring, and the role of the 3Dblox language (under IEEE P3537 Standardization) in enabling EDA tool interoperability. Learn about practical Silicon Lifecycle Management solutions that optimize quality, yield, reliability and manufacturing cost across advanced packaging configurations.
What You Will Learn:

Silicon proof points for monitoring, test, and repair across advanced packaging configurations
Key embedded test & repair flows for multi-die designs
In-silicon health monitoring solutions for silicon lifecycle management
Practical test cost minimization strategies for multi-die solutions

Featured Speakers

Dr. Yervant Zorian
Chief Architect, Synopsys
Dr. Yervant Zorian is a chief architect and fellow at Synopsys, as well as president of Synopsys Armenia. Yervant holds 35 U.S. patents, has authored four books, published over 350 refereed papers, and received numerous best paper awards. He received an M.S. degree in Computer Engineering from the University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from the Wharton School of Business, University of Pennsylvania.

Dr. Sandeep K Goel
Senior Director, TSMC
Dr. Sandeep K Goel is an academician and senior director at Taiwan Semiconductor Manufacturing Company (TSMC), USA. He previously held research and management roles at LSI, Magma Design Automation, and Philips Research. Dr. Goel earned his M.Tech. in VLSI from IIT Delhi in 1999 and his Ph.D. in Electrical and Computer Engineering from the University of Twente in 2005. He has co-authored multiple book chapters, published over 90 conference/journal papers, and holds more than 100 US patents. He received the Most Significant Paper Award at ITC in 2010 and the Distinguished Contributor Award from the IEEE Computer Society in 2022. He is the chair of IEEE Std. P3537 standard for 3Dblox: Chiplet connectivity and physical properties description language. His research focuses on design verification, testing, diagnosis, and defect modeling of 2D/3D SOCs.

REGISTER HERE

Webinar: From C++ to Silicon: Fast, Physically Aware, AI-Driven Exploration with Rise Design Automation and Precision Innovations
2026-02-03 09:00 - 10:00 | Virtual
As hardware designs grow more complex, architectural exploration is increasingly critical to delivering differentiated silicon. Teams frequently develop promising architectures only to discover late in the cycle that physical implementation is too costly or fails to meet key specifications. This challenge intensifies as designers integrate new accelerators — video, audio, ML, or custom datapaths — rapidly expanding the search space.
AI-based automation can help, but only when each exploration trial provides cost metrics (area, timing, power) that are both fast and credible. Traditional parameter sweeps are slow. Full physical analysis is expensive. And without correlation to real implementation costs, AI-guided exploration can simply produce the wrong answers faster.
Rise Design Automation and Precision Innovations are partnering to change this dynamic. Together, they deliver fast, accurate, physically aware exploration loops — ideal for reinforcement learning, iterative refinement, and high-volume experimentation.
Rise Design Automation provides 10× faster High-Level Synthesis (HLS) with timing and area correlation within a few percent of downstream RTL-synthesis results. The Rise toolchain can also execute downstream tools “under the hood” and incorporate their feedback directly into HLS. Integrating Precision Innovations’ industry ready OpenROAD-based RTL→GDSII flow and OpenROAD Flow Scripts adds production-grade physical estimation with strong area and timing accuracy validated down to advanced nodes (including 2–3nm).
Combined, this integrated flow enables rapid exploration from high-level C++/SystemC/SystemVerilog through synthesized RTL to physically correlated PPA — supporting hundreds or thousands of trials without licensing barriers.
This session demonstrates how an integrated, AI-driven architectural exploration solution from Rise Design Automation and Precision Innovations provides rapid, actionable feedback to guide design decisions, and how you benefit from these capabilities in your own design flow.

What You’ll Learn

In this technical deep dive, you’ll see how Rise Design Automation and Precision Innovations help you:

Run AI-guided architectural exploration with fast, physically grounded cost metrics
Model and explore designs in C++, SystemC, or SystemVerilog and automatically generate multiple RTL variants
Use Rise’s fast, correlated HLS engine to accelerate exploration with credible RTL-level PPA
Leverage Precision’s OpenROAD-based RTL→GDSII flow for production-grade physical estimation — enabling early visibility into area, timing, and implementation feasibility
Apply reinforcement learning and design agents to guide the search toward optimal architectures
Scale exploration across hundreds or thousands of trials without restrictive per-run licensing

This webinar highlights practical techniques to accelerate exploration, increase confidence, and improve architectural decisions earlier in the design process.

Live Demonstration

See a complete exploration loop from high-level behavioral model through Rise Design Automation’s HLS, through RTL synthesis, and into Precision Innovations’ OpenROAD-based physical estimator — with AI-guided refinement driven by real PPA feedback

Who Should Attend:

Hardware architects, design engineers, verification leads, and research teams who want to:

Accelerate architectural exploration for complex accelerators
Apply AI/ML or reinforcement-learning workflows to silicon design
Improve correlation between high-level design, RTL, and physical estimates
Confidently explore many architectural options without slow iteration loops
Shift verification and physical awareness earlier in the flow
Deploy scalable exploration without restrictive per-run licensing

Whether you’re adding a new accelerator to an SoC or exploring ML-driven design automation, this session provides a practical foundation for leveraging Rise + Precision.
REGISTER HERE

Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
2026-01-28 10:00 - 11:00 | Online
In this webinar, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks.
We will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout.
We will show you how these tools work on real designs as well.
WHO SHOULD ATTEND THIS WEBINAR?
If you are designing chips to deploy in networked environments, you need to understand the risks ahead and how to minimize them.
If you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions.
SPEAKERS
Beau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies
Dr. Paul Calzada will take you through a live demonstration of CODAx, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions.
* This webinar is in partnership with SemiWiki and Caspia Technologies
REGISTER HERE

Power Seminar - Burnaby
2026-01-28 09:00 - 17:00 | Burnaby, BC, Burnaby, British Columbia, Canada
About this event
As power levels rise and systems scale, high-power testing becomes more complex and time-consuming. This hands-on Power Solutions Seminar focuses on practical test strategies for batteries, fuel cells, green energy, and power conversion.
You will experience expert-led technical sessions with hands-on, real-world application insights. Explore Keysight’s three new High-Power ATE System Supplies and demos across our power portfolio to improve test efficiency, accuracy, and development speed.

Who should attend this event?
This event is designed for development engineers in power electronics, battery systems, and green energy.

REGISTER HERE

Webinar: Powering the Future: Megawatt Charging Solutions for Heavy-Duty Electrification
2026-01-28 | Virtual
About this event
Join our upcoming webinar to discover how Keysight is powering the future of heavy-duty electric transportation with advanced megawatt-charging test solutions.
Learn how to validate ultra-high-power delivery beyond 3 MW, ensure compliance with MCS and ISO 15118-20, and streamline interoperability testing, all within a single, fully controllable platform designed for both compliance and development debugging.
We’ll explore how seamless integration of software, hardware, and project services accelerates the deployment of safe, scalable, and standards-driven charging infrastructure for trucks, ships, and heavy machinery.

Who should attend this event?
Those involved in the shift towards a future-proven transportation, logistics, and construction ecosystem. Specific titles: OEM Electrification Leaders; EVSE Manufacturers & Charging Infrastructure Developers; Compliance & Standards Specialists; Fleet Electrification Managers: Grid Integration & Energy Management Specialists.

REGISTER HERE

Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)
2026-01-27 09:00 - 10:00 | Online
Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process.
What you will learn

The breadth of the entire Gencellicon portfolio
How timing closure solutions can alleviate your design process using Siemens tools

Who should attend

Implementation engineers
SoC architects
Design Verification teams
Test engineers
Power architects
Physical designers

Speaker:

Himanshu Bhatnagar
Senior Director, Siemens EDA

Himanshu brings over 20 years of expertise in chip design, having developed complex SoCs across networking, communications, imaging, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis, a practical guide to synthesis and static timing analysis. Before founding Excellicon, now Gencellicon, Himanshu held key positions at leading semiconductor companies, including Mindspeed Technologies, Conexant Systems, and ST Microelectronics. At Conexant Systems, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally, Himanshu has served as an advisor to various EDA companies.

REGISTER HERE

Semiconductor Traceability and Provenance Workshop
2026-01-27 08:30 - 17:00 | NIST’s National Cybersecurity Center of Excellence (NCCoE), 9700 Great Seneca Highway, Rockville, MD, 20850, United States
The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday, January 27, 2026, at the NIST National Cybersecurity Center of Excellence (NCCoE) conference facility, in Rockville, Maryland. This in-person, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain, which identified traceability as the top priority of semiconductor industry stakeholders.
As semiconductor devices grow more complex and globally distributed, the risks from counterfeit components, malicious tampering, and opaque sourcing threaten the security, reliability, and resilience of critical systems. Strengthening traceability and provenance is essential to mitigating supply chain threats, supporting national security imperatives, and addressing the grand challenges in secure microelectronics (https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000.pdf).
The workshop will convene technical leaders across the semiconductor ecosystem (e.g., hyperscalers, auto and semiconductor companies, federal agencies, academia) to address the practical challenges and opportunities for implementing traceability in semiconductor chips. This one-day event will feature plenary, panel, and interactive breakout sessions. Participants will be encouraged to collaborate and discuss key questions and topics that will identify short-term (<1 year) and longer-term (2028-2029 time frame) activities related to semiconductor traceability and provenance. The topics that will be considered include but are not limited to:

Existing solutions
Technical, operational challenges to traceability adoption
Opportunities for public-private collaboration (e.g., hyperscalers, automobile,
semiconductor companies, government agencies, academia)
Roadblocks to alignment and paths to overcoming them
Economic drivers and pilot use cases for traceability
Frameworks for joint standards development and implementation
Roadmap for collaboration and path to success

Outcomes from the workshop will include a published roadmap and post-workshop report that advances shared goals in securing semiconductor supply chains.
Registration Info
The registration fee for this event is $97.00 and includes AM/PM breaks and lunch.
Registration closes on Tuesday, January 20, 2026.
Registration Contact for Additional Information or Questions:
Carol L. Shibley
carol.shibley@nist.gov
(301) 975-8302
TECHNICAL CONTACT:
Kostas Amberiadis
kostas.amberiadis@nist.gov
REGISTER HERE

SpaceTech Symposium – Austin
2026-01-22 09:30 - 16:00 | Capital Factory, Capital Factory, 701 Brazos St., Austin, TX, 78701, United States
Satellite communications and design present complex challenges — from phased arrays to 5G non-terrestrial networks (NTNs). Are you equipped with the latest solutions to ensure mission success?
Join Keysight and CesiumAstro’s Vice President of Engineering, James Carwell, at our action-packed SpaceTech Symposium to learn practical insights and engage in demos to help you navigate these challenges.
Walk away with:

Expert tips on satellite link evaluation and testing.
Insights into 3GPP adoption and critical R&D work paving the way for NTN and 6G.
Proven methods to ensure network security in your satellite system.
Best practices for phased array system design and validation.

Plus, enjoy a complimentary lunch while networking with industry and education professionals in the satellite and wireless space.
Who should attend this event?
Engineers, developers, and leaders ready to accelerate design cycles, strengthen system performance, and stay ahead of emerging space-communication standards.
REGISTER HERE

Optical Design Engineering User Conference
2026-01-22 08:30 - 17:00 | San Francisco, CA, San Francisco, CA, United States
About this event
Stay connected with the latest optical design product innovations across CODE V, LightTools, RSoft, ImSym, and our optical scattering measurement solutions. Get tips and tricks on design best practices from our experts, and network with industry peers and the Keysight Optical Design Engineering team. The user conference is held in parallel with Photonics West, making it an ideal opportunity to deepen your expertise while connecting with the broader photonics community.

Who should attend this event?
Optical engineers using CODE V, LightTools, RSoft, ImSym, and our optical scattering measurement solutions.

REGISTER HERE

IEEE Hybrid Bonding Symposium
2026-01-22 - 2026-01-23 | SEMI HQ, SEMI HQ, 673 S Milpitas Blvd., Milpitas, CA, 95035, United States
January 22-23, 2026, hosted by SEMI International, Silicon Valley, CA USA
Note: HBS’26 is a hybrid event, with both in-person and virtual participation via WebEx.
Download the Call for Presentations!
Hybrid Bonding has emerged as the technology of choice in the semiconductor and heterogeneous integration industries for ultra-fine-pitch interconnection. With significant benefits for interconnect density and device performance, it will become widely adopted for a broad range of high-performance semiconductor devices in the years to come. The success of Hybrid Bonding technology for high-volume manufacturing depends critically on the process technology as well as materials and equipment. Design, performance characterization, thermal management and reliability are also important considerations to enable applications in various areas.
Review the HBS’25 Program, and watch videos of most of the presentations.
Post-Symposium Report on the 2025 Hybrid Bonding Symposium
REGISTER HERE

Webinar: Turning Compliance Into Competitive Credibility: Exclusive Launch of New CMMC Readiness Research
2026-01-21 | Virtual
About this event
Be the first to see brand new, Keysight-commissioned research on Cybersecurity Maturity Model Certification (CMMC) readiness across the U.S. Defense Industrial Base. In this live webinar, we’ll unveil findings from hundreds of security, IT, and compliance leaders and show where organizations really stand.
Plus, attendees will be the first to get the full research paper, The Power of Proof: Turning CMMC Compliance into Competitive Credibility.

Who should attend this event?
Designed for professionals in governance, risk, compliance, security validation, and program management, this webinar offers actionable intelligence for any organization preparing for CMMC certification.

REGISTER HERE

POWERGEN 2026
2026-01-20 - 2026-01-22 | Henry B. González Convention Center, 900 E Market St, San Antonio, TX, 78205, United States
Unprecedented Demand. Unmatched Opportunity.

A surge in data centers, industrial expansion, and electrification is reshaping power generation planning across North America. Utilities are under mounting pressure to maintain reliability and add new capacity. IPPs are accelerating project development to capture opportunity. EPCs and OEMs are finding innovative ways to build faster, smarter, and stronger amid supply chain and permitting headwinds.
At POWERGEN 2026, we’re focusing on what it takes to deliver real megawatts and how collaboration across the generation ecosystem can meet the moment.
Who should attend this event?
Those involved in building, operating and maintaining reliable megawatts during a period of rapid load growth including Utilities, Grid & Energy Technology Providers / Solution Providers, Independent Power Producers (IPPs) / Generators / Developers, Original Equipment Manufacturers (OEMs).

REGISTER HERE

SPIE Photonics West 2026
2026-01-17 - 2026-01-22 | San Francisco, CA, San Francisco, CA, United States
Share your work, insights, and breakthroughs. The 2026 call for papers is open.
SPIE Photonics West is the world’s largest optics and photonics technologies event. Present your research in biomedical optics, biophotonics, industrial lasers, optoelectronics, microfabrication, displays, quantum, and emerging vision technologies.
Conferences and Courses: 17–22 January
This is the place to be in January
Experience the benefits of attending SPIE Photonics West—networking with colleagues, learning the latest research, and experiencing the newest innovations make this the most exciting week in photonics. See for yourself.
Plan to take a course from an expert
Course offerings will give you the technical training you need to excel in your field. Choose from more than 55 courses in San Francisco during SPIE Photonics West. Adding a course to your registration adds to your entire event experience.
Five major exhibitions
Explore the companies that exhibit at the SPIE Photonics West Exhibition, BiOS Expo, AR | VR | MR Expo, and Quantum West Expo. These leading companies are providing new capabilities and innovative products to help move your projects forward. Plus, new this year, Vision Tech Expo is growing.
REGISTER HERE

Webinar: ASU-Silvaco Device TCAD Workshop: From Fundamentals to Applications
2026-01-16 09:30 - 17:30 | ASU Tempe Campus, ASU Tempe Campus, Old Main Building, 400 East Tyler Mall, Second Floor, Tempe, AZ, 85287, United States
This workshop is a fast-paced, one-day program led by Prof. Dragica Vasileska and Prof. Stephen M. Goodnick. Spend the morning grounding yourself in semiconductor physics and transport, then transition in the afternoon to instructor-led, hands-on Silvaco TCAD labs (e.g., MOS Capacitors, MOSFETs, SOI Devices, FinFETs).
The workshop is offered in a hybrid format. Participants have the option to join either in person at ASU or virtually via Zoom.
Attendees will learn to use Silvaco TCAD effectively and know how to select the appropriate physical models and material parameters for their devices. Whether you are an industry professional or student, you will leave with a practical grasp of semiconductor physics and the skills to use Silvaco TCAD effectively and efficiently. Complimentary lunch will be served, followed by a Silvaco overview and Digital Twin session from Silvaco’s VP of Worldwide Field Applications Engineering, Garrett Schlenvogt.
When: January 16, 2026
Time: 9:30am-5:30pm
Where: ASU Tempe Campus
Old Main Building
400 East Tyler Mall
Second Floor
Tempe, AZ, 85287
Seating is limited so register soon.
REGISTER HERE

Webinar: Accelerate IC Layout Parasitic Analysis with ParagonX
2026-01-15 10:00 - 12:00 | Online
We are pleased to offer two webinar sessions for your convenience. Please choose the time that best fits your schedule:
10:00AM – 12:00PM CET (session #1 for EMEA/APAC)
10:00AM – 12:00PM PST (session #2 for NA)
Featured Speakers:

Kopal Kulshreshtha, Principal Product Specialist, Synopsys
Rob Dohanyos, Principal Product Specialist, Synopsys

Introducing ParagonX, a powerful tool for intelligent analysis, debugging, simulation, and visualization of IC layout parasitics. It is perfect for root-cause analysis in top-level analog, custom digital, and mixed-signal designs.
Why You Should Attend:

Assess and quantify the effects of layout parasitics early in the design process.
Elevate your productivity with rapid iterations that guide layout optimizations.
Seamlessly integrate ParagonX into your analog and custom design workflow.

REGISTER HERE

Advanced Measurements Seminar - Calgary
2026-01-15 09:00 - 17:00 | Calgary, AB, Calgary, Alberta, Canada
About this event
Start the new year off right with fresh insights and sharp skills. Join Keysight experts in Calgary for an all-day Advanced Measurements Seminar and cocktail reception. This hands-on technical event features live demonstrations with the latest RF and high-speed digital technologies.
Gain practical, lab-ready insights to enhance accuracy, reduce uncertainty, and push your measurement capabilities further in 2026. Lunch and cocktails are on us.
Learn more and reserve your spot today!

Who should attend this event?
Ideal for RF and high-speed digital engineers looking to deepen their measurement expertise.

REGISTER HERE

Webinar: 5 Expectations for the Manufacturing Market in 2026
2026-01-14 11:00 - 12:00 | This course will be held Online
Discover the 5 Critical Manufacturing Market Trends Reshaping Semiconductors in 2026
AI-driven investments, sustainability, and advanced materials—what’s next for semiconductor manufacturing.
The semiconductor manufacturing industry is undergoing a transformative period as AI-driven investments accelerate, sustainability pressures mount, and foundries navigate capacity expansion amid weak consumer demand.
In this live TechInsights webinar, our manufacturing experts will highlight five critical developments shaping semiconductor fabrication and equipment markets in 2026, offering actionable insights for strategists, foundry operators, and equipment suppliers.
Key Topics You’ll Learn

TSMC’s 2nm Mass Production Leadership – Achieving 7% of total capacity by 2026 while foundry/logic CAPEX rises for the first time since 2022.
China’s Role in Equipment Sales – Export control uncertainties and slower recovery extending into 2027, with fabrication emissions projected to reach 200M metric tons CO₂e.
Inventory Optimization & AI Growth – Leveraging oversupply in consumer, industrial, and automotive segments to focus on AI-driven production.
Glass Substrates Challenge Traditional Materials – Superior flatness, signal integrity, and sub-2-micron via capabilities for AI accelerators and HBM applications.
Wafer Fab Equipment Growth Focus – Concentration in microlithography for cutting-edge AI chips, with subsystem suppliers benefiting from Asian capacity expansions.

REGISTER HERE

Webinar: Advances in ATPG: From Power and Timing Awareness to Intelligent Pattern Search with AI
2026-01-14 10:00 - 11:00 | Online
Date: Jan 14, 2026 | 10:00 AM PST

Featured Speakers:

Srikanth Venkat Raman, Product Management Director, Synopsys
Khader Abdel-Hafez, Scientist, Synopsys
Theo Toulas, R&D Principal Engineer, Synopsys
Bruce Xue, Staff Engineer, Synopsys

As System-on-Chip (SoC) designs become increasingly complex, meeting test quality and cost goals requires advances in automatic test pattern generation (ATPG). Synopsys TestMAX™ ATPG is Synopsys’ state-of-the-art pattern generation solution. In this Synopsys webinar, we will showcase the latest ATPG advancements, from power- and timing-aware capabilities to leveraging AI for reducing test costs. Discover how you can meet the power constraints of your SoC tests with power-efficient ATPG patterns. Learn how timing-aware ATPG can enhance test quality. We will also explore Synopsys TSO.ai™ (Test Space Optimization AI), the industry’s first autonomous AI application for semiconductor testing, designed to minimize test cost and time-to-market for today’s complex designs.
Why You Should Attend:

Discover best practices for limiting power consumption during shift and capture operations.
See practical demonstrations of how you manage test power at the top-level of your SoC through a top-level budget and partition-level budgets.
Learn how advanced fault models (slack-based transition, path delay, and hold-time) can improve the quality of your tests from a timing standpoint.
Gain insights from Synopsys experts on how TestMAX™ ATPG leverages tighter connection with PrimeTime® to better handle timing exceptions (SDC) during test generation. See how ATPG can handle Muti-cycle paths (MCPs).
Learn how TSO.ai automatically searches for an optimal solution in a large test search space to minimize pattern count and ATPG turn-around time reducing test costs dramatically.

REGISTER HERE

Webinar: Physics-Based Foundations for Power Supply Design
2026-01-14 08:00 - 09:00 | Virtual
Overview:

This webinar provides engineers with a science-driven framework for power supply design, rooted in the physics of electromagnetic energy flow. Inspired by Ralph Morrison’s pioneering approach, the session begins with core principles of energy behavior, then explores how current, fields, and waves interact inside real circuits.
Attendees will gain practical insight into:

How electromagnetic interactions shape power integrity
Why grounding, return paths, inductance, capacitance, and loop control are critical to reliable design
How to apply field-based thinking to achieve predictable, first-time success
How to apply field-based thinking to achieve predictable, first-time success

By the end of the session, participants will walk away with a clear, concise, and powerful engineering perspective—one that replaces “black magic” with confidence and clarity in designing robust power systems.

REGISTER HERE

Webinar: PQShield with Microchip’s PolarFire® SoC FPGAs: Securing the Future of Embedded Systems in the Post-Quantum Era
2026-01-13 09:00 - 10:00 | Online
As the quantum threat moves from theory to reality, attacks put all long-lifecycle designs at risk. In this early PQC era, simply implementing the new NIST algorithms isn’t enough. Implementations will evolve, and new physical attacks like side-channel analysis present a major threat to the security of these complex new algorithms.
The solution requires both crypto-agility and deep hardware security. This webinar showcases PQShield’s hardware/software co-design as a side-channel secure PQC solution for Microchip’s PolarFire ® Series of products.

Speaker:

Sebastien Riou
Fellow, Product Security Architecture, PQShield

Sebastien has 15+ years experience in the semiconductor industry, focusing on achieving “banking grade security” on resource constrained ICs such as smart cards and mobile secure elements. Formerly of Tiempo-Secure, he helped create the world first integrated secure element IP achieving CC EAL5+ certification. He is the author of a semi-finalist algorithm at the Lightweight Cryptography NIST Standardisation process. He holds Master degrees in Computer Science and Cognitive Science from INPG.

REGISTER HERE
