Webinar: Marvell: Accelerating Interposer Design with Early Signal Integrity Analysis
2026-04-28 09:00 - 10:00 (America/Los_Angeles) | Online
In this webinar, Marvell will present how its team accelerates passive interposer routing for advanced 2.5D/3.5D multi die designs by bringing early, physics based signal integrity feedback into each routing iteration. Rather than relying on repeated, compute intensive 3D FEM cycles during development, Marvell uses a Method of Moments (MoM) early SI check available within Synopsys 3DIC Compiler to evaluate routing with real parasitics and simulation data, fast enough to support rapid iteration and safer exploration of auto routing strategies. Marvell will also share practical correlation takeaways, where MoM tracks FEM strongly and where additional margin and correlation work may be needed ahead of final signoff.
What you’ll learn

Why traditional interposer SI signoff can become a major schedule bottleneck
How early SI analysis with MoM differs from FEM and where it fits best
How to use physics-based SI feedback during interposer routing iterations
When and how to correlate early SI results with FEM for confidence and margin
How early SI enables faster convergence and broader design space exploration

Featured Speakers

Nitin Navale
Senior Principal CAD Engineer, Marvell
Nitin Navale currently serves as 3DIC Methodology Lead at Marvell Semiconductor. He previously worked at AMD & Xilinx for nearly 20 years, where he contributed to CAD & Methodology across a wide range of disciplines spanning 3DIC, Signoff, RTL/Netlisting, and Physical Verification. Nitin earned his BS and MS in Electrical Engineering from the University of Illinois, Urbana-Champaign. Outside work, he is consumed by his devotion to gaming, strategy, and music.

Adish Mehta
Senior Staff Engineer, Marvell
Adish Mehta is a seasoned semiconductor professional specializing in EM/IR signoff, power integrity, and signal electromigration analysis for advanced SoC and multi-die designs. He has led the development of scalable, hierarchical, and in-context signoff methodologies that improve reliability and design efficiency across bleeding-edge technology nodes. Adish frequently collaborates with global design teams, foundries, and EDA vendors to drive innovation in power and reliability analysis, helping deliver robust, production-ready silicon across a variety of platforms.

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SEMIEXPO Heartland
2026-04-29 - 2026-04-30 | Detroit Marriott at the Renaissance Center, 400 Renaissance Dr W, Detroit, MI, 48243, United States
FOCUSED ON SMART MANUFACTURING & SMART MOBILITY

DRIVING SEMICONDUCTOR BUSINESS IN THE MIDWEST
Thank you for being part of the launch of SEMIEXPO Heartland—where Smart Manufacturing and Smart Mobility came together like never before! This groundbreaking event opened new opportunities for collaboration and growth, driving us toward the semiconductor industry’s $1T future.
With so much innovation concentrated in the Midwest, SEMIEXPO Heartland is just getting started. Stay tuned for our next chapter in Spring 2026—we’ll see you in Detroit, MI! Get ready for even more inspiration, insights, and connections at the intersection of two critical markets.
MAKE AN IMPACT AT THE INAUGURAL SEMIEXPO HEARTLAND
Plan Now to Exhibit or Sponsor. Contact—
Shane Poblete | +1 202-847-5983 | spoblete@semi.org

2025 Post Show Report

Analytics & Statistics
Attendee Demographics
Keynotes
Program Highlights
And more!

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Webinar: Application-Specific Processors (ASIPs) for Physical AI
2026-04-29 07:00 - 08:00 | Online
Physical AI is increasingly popular in applications requiring real-time decision making and autonomous operation. Different from NPUs for cloud platforms, Physical AI processors can be made application-specific. By jointly tuning their ISA and memory architecture to the network models required by the application, power consumption and silicon area are drastically reduced.
Synopsys ASIP Designer is the industry-leading tool to explore, design, and optimize application-specific instruction-set processors (ASIPs), including custom NPUs for physical AI.
In this Synopsys webinar, we present the design of “SmarT”, an ASIP with a RISC-V ISA augmented with specialized vector units for convolutions and quantization, with 64 MACs. It supports circular gather/scatter addressing of vector data in parallel with computations. Low-overhead DMA moves data blocks from external to local memory.
Next, we present a multi-core RISC-V based accelerator for hyperdimensional computing, designed with ASIP Designer by TU Munich. It applies near-memory computing (NMC) to minimize power consumption and memory bandwidth. This 5-core chip is the first university-led tape-out in Germany using TSMC 7nm technology.
Learn about:

Synopsys ASIP Designer, the industry-leading tool to explore, design and optimize application specific processors
ASIP Design methodologies to address challenges in jointly optimizing the memory architecture and the computational resources for Physical AI architectures
Two ASIP designs examples with customize memory architectures for Physical AI applications

Featured Speaker

Dr. Falco Munsche
Technical Product Marketing, Synopsys
Falco Munsche is the Technical Product Manager for ASIP design tools at Synopsys. Previously he worked for a total of 20 years as Application Engineer and Software Engineer of ASIP design tools for Synopsys and CoWare, and as a Design Consultant for Synopsys.

Prof. Hussam Amrouch
Technical University of Munich, Germany
Hussam Amrouch is Professor heading the Chair of AI Processor Design within the Technical University of Munich (TUM). He is the head of Brain-inspired Computing at the Munich Institute of Robotics. Further, he is the head of the Semiconductor Test and Reliability at the University of Stuttgart. He is the Academic Director of TUM Venture Labs. He is Founding Director of the Munich Advanced-Technology Center for AI Chips (MACHT-AI).

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Webinar: Powering 3D Multi-Die Designs with RedHawk-SC Electrothermal
2026-04-30 09:00 - 10:00 | Online
As semiconductors continue to scale, designers are turning to 3DIC architectures to meet increasing demands for performance, energy efficiency, and functional density in data centers and edge AI applications. However, stacking multiple dies introduces new multiphysics challenges including electrical, structural, and thermal issues. Join this webinar to learn how RedHawk-SC Electrothermal enables designers to analyze the multiphysics behavior of chips all at once in complex multi-die designs.
Together, Synopsys and Ansys, part of Synopsys, provide engineers a comprehensive flow that offers in-design analysis along with final signoff, enabling faster and more confident development of next-generation multi-die designs.
Attend this webinar to:

Enhance your understanding of RedHawk-SC Electrothermal as a foundry-certified multiphysics integrity tool for multi-die designs
Learn about new features and flow capabilities for 2.5D/3D thermal and mechanical analysis, including GPU acceleration and ML-based solver
Integration of multiphysics simulation in Synopsys implementation and signoff solutions

Featured Speaker

Dr. Lang Lin
Product Management, Principal
Dr. Lang Lin, Product Management, Principal
Bio: Dr. Lang Lin is a technology leader at Synopsys Inc., where he directs product strategy for EDA solutions that ensure the multiphysics integrity, reliability, and security of advanced IC and multi die systems. With a Ph.D. in Electrical and Computer Engineering from the University of Massachusetts, his background spans low power design, multi-die design, and hardware security—areas that continue to influence his work at the intersection of multiphysics modeling and secure silicon design. Dr. Lin has co authored over 40 papers and patents, and his work has been recognized with top honors including IEEE HOST Best Paper Award, IEEE DAC Best Paper Award, and the Ansys CEO Innovation Award. He worked for Intel and Ansys before his product management role at Synopsys.
Profile: Lang Lin | Synopsys

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Display Week 2026
2026-05-03 - 2026-05-08 | Los Angeles Convention Center, 1201 S Figueroa St, Los Angeles, 90015
Where Innovation Meets Display.
Gain insights directly from the experts shaping the future of display technology. Explore next-generation innovations from over 200 leading manufacturers and emerging players. Engage with global engineers, developers, and decision-makers in discussions that are driving technical advancement and commercial impact.
Gain fresh perspectives, ingenious strategies, and the motivation to advance your work. The Display Week 2026 keynote lineup features forward-thinkers from top companies and major research institutes. Don’t miss the unique opportunity to hear about the future of display technology from the leaders who are shaping it.
REGISTER HERE

IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
2026-05-04 - 2026-05-07 | Washington DC, USA, Washington DC, DC, United States
The premier symposium that facilitates the rapid growth of hardware-based security research and development. Since 2008, HOST has served as the globally recognized event for researchers and practitioners to advance knowledge and technologies related to hardware security and assurance.
May 4 – 7 2026
Washington DC, USA

About the Conference

Rapid proliferation of computing and communication systems with increasing computational power and connectivity into every sphere of modern life has brought security to the forefront of system design, test, and validation processes. The emergence of new application spaces for these systems in the internet-of-things (IoT) regime is creating new attack surfaces as well as new requirements for secure and trusted system operation. Additionally, the design, manufacturing and the distribution of microchip, PCB, as well as other electronic components are becoming more sophisticated and globally distributed with a number of potential security vulnerabilities. Therefore, hardware plays an increasingly important and integral role in system security with many emerging system and application vulnerabilities and defense mechanisms relating to hardware. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) aims to facilitate the rapid growth of hardware-based security research and development. HOST highlights new results in the area of hardware and system security. Relevant research topics include techniques, tools, design/test methods, architectures, circuits, and applications of secure hardware.
Additional guidance for HOST reviewers on preprint, double-blind, multiple-submissions, and related IEEE policy can be found on the HOST Publication Policies page.
Contact Information
General Chairs
Saverio Fazzari, Email: Saverio.Fazzari.ctr@darpa.mil
Sandip Ray, Email: sandip@ece.ufl.edu
IEEE Open Conference Statement
Expanding participation in computing is central to the goals of the IEEE Computer Society and all of its conferences. The IEEE Computer Society is firmly committed to broad participation in all sponsored activities, including but not limited to, technical communities, steering committees, conference organizations, standards committees, and ad hoc committees that welcome the entire global community.
IEEE’s mission to foster technological innovation and excellence to benefit humanity requires the talents and perspectives of people with many disciplinary backgrounds.
All individuals are entitled to participate in any IEEE Computer Society activity free of discrimination and harassment.

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SEMICON Southeast Asia 2026
2026-05-05 - 2026-05-07 | MITEC (Malaysia International Trade and Exhibition Centre), Kompleks MITEC, 8, Jalan Dutamas 2, Kompleks Kerajaan, Kuala Lumpur, Wilayah Persekutuan, 50480, Malaysia
Expanding The Coverage of the Electronics Manufacturing Supply Chain!
SEMI Southeast Asia
SEMI Southeast Asia was established in 1993, the same year the SEMICON Singapore exhibition was established. The aim of the SEMI Southeast Asia office is to provide all of the SEMI International Services to the region in a timely manner. If you happen to be visiting or plan to set up operations in Southeast Asia, please contact us at the SEMI Southeast Asia office.
About SEMICON Southeast Asia
Expanding the Coverage of the Global Electronics Manufacturing Supply Chain!
While Southeast Asia is rising up fast as a world-class electronics manufacturing hub with end-to-end R&D capabilities – SEMICON Southeast Asia has become an important exposition for the electronics industry in Southeast Asia. The show connects the decision makers from the industry, demonstrates the most advanced products and brings in the most up-to-date market and technology trends. Bringing solutions to industry challenges that can best be addressed at the event!
REGISTER HERE

About SEMI

SEMI is the global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. SEMI members are responsible for the innovations in materials, design, equipment, software, devices, and services that enable smarter, faster, more powerful, and more affordable electronic products. Electronic System Design Alliance (ESD Alliance), FlexTech, the Fab Owners Alliance (FOA) and the MEMS & Sensors Industry Group (MSIG) are SEMI Strategic Association Partners, defined communities within SEMI focused on specific technologies. SEMI maintains offices in Beijing, Bengaluru, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.
SEMI Tradeshows Worldwide
Did you know that SEMI produces tradeshows in virtually every international semiconductor market? You can participate in China, Europe, Korea, Japan, Singapore, and Taiwan. See the SEMI Tradeshows Calendar.

Contact

152 Beach Road, #09-03/04
Gateway East
Singapore 189721
Tel: 65.6339.6361
Fax: 65.6339.6637
Email: semiconsea@semi.org

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TSMC 2026 Austin Technology Workshop
2026-05-05 08:30 - 17:30 | Austin Marriott Downtown, Austin Marriott Downtown, 304 E Cesar Chavez St, Austin, TX, 78701, United States
Join us to get the latest on:

TSMC’s industry-leading HPC, Smartphones, IoT, and Automotive platform solutions
TSMC’s advanced logic technology progress on 3nm, 2nm, A16, A14 processes and beyond
TSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®, InFO, CoWoS®, and TSMC-SoW™
TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more
TSMC’s manufacturing excellence, capacity expansion plans, and green manufacturing achievements
TSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design

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CadenceCONNECT: Tech Days Europe 2026 - Munich
2026-05-06 | Munich, Germany
Join us at CadenceCONNECT: Tech Days Europe 2026, our annual, free, multi-track event dedicated to the engineers, innovators, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows, boosting productivity, and enabling breakthroughs across every domain.
REGISTER HERE

Webinar: All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die
2026-05-06 08:00 - 09:00 | Online
Abstract

Dive into the future of Bluetooth audio with Ceva and Dolphin Semiconductor’s breakthrough 12nm Smart Edge AIoT SoC solution.
This webinar shows how advanced wireless connectivity, integrated AI processing, and premium audio technologies and power management come together to deliver superior performance, lower power, and faster time to market.
Learn how a combined Ceva and Dolphin Semiconductor’s solution turnkey platform enables low power and high performance next generation features: Bluetooth High Data Throughput, Channel Sounding, spatial audio, voice commands, sensor fusion, and more.
Ideal for cutting edge earbuds, headsets, smartwatches, and smart glasses.
Don’t miss this opportunity to enhance your next audio product with industry leading innovation.
What you will learn in this session:

Map and understand audio peripheral product challenges, particularly for TWS/OTC
Evaluate the pros and cons of existing design level solutions
Ceva’s and Dolphin Semiconductor’s solution for overcoming TWS/OTC device challenges

Target Audience
Chip architects & SoC designers, audio and DSP engineers, embedded software engineers, and product managers for hearables & wearables

Speakers

Franz Dugand
Sr. Director, Product Marketing, Ceva

Etienne Faucher
Product line Portfolio Manager – Audio, Dolphin Semiconductor

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Webinar: RedHawk-SC: From EMIR Signoff to IR-Aware Design Closure
2026-05-06 10:00 - 11:00 | Online
As power integrity challenges increase with advanced nodes and multi-die architectures, EMIR analysis must evolve beyond traditional signoff. In this Synopsys webinar, we will show how RedHawk-SC is expanding its capabilities not only to enhance EMIR analysis, but also to enable IR-aware Static Timing Analysis (IR-STA) and IR-driven ECO (IR-ECO) flows.
Join us to learn how tighter integration between power integrity and timing analysis, across both single-die and multi-die designs, helps engineers better understand IR-drop impact, accelerate debug, and achieve faster, more reliable design closure.
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Webinar: How Data Rates Doubled, and Where Validation Reaches Its Limit
2026-05-08 10:00 - 11:00 | Online
Data rates have doubled, but validation methods have not kept pace. As PCIe, DDR, and multi-terabit optical interconnects evolve, engineers are encountering signal integrity challenges much earlier in the design process.
Join Niels Fache, Senior Vice President and General Manager of Design Engineering Software at Keysight, to explore where validation becomes more challenging as speeds increase, and how engineering teams are adapting. You’ll learn how simulation, architecture modeling, and high-fidelity measurement help validate designs before silicon exists and reduce downstream risk.
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The 18th IEEE International Memory Workshop
2026-05-10 - 2026-05-13 | Leuven, Belgium, Leuven, Belgium
The 18th IEEE International Memory Workshop (IEEE IMW) will be held in 2026 in Leuven, Belgium. It is currently planned as an on-site event. This conference brings the memory community together in a workshop environment to discuss the memory process and design technologies, applications, market needs and strategies. It is sponsored by the IEEE Electron Devices Society and meets annually in May.
Although it is the 18th IMW meeting to be held next year, it has a long history of Non-Volatile Semiconductor Memory Workshops (NVSMW) dating back to 1976. In 2008, NVSMW and the International Conference on Memory Technology and Design (ICMTD) merged to incorporate both the volatile and non-volatile memory aspects in one forum while maintaining the workshop experience. And the scope was extended from non-volatile memory technology and design, which had been successfully discussed in more than 30 years of NVSMW, to the other memory technologies, which were the focus of ICMTD.
The IEEE IMW is the premier international forum for both new and seasoned technologists having diverse technical backgrounds to share and learn about the latest developments in memory technology with the global community. The scope of workshop content ranges from new memory concepts in early research to the technology drivers currently in volume production as well as emerging technologies in development. The morning and afternoon technical sessions are organized in a manner that provides ample time for informal exchanges amongst presenters and attendees. The evening panel discussions will address hot topics in the memory and memory system field. Papers are solicited in all aspects of semiconductor memory technology (Flash, DRAM, SRAM, PCRAM, RRAM, MRAM, FRAM, embedded memories, system, and emerging memories), including but are not limited to:

Device Physics & Modeling
Cell Design & Novel Materials
Memory Process & Integration
Circuit Design, Algorithms & Error Management
Quality & Reliability
System Architecture
New Concepts & Disruptive Technologies
Emerging Applications & Markets
SSD, Mobile & Automotive Applications
In-Memory & Neuromorphic Computing
Memory-enabled Artificial Intelligence

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Embedded Vision Summit 2026
2026-05-11 - 2026-05-13 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
The premier conference for innovators incorporating computer vision and AI in products
The 2025 Summit has now concluded. Join us May 11-13, 2026!

Attend an Immersive Experience

At the premier conference for innovators incorporating computer vision and AI into products

Join 1,400+ product and application developers, business leaders, investors and customers—all focused on perceptual AI at the edge.
Special features and Summit themes include:

80+ sessions on embedded vision and deep learning techniques, technologies, tools and opportunities, including formats like: presentations, case studies and panel discussions
Multiple expert sessions on deep learning for vision, 3D perception and low-power vision implementation and much more
Keynote presentations by industry luminaries
Four tracks tailored for engineers and business executives, newcomers and experts
Practical sessions to help you create visually intelligent products and gain know-how about computer vision
Edge AI Deep Dive Day filled with in-depth learning from top technology suppliers
An intensive three-hour training session designed to introduce the latest techniques in vision-language models (VLMs) and their integration with traditional computer vision methods
Case studies from leading innovators
Learn from fast-paced panel discussions presenting an array of viewpoints
Ability to see technology in action with live demos of the latest enabling technologies and dig deep into the practical applications and techniques of computer vision and AI

REGISTER HERE

ASMC 2026
2026-05-11 - 2026-05-14 | Hilton Albany, 40 Lodge St, Albany, NY, 12207, United States
ASMC brings together manufacturers, equipment and materials suppliers, and academia to solve manufacturing challenges with innovative strategies and methodologies.

View the 2025 Agenda

Advancing Semiconductor Manufacturing Excellence
ASMC is the leading international technical conference for discussing solutions that improve the collective manufacturing expertise of the semiconductor industry. Solving the challenges presented by semiconductor manufacturing is a combined effort by device makers, equipment and materials suppliers, and academics. ASMC provides an unparalleled platform for semiconductor professionals to network and learn the latest in the practical application of advanced manufacturing strategies and methodologies. Technical presentations at ASMC highlight industry innovations with specific results and select ASMC manuscripts are published in the ASMC Special Section of IEEE Transactions on Semiconductor Manufacturing.
The ASMC Committee is composed of industry professionals representing the microelectronics supply chain. All papers presented at the conference are peer-reviewed by the ASMC Technical Committee.
WHO SHOULD ATTEND

Academia
Chief Technology Officers
Fab Managers
Equipment Manufacturers
IC Manufacturers
Materials Suppliers
Operations Managers
Process Engineers
Product Managers
Technical Experts

REGISTER HERE

User2User Europe 2026
2026-05-12 | Munich, Germany
Join us in Munich where peer-delivered technical sessions were be shared across a breadth of topics so you can explore new concepts or dive deep in your core area of expertise with fellow like-minded professionals.
Speaker submissions now open!
About User2User
The User2User conference is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens electronic design automation (EDA) tools.
What to expect?
The Siemens User2User conference provides a dedicated environment for exchanging ideas, information and best practices that enable you to lead in your role and achieve success with your customers.

Technical agenda concentrated on the digital future
Industry leaders exploring macro trends and innovation
Super users sharing business challenges and roadblocks
Case studies demonstrating business results
Networking with like-minded peers in EDA

REGISTER HERE

CadenceCONNECT: Tech Days Europe 2026 - Edinburgh
2026-05-12 | Edinburgh, Scotland, Edinburgh, Scotland, United Kingdom
Join us at CadenceCONNECT: Tech Days Europe 2026, our annual, free, multi-track event dedicated to the engineers, innovators, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows, boosting productivity, and enabling breakthroughs across every domain.
Event Details

06 May 2026 – 30 Jun 2026
Various
REGISTER HERE

ChipEx2026
2026-05-12 - 2026-05-13 | Tel Aviv, Israel, Tel Aviv, Israel
The major annual event of the Israeli semiconductor industry
ChipEx2026, the largest annual event of the Israeli semiconductor industry, will be held on May 12-13, 2026 in Tel Aviv, Israel. ChipEx2026 showcases companies including manufacturers, developers and suppliers of advanced hardware technologies & services. It also includes a technical seminar where the world’s leading experts address the industry’s most relevant issues.
The event is produced by ASG Ltd. in cooperation with SIA, Semiconductor Industry Association and with Semi, the largest global industry association.
The goal of ChipEx2026 is to update all professionals involved with the Israeli semiconductor industry with the latest technological innovations and future directions of the industry.
ChipEx2026 target audience are all people involved with the semiconductor industry including engineers, R&D managers, industry experts, senior executives in microelectronics related companies, multinational design centers, consultants, venture capital managers as well as electrical/electronic/computer science students & professors from the various universities around Israel.
ChipEx2026 consists of three main parts:
Vendors’ Exhibition
The ChipEx exhibition includes booths in various sizes for presentations and demonstrations of new design and development tools. This year, the ChipEx2026 exhibition will take place on May 12, 2026 at the Tel-Aviv Expo Center and will include industry vendors, service providers, and manufacturers of electronic design tools, components and manufacturing equipment from Israel and around the globe. These exhibitors will exhibit and update the visitors with the latest developments in tools and services for the semiconductor industry.
Technical Seminar
Technical lectures given by industry experts, senior executives from the semiconductor industry, vendors, and university professors. The format of the sessions intends to cultivate and promote an instructive and productive interchange of ideas and solutions among industry developers and designers. The lectures are divided to various tracks in separate halls and address the major topics related to the microelectronics industry. This year, the ChipEx2026 technical seminar will take place on May 12, 2026 at the Tel-Aviv Expo Center.
ChipEx2026 Executive Summit
The Clossing session of ChipEx2026 will take place on May 13, 2026 at Peres Center for Peace and Innovation and will include top industry figures and will act as the Executive summit of ChipEx2026 targeting Industry leaders and top executives from Israel and around the globe.
ChipEx2026 is a great opportunity for any industry vendor or service provider to meet its target audience as well as interact with the decision makers in the various Israeli semiconductor companies.
We invite you to take part in ChipEx2026 as an exhibitor, a speaker and/or as a sponsor.
For more details please contact us at:
Phone: +972-9-7454007
Fax: +972-9-7748858
info@chiportal.co.il
www.chipex.co.il
REGISTER HERE

Webinar: Intel: Enabling and Evaluating Intel EMIB-T Bridging Design with Synopsys Tools
2026-05-12 09:00 - 10:00 | This course will be held Online
In this webinar, Intel will present how EMIB-T (Embedded Multi-die Interconnect Bridge with TSVs) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share a production-oriented EMIB-T reference methodology built on Synopsys’ 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump and TSV planning, automated die‑to‑die routing for HBM and UCIe, and a unified exploration‑to-signoff data model help Intel manage system‑level co-design complexity while maintaining closure on timing, power, thermal, and SIPI. Intel will also discuss SIPI methodology using Synopsys Tools and EMIB-T’s ability to support dense, high-speed HBM interfaces.
What you’ll learn

How EMIB-T addresses key multi-die design challenges
Why early bump/TSV planning is critical for EMIB‑T success
How automated die-to‑die routing accelerates convergence
How a unified flow supports scalable timing, power, thermal, and SIPI signoff
How EMIB‑T enables high‑speed HBM integration with confidence

REGISTER HERE

RISC-V Now! by Andes Beijing
2026-05-12 13:00 - 17:00 | Park Plaza Beijing Science Park, Park Plaza Beijing Science Park, 25 Zhichun Rd, Beijing, Haidian District, China
RISC-V Now! by Andes is the conference focused on turning RISC-V standards into products that ship — where spec goes to scale.
It brings together customers, ecosystem partners, and teams evaluating RISC-V for silicon, software, and system integration to share real-world experience deploying RISC-V at commercial scale.
From AI and automotive to datacenter and IoT, RISC-V Now! goes beyond standards discussions to address the realities of execution: architecture decisions, software enablement, system integration, and business outcomes.
Whether you’re a silicon architect, software architect, or CXO, RISC-V Now! delivers practical insight, hard-earned lessons, and actionable perspective on building successful RISC-V products.

REGISTER HERE

DVCon China 2026
2026-05-13 08:00 - 17:00 | Shanghai Renaissance Pudong Hotel, Renaissance Shanghai Pudong, 719 Yingchun Rd,, Pudong, Shanghai, 201204, China
Hello everyone! Welcome to the 2026 DvCon China Conference! As the chair of this conference, l am truly honored to be here with all of you. lt’s exciting to gather together and discuss the latest trends and cutting-edge technologies in the field of design verification.
In recent years, we’ve seen tremendous growth in China’s chip development across various sectors, particularly in critical areas like CPUs, GPUs, artificial intelligence, automotive electronics, communications, and the Internet of Things (loT). lt’s inspiring to witness the rapid rise of domestic companies in these fields, which not only drives technological advancement but also enhances our overall market competitiveness.
About DVCon China
DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon China is similar to the successful DVCon United States conference held for over 20 years in the Silicon Valley.
In order to boost the interest, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in China, this highly technical conference is organized to invite industry experts to learn and share best practices on:
1. The application of system-level design and verification languages such as SystemC, SystemVerilog or e 2.The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL) 3.Verification methodologies based on the Universal Verification Methodology (UVM)
REGISTER HERE

CadenceCONNECT: Tech Days Europe 2026 - Bracknell
2026-05-14 | Bracknell, UK, Bracknell, United Kingdom

TSMC 2026 Boston Technology Workshop
2026-05-14 08:30 - 17:30 | Boston Marriott Burlington, Boston Marriott Burlington, One Burlington Mall Road, Burlington, MA, 01803, United States

TSMC 2026 Taiwan Technology Symposium
2026-05-14 09:00 - 16:30 | Sheraton Hsinchu Hotel, Sheraton Hsinchu Hotel, No. 265號, E Section 1, Guangming 6th Rd, Zhubei City, Hsinchu County, 302, Taiwan
Join us to get the latest on:

TSMC’s industry-leading HPC, Smartphones, IoT, and Automotive platform solutions
TSMC’s advanced logic technology progress on 3nm, 2nm, A16, A14 processes and beyond
TSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®, InFO, CoWoS®, and TSMC-SoW™
TSMC’s specialty technology breakthroughs on ultra-low power, RF, embedded memory, power management, sensor technologies, and more
TSMC’s manufacturing excellence, capacity expansion plans, and green manufacturing achievements
TSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design

For more information on the TSMC Technology Symposium, e-mail us at: symposium@tsmc.com.
We look forward to seeing you at the TSMC 2026 Technology Symposium!
REGISTER HERE

Webinar: How Frequency Ranges Expanded, and Why Measurement Fidelity Became Critical
2026-05-15 10:00 - 11:00 | Online
As systems move into higher frequencies and wider bandwidths, small measurement errors can lead to costly design decisions. Engineers working in wireless, radar, satellite, and optical domains must now validate signals that push existing tools to their limits.
Join Jun Chie, Vice President of Product Management at Keysight, to explore where measurement fidelity begins to break down, and how engineers are adapting. You’ll see how next-generation instrumentation helps improve signal accuracy, reduce uncertainty, and increase confidence in design decisions.
REGISTER HERE

VOICE 2026
2026-05-18 - 2026-05-20 | Scottsdale, Arizona, Scottsdale, AZ, United States
VOICE is a developer conference, created by test engineers for test engineers.

Each year, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements, express new ideas, share best practices and network with one another.

REGISTER HERE

Surface Preparation and Cleaning Conference (SPCC)
2026-05-18 - 2026-05-20 | Wild Horse Pass, Wild Horse Pass, 5040 Wild Horse Pass Blvd, Chandler, AZ, 85226, United States
Surface Preparation and Cleaning Conference (SPCC), formerly presented by Linx Consulting, brings together key business insights, IC manufacturers, equipment makers, materials and chemical providers, metrology experts, process technologists to address critical challenges, and innovations in surface preparation and cleaning.
Held at the Wild Horse Pass Resort in Chandler, Arizona, SPCC 2026 will feature technical sessions, poster presentations, and business-focused programming, creating a unique forum where technology and industry strategy converge.
REGISTER HERE

CadenceCONNECT: Tech Days Europe 2026 - Cambridge
2026-05-19 | Cambridge, UK, Cambridge, England, United Kingdom

Webinar: Intel: From Construction to Signoff: 3DIC Methodology for Disaggregated Designs
2026-05-19 09:00 - 10:00 | Online
Featured Speaker:

Victoria Kolesov, Principal Engineer, Intel

In this Synopsys webinar, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’ complete design implementation and signoff flows for static timing analysis signoff and 3D layout verification in both passive and active interposer designs. The session highlights how increasing accuracy requirements have shaped 3D construction practices, standards, and collateral, enabling consistent, correct‑by‑construction signoff across process nodes, TSVs, and complex die‑to‑die interconnects.
What you’ll learn:

How Intel approaches 3DIC construction for disaggregated designs
Key requirements for static timing and layout signoff in 3DIC flows
Differences between passive and active interposer signoff considerations
How accuracy requirements influence 3D construction methodologies
Best practices for achieving correct‑by‑construction 3DIC signoff

Featured Speaker

Victoria Kolesov
Principal Engineer, Intel
Victoria Kolesov joined Intel in 2001 and has held a variety of responsibilities including RTL development, design completion, and design automation. Her current focus is interconnect implementation and 3D design integration. Victoria obtained her MS in Computer Science from St.Petersburg Technical University, Russia.

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Webinar: How System Scale Expanded, and Why Network Traffic Validation Became Essential
2026-05-22 10:00 - 11:00 | Online
AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions, not just in isolated tests.
Join Ram Periakaruppan, vice president and general manager of network applications and security at Keysight, to learn how large-scale traffic emulation reveals congestion, latency issues, and performance limits. You’ll see how to validate AI infrastructure under real workloads and ensure it performs reliably at scale.
REGISTER HERE
