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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260617
DTEND;VALUE=DATE:20260620
DTSTAMP:20260619T063613
CREATED:20260107T105806Z
LAST-MODIFIED:20260107T105806Z
UID:365400-1781654400-1781913599@semiwiki.com
SUMMARY:3D & Systems Summit 2026
DESCRIPTION:Themed Heterogeneous Integration: Bolstering Europe’s Resilience the 3D & Systems Summit 2025 will primarily focus on exploring strategies for enhancing Europe’s semiconductor industry addressing topics as geopolitical dynamics\, market trends\, as well as the latest advancements in chiplet applications and hybrid bonding techniques. The Summit will feature an exclusive exhibition area\, showcasing industry leaders alongside innovative emerging companies. This Summit is a platform for gathering and exchange of knowledge and fostering of collaborations within the semiconductor sector. \nAttendees will have several opportunities for B2B matching\, including networking receptions\, coffee breaks\, lunches\, and a unique Networking Dinner Cruise along the beautiful Elbe River. \nREGISTER HERE
URL:https://semiwiki.com/event/3d-systems-summit-2026/
LOCATION:Hilton Dresden Hotel\, Hilton Dresden Hotel\, An der Frauenkirche 5 D\, Dresden\, 01067\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-025739.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260617T100000
DTEND;TZID=America/Los_Angeles:20260617T110000
DTSTAMP:20260619T063613
CREATED:20260528T212700Z
LAST-MODIFIED:20260528T212720Z
UID:369738-1781690400-1781694000@semiwiki.com
SUMMARY:Webinar: Americas Session | SOS for Visual Studio Code: Design Data Management for Digital Design Teams
DESCRIPTION:About this event\nThis webinar showcases how the Keysight Technologies SOS extension integrates design data management directly into Visual Studio Code\, helping digital design and verification teams streamline RTL and HDL workflows without leaving their coding environment. \n\n\n\n\n\n\nWho should attend this event?\nDigital design engineers writing RTL in SystemVerilog\, Verilog\, or VHDL who use VS Code as their primary editor\, Verification engineers building UVM environments\, constrained-random testbenches\, or formal property sets\, SoC integration and IP development teams managing shared blocks and hierarchical references across multiple projects\, CAD\, methodology\, and design infrastructure leads responsible for revision discipline\, reproducibility\, and audit traceability\, Engineering managers evaluating consolidation of design data management across digital\, analog\, and mixed-signal flows\, Current SOS users on the SOS command line or other clients who want a modern editor-native experience\, Teams currently relying on Git\, Perforce\, or ad hoc snapshot scripts for HDL projects who are evaluating purpose-built EDA design data management. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-americas-session-sos-for-visual-studio-code-design-data-management-for-digital-design-teams/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-28-142704.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260622
DTEND;VALUE=DATE:20260627
DTSTAMP:20260619T063613
CREATED:20251211T213919Z
LAST-MODIFIED:20251211T213919Z
UID:364634-1782086400-1782518399@semiwiki.com
SUMMARY:ISC 2026
DESCRIPTION:CONFERENCE & EXHIBITION\n\n\n\n\n\n\n\n\nHPC\, AI\, Quantum: Powering Innovation and Sustainability \n\n\n\n\nISC 2026 connects scientists\, engineers\, and technology leaders to explore the future of high performance computing. We will examine today’s breakthroughs in artificial intelligence\, high performance computing and quantum technologies\, as well as what lies ahead. \nAdditionally\, we are committed to sustainability by promoting energy-efficient and cost-effective computing\, while empowering the next-generation workforce to continue the community’s legacy of innovation. \nISC 2026 will bring together a mix of people from different backgrounds and areas of expertise to drive HPC. Whether you are just entering the field\, in a mid-level position\, a part of senior management\, or a student\, we welcome you to join our efforts to connect people and technologies. \n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/isc-2026/
LOCATION:Hamburg\, Germany\, Hamburg\, Germany
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260623
DTEND;VALUE=DATE:20260624
DTSTAMP:20260619T063613
CREATED:20260114T021718Z
LAST-MODIFIED:20260129T235644Z
UID:365702-1782172800-1782259199@semiwiki.com
SUMMARY:Verification Futures Conference 2026 UK
DESCRIPTION:Verification Futures UK 2026\, co-located with Semiconductors Futures 2026 organised by Tessolve and co-organised this year with Alpinum. The conference continues its strong tradition of delivering a unique blend of conference presentations\, exhibitions\, training\, and industry networking sessions focused on the challenges faced in hardware and software verification. The event remains an important forum for end-users to define their verification challenges and collaborate with engineers\, researchers\, and vendors to shape practical solutions. In 2026\, Verification Futures continues to strengthen its core emphasis on verification methodologies\, DV tools\, and engineering workflows\, including areas such as formal methods for complex SoCs\, CPU & RISC-V verification\, open-source and licence-free verification tools\, AI in design verification (AI in DV)\, verification planning and coverage\, and HW/SW co-verification. \nSemiconductors Futures 2026 brings together the semiconductor community\, covering AI/ML in IP & SoC design\, AI’s impact on EDA and workflows\, FPGA & mixed-signal\, with a focus on the automotive\, data centre\, and AI products. New tracks consider emerging technologies such as quantum computing\, photonics\, and chiplets\, as well as startups and investments. We expect 50+ engineering students to attend a separate session. \nCALL FOR PAPERS \nREGISTER HERE
URL:https://semiwiki.com/event/verification-futures-conference-2026-uk/
LOCATION:Hybrid: In-Person and Virtual Conference\, Reading\, United Kingdom
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260623
DTEND;VALUE=DATE:20260626
DTSTAMP:20260619T063613
CREATED:20260414T063431Z
LAST-MODIFIED:20260414T063431Z
UID:368412-1782172800-1782431999@semiwiki.com
SUMMARY:LID World Summit 2026
DESCRIPTION:CEA-Leti’s flagship event\n\n\n\n\nDiscover sustainable semiconductor breakthroughs to guide your roadmap from lab-to-market and to tomorrow’s AI factory at LID World Summit 2026. \nJoin industry leaders to discover groundbreaking innovation that will help meet technological goals for the healthcare\, automotive\, industrial\, defense\, and consumer-electronics sectors. Leave with confidence in the possible. \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/lid-world-summit-2026/
LOCATION:Grenoble\, France
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260624T010000
DTEND;TZID=America/Los_Angeles:20260624T020000
DTSTAMP:20260619T063613
CREATED:20260528T212844Z
LAST-MODIFIED:20260528T212844Z
UID:369741-1782262800-1782266400@semiwiki.com
SUMMARY:Webinar: Americas Session | End-to-End Co-Design for Ethernet: Bridging Photonics and Electronics with EOE Simulation
DESCRIPTION:About this event\nThis webinar shows how engineers can use a unified EOE simulation workflow in Keysight Advanced Design System (ADS) to co-design and validate high-speed Ethernet systems across both electronic and photonic domains for faster\, more accurate development. \n\n\n\n\n\n\nWho should attend this event?\nSignal integrity engineers working on high-speed Ethernet links\, Photonic design engineers developing optical transceivers and PICs\, System architects in data center and AI infrastructure\, Hardware design engineers involved in co-packaged optics (CPO) and pluggable modules\, R&D teams focused on next-generation interconnect technologies. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-americas-session-end-to-end-co-design-for-ethernet-bridging-photonics-and-electronics-with-eoe-simulation/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-28-142811.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260624T090000
DTEND;TZID=America/Los_Angeles:20260624T120000
DTSTAMP:20260619T063613
CREATED:20260518T213746Z
LAST-MODIFIED:20260518T213746Z
UID:369367-1782291600-1782302400@semiwiki.com
SUMMARY:Synopsys Virtual Prototyping Day
DESCRIPTION:Join us for our 6th Annual Virtual Prototyping Day and learn how you can “shift left” your development cycle with virtual prototypes. \nHighly complex SoC and muti-die designs are putting pressure on silicon and software development teams to meet time-to-market demands. Virtual prototypes are the answer to begin development earlier\, reduce costs\, collaborate across teams\, and get your design to market faster. \nThis popular series features customers and partners who will present how they solve their design challenges using virtual prototypes. \nThis is an on-line event where you can attend from the convenience of your office\, home\, or anywhere you happen to be! \nWe have 2 specialized tracks designed to cater to the diverse interests and needs of our community: \nTrack 1 – System Architecture Design & Exploration \nOptimize the efficiency and performance of complex systems by enabling early architecture design exploration and optimization. This approach helps in identifying potential issues and opportunities for improvement\, ultimately leading to reduced development costs and faster time-to-market. \nTrack 2 – Software Development & Test \nEnhance software development and testing with a virtual environment\, where developers can simulate and validate system behavior without the need for physical hardware. This accelerates the development process\, improves early detection of issues\, and reduces costs associated with hardware dependencies and testing infrastructure. \nREGISTER HERE
URL:https://semiwiki.com/event/synopsys-virtual-prototyping-day/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-18-143657.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260625T090000
DTEND;TZID=America/Los_Angeles:20260625T100000
DTSTAMP:20260619T063613
CREATED:20260602T201039Z
LAST-MODIFIED:20260604T000532Z
UID:369891-1782378000-1782381600@semiwiki.com
SUMMARY:Webinar: Intel: Pushing EMIB Forward Design Methodology Insights with Synopsys Tools - SemiWiki
DESCRIPTION:Date: Jun 25\, 2026 | 9:00 AM PST \n\n\nIn this webinar\, Intel will present how EMIB (Embedded Multi‑die Interconnect Bridge) enables compact\, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share an EMIB reference methodology built on Synopsys 3DIC Compiler platform that spans early planning through signoff. The webinar highlights how early bump planning\, automated die-to‑die routing for HBM and UCIe\, and a unified exploration‑to-signoff data model help Intel manage system‑level co-design complexity while maintaining closure on timing\, power\, thermal\, and SIPI. Intel will also discuss SIPI methodology using Synopsys Tools and EMIB’s ability to support dense\, high‑speed HBM interfaces. \nWhat you’ll learn \n\nHow EMIB addresses key multi-die design challenges\nWhy early bump planning is critical for EMIB success\nHow automated die-to-die routing accelerates convergence\nHow a unified flow supports scalable timing\, power\, thermal\, and SIPI signoff\nHow EMIB enables high-speed HBM integration with confidence\n\n\n\n\n\nFeatured Speaker\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nSadha Parasuraman \nDesign Methodology Architect and EDA Enablement Manager\, Intel\n \nSadha Parasuraman is an EDA Enablement Manager and Design Methodology Architect for advanced design and customer enablement at Intel Foundry. Sadha’s Extensive experience in design flows and methodology stacks across semiconductor technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-intel-pushing-emib-forward-design-methodology-insights-with-synopsys-tools/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/06/synopsys-intel-linkedin-update-1200x1200-v3.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260625T090000
DTEND;TZID=America/Los_Angeles:20260625T163000
DTSTAMP:20260619T063613
CREATED:20260429T075058Z
LAST-MODIFIED:20260429T075058Z
UID:368934-1782378000-1782405000@semiwiki.com
SUMMARY:TSMC 2026 China Technology Symposium
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nFor more information on the TSMC Technology Symposium\, e-mail us at: symposium@tsmc.com. \nWe look forward to seeing you at the TSMC 2026 Technology Symposium! \nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-2026-china-technology-symposium/
LOCATION:Shanghai International Convention Center (SHICC)\, No.2727\, Riverside Avenue\, Pudong\, Shanghai\, 200120\, China
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END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260625T100000
DTEND;TZID=America/Los_Angeles:20260625T110000
DTSTAMP:20260619T063613
CREATED:20260528T213005Z
LAST-MODIFIED:20260528T213005Z
UID:369744-1782381600-1782385200@semiwiki.com
SUMMARY:Webinar: How Manufacturing Complexity Increased\, and Why Validation Had to Evolve
DESCRIPTION:About this event\nEngineering at the Edge Webinar Series – Episode 4 \nAs semiconductor complexity increases and board designs become denser\, manufacturing teams face tighter tolerances\, reduced test access\, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional approaches struggle to address. \nJoin Jason Kary\, Senior Vice President and President of Keysight’s ElectronicIndustrial Solutions Group\, to explore how manufacturing validation is evolving. You’ll learn how wafer-level and in-circuit test strategies improve coverage\, detect defects earlier\, and enable consistent\, high-volume production at scale without compromising quality. \n\n\n\n\n\n\nWho should attend this event?\nSemiconductor and electronics manufacturing engineers should attend. This session fits teams focused on test coverage\, yield improvement\, and high-volume production validation. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-manufacturing-complexity-increased-and-why-validation-had-to-evolve-2/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-28-142402.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260627
DTEND;VALUE=DATE:20260628
DTSTAMP:20260619T063613
CREATED:20260414T062122Z
LAST-MODIFIED:20260414T062122Z
UID:368392-1782518400-1782604799@semiwiki.com
SUMMARY:Scaling DRAM Technology to Meet Future Demands: System Challenges and Opportunities
DESCRIPTION:Tutorial Abstract\nSince the invention of the 1T1C bit cell more than 50 years ago\, DRAMs have become the main memory of choice for processors in computing systems and consumer electronics devices. As new computing paradigms have been created\, including AI\, 3D graphics\, HPC\, cloud computing\, and smart phones\, specialized processors and DRAM memories have been developed that are optimized for these use cases. The same 1T1C DRAM bit cell is used in each of these applications\, but the internal architecture and interfaces of the DRAMs supporting these markets are optimized in different ways\, and the DRAMs are packaged differently (sometimes with additional buffer chips) to meet the needs of the system. \nAcross all markets\, there is a relentless demand for higher performance and better power efficiency\, as insufficient DRAM bandwidth can bottleneck application performance and interfaces to DRAMs can consume half of the SOC power. DRAMs are also being stressed by growing reliability concerns as they incorporate on-die ECC and mitigation for disturbance effects such as RowHammer and RowPress. As AI continues to grow across markets (HPC\, server\, client\, mobile\, etc.)\, the design of efficient\, performant and reliable memory systems is becoming increasingly critical. AI models are continuing to grow\, pushing the capacity and bandwidth requirements of DRAMs. Simply scaling with historical techniques will no longer achieve the required characteristics due to physical challenges\, limits of process scaling\, and system architecture constraints including thermals and power delivery. \nThis tutorial will describe DRAM architecture in detail\, highlighting the similarities and differences between different DRAM technologies and the unique tradeoffs and design choices made to meet system needs. We will also cover the key components that memory transactions travel thorough to get to DRAMs and back\, including memory controllers\, PHYs\, and where applicable\, modules and buffer chips. We will describe the architecture of these critical components and discuss how DRAM architecture choices impact their performance and power efficiency. Standard scaling techniques for DRAMs will be highlighted along with challenges that the industry is currently facing. Input from industry experts will show the pros and cons of DRAM architecture choices\, demonstrating the system impact and requirements for mainstream adoption. Future DRAM architectures will also be discussed. \nTopics that will be covered\nThe tutorial will focus on DRAM architecture\, specifically looking at design tradeoffs and subsequent impact to the overall system performance\, power\, cost and reliability. The tutorial will cover the following topics: \n\nBackground and History of DRAM markets. How they were historically defined\, what changed\, and the drivers of new technologies.\nDRAM array architecture\, internal data paths\, shared structures\, and interfaces.\nThe future of DRAM\, including 3D DRAM cells.\nMemory modules\, including DIMMs\, CAMMs\, MRDIMMs\, and CXL modules and their buffer chips.\nCapacity\, power\, reliability\, cost tradeoffs that motivate different DRAM architectures for different markets including computing\, mobile\, graphics\, and AI. This will include underlying core architecture\, packaging and system integration.\nPower and energy differences between DRAM technologies.\nNovel packaging techniques including stacking and 2.5D assembly.\nReliability\, Availability\, and Serviceability (RAS) techniques\, including on-die error correction\, system-level ECC\, redundancy and repair\, and RowHammer and RowPress mitigation.\nProcessing in memory that has been implemented in DRAM silicon.\nMemory controller architecture and design challenges with current and future DRAMs.\nPHY architectures and challenges with achieving higher data rates and power efficiencies.\nSystem performance considerations\, including latency under load and the impact of core timings and core architecture on performance.\nMemory system architecture considerations to achieve maximum performance\, highlighting the impact of DRAM core timing and architecture tradeoffs on the host controller design.\nIndustry adoption challenges facing new DRAM technologies and features.\nChallenges for the future.\n\nOrganizers and Affiliations\nSteven Woo is a Fellow and Distinguished Inventor at Rambus Inc.\, where he leads research in Rambus Labs on advanced memory systems for accelerators and computing infrastructure\, and manages a team of senior architects. Since joining Rambus\, Steve has worked in various roles leading architecture\, technology\, and performance analysis efforts\, and in marketing and product planning roles leading strategy and customer programs.  He has more than 30 years of experience working on advanced memory systems and holds more than 100 US and international patents. Steve received his PhD and MS degrees in Electrical Engineering from Stanford University\, and Master of Engineering and BS Engineering degrees from Harvey Mudd College. \nWendy Elsasser is a Technical Director of Research Science at Rambus Inc. She works in the Rambus Labs R&D division researching future system architecture and developing innovative solutions to address the challenges of the memory sub-system. She has over 25 years of experience in industry\, starting with semi-custom micro-controller design\, test\, and implementation. Over the last 20 years\, her focus has been on memory sub-systems\, primarily external DRAM. Her experience includes DRAM controller architecture\, design\, and validation as well as active contributions to consortiums and standards bodies. Specifically\, she was a leader in the Gen-Z consortium and JEDEC\, helping to define future memory interfaces and DRAM standards. Her work has resulted in 15 patents. \nRobert Palmer is a Senior Technical Director of Research Science at Rambus Inc.\, leading research in future memory module and memory buffer chip architectures. He has over 25 years of industry experience developing silicon IP and communication ICs\, spanning the design of high-speed wireline transceiver circuits\, serial link and memory controller PHY microarchitectures\, and DDR and CXL memory buffer chip architectures and microarchitectures. In addition to his tenure at Rambus\, Robert has held positions at Velio Communications and Nvidia Research. He holds over 60 US and international patents. \nTaeksang Song is a Corporate Vice President at Samsung Electronics where he is leading a team dedicated to pioneering cutting-edge technologies including CAMM\, MRDIMM\, CXL memory expanders\, fabric attached memory solutions and processing near memory to meet the evolving demands of next-generation data-centric AI architectures. He has 20 years of professional experience in memory and sub-system architecture\, interconnect protocols\, system-on-chip design and collaborating with CSPs to enable heterogeneous computing infrastructure. Prior to joining Samsung Electronics\, he worked at Rambus Inc.\, Micron Technology and SK hynix in lead architect roles for the emerging memory controllers and systems. Taeksang received his PhD from KAIST\, South Korea\, in 2006. He has authored and co-authored over 20 technical papers and holds over 50 U.S. patents. \nREGISTER HERE
URL:https://semiwiki.com/event/scaling-dram-technology-to-meet-future-demands-system-challenges-and-opportunities/
LOCATION:Raleigh\, North Carolina\, Raleigh\, NC\, United States
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260627
DTEND;VALUE=DATE:20260702
DTSTAMP:20260619T063613
CREATED:20260414T062249Z
LAST-MODIFIED:20260414T062249Z
UID:368397-1782518400-1782950399@semiwiki.com
SUMMARY:ISCA 2026
DESCRIPTION:The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. The conference specifically seeks particularly forward-looking and novel submissions. In 2026\, the 53rd edition of ISCA will be held in Raleigh at the Raleigh Convention Center from June 27 to July 1\, 2026. \nREGISTER HERE
URL:https://semiwiki.com/event/isca-2026/
LOCATION:Raleigh Convention Center\, Raleigh Convention Center\, 500 Fayetteville St\, Raleigh\, NC\, 27601\, United States
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260628
DTEND;VALUE=DATE:20260702
DTSTAMP:20260619T063613
CREATED:20260107T110056Z
LAST-MODIFIED:20260107T110056Z
UID:365403-1782604800-1782950399@semiwiki.com
SUMMARY:ALD/ALE 2026
DESCRIPTION:Overview\n\n\n\n\nThe AVS 26th International Conference on Atomic Layer Deposition (ALD 2026) featuring the 13th International Atomic Layer Etching Workshop (ALE 2026) will be a three-day meeting dedicated to the science and technology of atomic layer controlled deposition of thin films and atomic layer etching.  Since 2001\, the ALD conference has been held alternately in the United States\, Europe and Asia\, allowing fruitful exchange of ideas\, know-how and practices between scientists. The conference will take place Sunday\, June 28-Wednesday\, July 1\, 2026\, at the JW Marriott Water Street\, Tampa\, Florida. \nAs in past conferences\, the meeting will be preceded (Sunday\, June 28) by one day of tutorials and perspectives and a welcome reception. Sessions will take place (Monday-Wednesday\, June 29-July 1) along with an industry tradeshow. All presentations will be audio-recorded and provided to attendees following the conference (posters will be included as PDFs). Anticipated attendance is 700+. View List of Invited Speakers \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/ald-ale-2026/
LOCATION:JW Marriott Water Street\, JW Marriott Water Street\, 510 Water St\, Tampa\, FL\, 33602\, United States
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END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260629
DTEND;VALUE=DATE:20260702
DTSTAMP:20260619T063613
CREATED:20260211T220710Z
LAST-MODIFIED:20260211T220710Z
UID:366633-1782691200-1782950399@semiwiki.com
SUMMARY:Realize LIVE Europe 2026
DESCRIPTION:Join us in 2026\nWe are ready to deliver more \n1\,800+ attendees. Join our community of users\, industry experts and trusted partners. Realize LIVE offers something for everyone! \n350+ sessions. Explore breakout sessions\, technical tracks\, trainings and more. More than 60% of sessions were led by customers\, sharing real-world insights. \n90% overall satisfaction rate. Realize LIVE is your digital transformation destination! Join our community and walk away a better user. \n\n\n\n\nAccelerate your digital transformation journey\n\n\n\n\n\nLearned from experts and industry leaders\, built skills and discovered the latest trends and technology with more than 350+ sessions at Realize LIVE Europe. \n\n\n\n\n\n\nBecome a better user\nLeave empowered — 88% of attendees left Realize LIVE Europe 2025 with new skills and enhanced tool proficiency. \n\n\nGet inspired by thought leaders\nIn 2025 over 60% of sessions were led by customers\, sharing real-world insights and innovations. You can expect even more in 2026. \n\n\nStay ahead with product roadmaps\nAttendees will stay up-to-date with exclusive product presentations showcasing the latest advancements in Siemens technology\, and hear about functionality updates\, so you can plan for what comes next. \n\n\nGain exclusive hands-on training and certification\nAttendees receive complimentary hands-on training\, 60 days access to Siemens Xcelerator Academy and 20 lab hours. Plus\, the opportunity to earn your Siemens Xcelerator Certification (€1000 value). \n\n\nConnect and celebrate with product experts\nJoined dedicated portfolio meet-ups\, industry receptions and our Community Corner to connect with peers who are on their digital transformation journey. Don’t forget the evening events — a great chance to relax and network! \n\n\nDive into the Siemens ecosystem\nRealize LIVE Europe is your destination for all things digital transformation. Meet experts\, engage with partners and experience live demos in the Solutions Center. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/realize-live-europe-2026/
LOCATION:RAI Amsterdam Convention Centre\, Europaplein 24\, Amsterdam\, 1078 GZ\, Netherlands
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/Screenshot-2026-02-11-140637.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260629
DTEND;VALUE=DATE:20260703
DTSTAMP:20260619T063613
CREATED:20260107T110301Z
LAST-MODIFIED:20260107T110301Z
UID:365409-1782691200-1783036799@semiwiki.com
SUMMARY:SMACD 2026
DESCRIPTION:Welcome to SMACD 2026\nInternational Conference on Synthesis\, Modeling\, Analysis and Simulation Methods\, and Applications to Circuit Design \nREGISTER HERE
URL:https://semiwiki.com/event/smacd-2026/
LOCATION:Dresden\, Germany\, Dresden\, Germany
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/images-1.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260630
DTEND;VALUE=DATE:20260701
DTSTAMP:20260619T063613
CREATED:20260414T060533Z
LAST-MODIFIED:20260414T060533Z
UID:368379-1782777600-1782863999@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Leuven
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-leuven/
LOCATION:Leuven\, Belgium\, Leuven\, Belgium
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260630T090000
DTEND;TZID=America/Los_Angeles:20260630T100000
DTSTAMP:20260619T063613
CREATED:20260528T213232Z
LAST-MODIFIED:20260528T213232Z
UID:369746-1782810000-1782813600@semiwiki.com
SUMMARY:Webinar: See it Before You Build it with VisionSym
DESCRIPTION:About this event\nJoin our upcoming webinar to discover how VisionSym transforms CAD models into photorealistic images using LightTools or LucidShape—eliminating the need for physical prototypes. \nWith GPU-accelerated ray tracing and photometrically accurate simulations\, VisionSym enables both design verification and visual appearance evaluation in one streamlined workflow. \nIn this session\, you’ll learn how to: \n\nValidate designs against automotive regulations and OEM specs\nUse photorealistic simulations to improve efficiency and accuracy\n\n\n\n\n\n\n\n\nWho should attend this event?\nEngineers and managers seeking faster\, more integrated design workflows. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-see-it-before-you-build-it-with-visionsym/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-28-143151.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260630T090000
DTEND;TZID=America/Los_Angeles:20260630T100000
DTSTAMP:20260619T063613
CREATED:20260528T213352Z
LAST-MODIFIED:20260528T213352Z
UID:369749-1782810000-1782813600@semiwiki.com
SUMMARY:Webinar: ImSym – Imaging System Simulator Discovery Training
DESCRIPTION:About this event\nThis discovery training introduces ImSym – Imaging System Simulator\, an advanced platform for end-to-end imaging system simulation. \nImSym allows engineers to virtually prototype imaging systems by modeling the full image formation pipeline\, from scene and optics through the detector and image signal processing. This enables earlier insight into real-world image performance and supports more efficient design decisions. \nWhat You Will Learn: \n\nUnderstand what ImSym is and the imaging challenges it addresses\nIdentify key components of the imaging system pipeline\nGain a high-level view of the ImSym interface and workflow\nUnderstand the fundamentals of end-to-end image simulation\n\n\n\n\n\n\n\nWho should attend this event?\nThis training is ideal for: \n\nOptical and lens designers\nStray light engineers\nSystem engineers\nImaging and optical engineers\nEngineering managers evaluating imaging workflows\n\nNo prior ImSym experience required. A basic understanding of imaging systems or optics is recommended. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-imsym-imaging-system-simulator-discovery-training/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-28-143338.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260702
DTEND;VALUE=DATE:20260703
DTSTAMP:20260619T063613
CREATED:20260414T060635Z
LAST-MODIFIED:20260414T060635Z
UID:368381-1782950400-1783036799@semiwiki.com
SUMMARY:CadenceCONNECT: Tech Days Europe 2026 - Barcelona
DESCRIPTION:Join us at CadenceCONNECT: Tech Days Europe 2026\, our annual\, free\, multi-track event dedicated to the engineers\, innovators\, and visionaries shaping the future of electronic design. Our aim is to bring together like minded thinkers to explore how AI-driven Cadence technologies are transforming design workflows\, boosting productivity\, and enabling breakthroughs across every domain. \nREGISTER HERE
URL:https://semiwiki.com/event/cadenceconnect-tech-days-europe-2026-barcelona/
LOCATION:Barcelona\, Spain\, Barcelona\, Spain
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/04/Screenshot-2026-04-13-225642.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260703T100000
DTEND;TZID=America/Los_Angeles:20260703T180000
DTSTAMP:20260619T063613
CREATED:20260615T230513Z
LAST-MODIFIED:20260615T230513Z
UID:370310-1783072800-1783101600@semiwiki.com
SUMMARY:TSMC 2026 Japan Technology Symposium
DESCRIPTION:Join us to get the latest on:\n\nTSMC’s industry-leading HPC\, Smartphones\, IoT\, and Automotive platform solutions\nTSMC’s advanced logic technology progress on 3nm\, 2nm\, A16\, A14 processes and beyond\nTSMC 3DFabric® advanced silicon stacking and packaging technology advancement on TSMC-SoIC®\, InFO\, CoWoS®\, and TSMC-SoW™\nTSMC’s specialty technology breakthroughs on ultra-low power\, RF\, embedded memory\, power management\, sensor technologies\, and more\nTSMC’s manufacturing excellence\, capacity expansion plans\, and green manufacturing achievements\nTSMC’s Open Innovation Platform® Ecosystem to speed up time-to-design\n\nREGISTER HERE
URL:https://semiwiki.com/event/tsmc-2026-japan-technology-symposium/
LOCATION:PACIFICO Yokohama NORTH\, 1 Chome-1-2 Minatomirai\, Yokohama\, Kanagawa\, 220-0012\, Japan
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/Screenshot-2026-06-15-160419.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260715T080000
DTEND;TZID=America/Los_Angeles:20260715T170000
DTSTAMP:20260619T063613
CREATED:20260616T203422Z
LAST-MODIFIED:20260616T203422Z
UID:370355-1784102400-1784134800@semiwiki.com
SUMMARY:Advanced Packaging Summit 2026
DESCRIPTION:Advanced Packaging Summit 2026\, under the theme “Packaging the Future of AI – From Silicon to Photon\,” will examine the evolution of packaging technologies in the AI era and their broader implications for the semiconductor industry. Featuring presentations by leading industry experts\, the summit will explore market shifts driven by the growing demand for AI semiconductors\, along with key technologies enabling advanced packaging. The program will also highlight the innovation journey from silicon-based integration technologies to photonics-based interconnects\, which are essential to enhancing packaging productivity and scalability. Panel discussions in each session will further provide opportunities to exchange insights on real-world applications\, technical challenges\, and possibilities for cross-industry collaboration\, while exploring new business opportunities and strategic perspectives created by advanced packaging technologies in the AI era. \nREGISTER HERE
URL:https://semiwiki.com/event/advanced-packaging-summit-2026/
LOCATION:Suwon Convention Center\, Suwon Convention Center\, 140 Gwanggyojungang-ro\, Yeongtong-gu\, Suwon-si\, Gyeonggi-do\, Korea\, Republic of
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2026/06/APS_web-square_0.jpg.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260719
DTEND;VALUE=DATE:20260722
DTSTAMP:20260619T063613
CREATED:20260616T203728Z
LAST-MODIFIED:20260616T203728Z
UID:370358-1784419200-1784678399@semiwiki.com
SUMMARY:10th Edition — IEEE International Test Conference INDIA 2026
DESCRIPTION:International Test Conference is the world’s premier venue dedicated to the electronic test of devices\, boards and systems-covering the complete cycle from design verification\, design-for-test\, design-for-manufacturing\, silicon debug\, manufacturing test\, system test\, diagnosis\, reliability and failure analysis\, and back to process and design improvement. \nAt IEEE ITC India\, design\, test\, and yield professionals can confront challenges faced by the industry\, and learn how these challenges are being addressed by the combined efforts of academia\, design tool and equipment suppliers\, designers\, and test engineers. \nWho should attend?\n\nStudents\, researchers\, faculty\, and industry professionals in VLSI\, semiconductor testing\, and electronics are encouraged to attend. \nIt is ideal for anyone interested in chip design\, validation\, and emerging test technologies. \n\nIs the conference fully offline\, virtual\, or hybrid?\n\nIEEE ITC India 2026 is primarily an in-person (offline) conference to enable better networking and collaboration. \nSome sessions may be accessible in hybrid or virtual mode based on final arrangements. \n\n\n\nWhat are the key focus areas?\n\nThe conference covers VLSI testing\, DFT\, silicon debug\, reliability\, and hardware security. \nIt also includes emerging areas like AI in testing and next-gen technologies such as IoT and 5G/6G. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/10th-edition-ieee-international-test-conference-india-2026/
LOCATION:Radisson Blu Bengaluru\, Radisson Blu Bengaluru\, Bangalore\, India
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/Screenshot-2026-06-16-133626.png
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260721T090000
DTEND;TZID=America/Los_Angeles:20260721T170000
DTSTAMP:20260619T063613
CREATED:20260528T213539Z
LAST-MODIFIED:20260528T213539Z
UID:369752-1784624400-1784653200@semiwiki.com
SUMMARY:LucidShape User Group Meeting - North America
DESCRIPTION:About this event\nJoin us for our annual LucidShape User Group Meeting— This year’s meeting brings together the LucidShape community for a day of insights\, innovation\, and collaboration. Whether you’re focused on automotive lighting\, simulation workflows\, or advanced design techniques\, you’ll gain practical knowledge you can apply right away. \nWhat You’ll Experience \n\nLatest LucidShape Innovations\nDiscover new features and capabilities designed to enhance your optical design workflows.\nReal-World Applications\nExplore how LucidShape is used across lighting design applications—from concept to validation.\nTechnical Deep Dives\nLearn more about simulation methods\, modeling accuracy\, and performance optimization.\nNetworking Opportunities\nConnect with fellow users\, industry peers\, and the Keysight team.\n\n\n\n\n\n\n\nWho should attend this event?\nThis event is ideal for: \n\nOptical and lighting design engineers\nSimulation and modeling specialists\nAutomotive lighting professionals\nAnyone looking to deepen their expertise in LucidShape\n\nAttendance is free\, but space is limited. Secure your place today and join us in Novi for a valuable day of learning and connection. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/lucidshape-user-group-meeting-north-america/
LOCATION:Novi\, MI\, Novi\, MI\, Novi\, MI\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/05/Screenshot-2026-05-28-143457.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260726
DTEND;VALUE=DATE:20260730
DTSTAMP:20260619T063613
CREATED:20260107T110547Z
LAST-MODIFIED:20260107T110547Z
UID:365412-1785024000-1785369599@semiwiki.com
SUMMARY:DAC 2026
DESCRIPTION:The Long Beach Convention Center will serve as a dynamic venue for DAC 2026: The Chips to Systems Conference. Set along the scenic Southern California coastline\, the center offers modern meeting spaces and a vibrant setting that reflects the innovative spirit of DAC. Its central location in downtown Long Beach provides easy access to hotels\, dining\, and entertainment\, making it an ideal hub for bringing together industry leaders\, researchers\, and practitioners to explore the future of design automation from chips to systems. \n\nWhat is DAC?\n\nLeading worldwide event for design engineering professionals since 1963 \n\n\n\n\n\n\nDAC: The Chips to Systems Conference DAC is where the future of electronic design takes shape. Each year\, system architects\, chip designers\, engineers\, researchers\, and executives from 11\,000+ organizations worldwide come together to learn\, connect\, and innovate. With over 60 expert-selected technical sessions and 150 exhibitors showcasing the latest in AI automated tools\, EDA\, and IP\, DAC is the place to discover breakthrough ideas\, build lasting connections\, and stay at the forefront of the chip design industry. Don’t miss it. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/dac-2026/
LOCATION:Long Beach Convention & Entertainment Center\, 300 E Ocean Blvd\, Long Beach\, CA\, 90802\, United States
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2026/01/dac26-web-hero_09.29.25.webp
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260804
DTEND;VALUE=DATE:20260806
DTSTAMP:20260619T063613
CREATED:20260211T220912Z
LAST-MODIFIED:20260211T220912Z
UID:366636-1785801600-1785974399@semiwiki.com
SUMMARY:Realize LIVE Asia-Pacific 2026
DESCRIPTION:Where your digital transformation gets real — fast\nWe are excited to be visiting a new city with the Realize LIVE digital transformation conference to showcase artifial intelligence\, digitalization\, sustainability and optimization across the product lifecycle. Learn\, network and connect with the Siemens software community\, and walk away with new tools and insights for your digital journey. \nGet a sneak peek of what you can expect! \n\n\n\n\nAccelerate your digital transformation journey\n\n\n\n\n\n\n\nBecome a better user\nLeave empowered — 85% of Realize LIVE event attendees leave with new skills and enhanced tool proficiency. \n\n\nBecome inspired by thought leaders\nRealize LIVE participants become inspired after attending sessions led by customers and Siemens experts\, who share real-world insights and innovations\, leave event participants inspired. \n\n\nStay ahead with product roadmaps\nStay up-to-date with exclusive product presentations showcasing the latest advancements in Siemens technology\, and preview upcoming updates to plan for what’s next. \n\n\nGain exclusive access to training and certification\nGet 60 days of access to Siemens Xcelerator Academy\, as well as a voucher to Siemens Xcelerator Certification (valid for six months). \n\n\nConnect and celebrate with product experts\nJoin the Realize LIVE reception and dedicated meet-ups to connect with peers who are on their digital transformation journey. \n\n\nDive into the Siemens ecosystem\nRealize LIVE is your destination for all things related to digital transformation. Meet experts; engage with partners; and experience live demos in the solutions center. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/realize-live-asia-pacific-2026/
LOCATION:Bengaluru\, India\, Bengaluru\, India
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/02/Screenshot-2026-02-11-140843.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260804
DTEND;VALUE=DATE:20260807
DTSTAMP:20260619T063613
CREATED:20260616T204046Z
LAST-MODIFIED:20260616T204046Z
UID:370361-1785801600-1786060799@semiwiki.com
SUMMARY:Future of Memory and Storage (FMS) 2026: 20th Anniversary
DESCRIPTION:What is FMS?\nOur over-arching mission is to help accelerate the move towards a world where advanced memory and storage technologies enable AI systems\, data centers\, hyperscalers and enterprises to operate at unprecedented scale\, speed and efficiency. All the while supporting the engineers and architects building the infrastructure of the future. \nFUTURE OF MEMORY & STORAGE is a multi-faceted event experience providing the most comprehensive and technically credible memory and storage event on the planet. It is carefully curated by an experienced team plugged into a global network. \nOur presenters are visionary industry leaders\, engineers and architects from all disciplines. They are selected for their relevance\, dynamism and insight. \nREGISTER HERE
URL:https://semiwiki.com/event/future-of-memory-and-storage-fms-2026-20th-anniversary/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/Screenshot-2026-06-16-134008.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260812
DTEND;VALUE=DATE:20260813
DTSTAMP:20260619T063613
CREATED:20260616T204621Z
LAST-MODIFIED:20260616T204621Z
UID:370369-1786492800-1786579199@semiwiki.com
SUMMARY:CadenceLIVE India
DESCRIPTION:Join us on August 12 for CadenceLIVE India 2026\, where Cadence technology users connect with the engineers and industry leaders who develop the solutions and the industry experts who influence market trends. \nParticipants experience a day of learning\, connection\, and cutting-edge technology shaping the future of electronic design and intelligent systems. This premier event brings together the brightest minds for a day of inspiration and innovation. \nREGISTER HERE
URL:https://semiwiki.com/event/cadencelive-india/
LOCATION:Sheraton Grand Bengaluru Whitefield\, Sheraton Grand Bengaluru Whitefield\, PRESTIGE SHANTINIKETAN\, Hoodi\, Thigalarapalya\, Whitefield\, Bengaluru\, Karnataka\, 560048\, India
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/Screenshot-2026-06-16-134550.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260812
DTEND;VALUE=DATE:20260815
DTSTAMP:20260619T063613
CREATED:20260616T204334Z
LAST-MODIFIED:20260616T204334Z
UID:370364-1786492800-1786751999@semiwiki.com
SUMMARY:35th USENIX Security Symposium
DESCRIPTION:The 35th USENIX Security Symposium will take place on August 12–14\, 2026\, at the Baltimore Marriott Waterfront in Baltimore\, MD\, USA. The USENIX Security Symposium brings together researchers\, practitioners\, system programmers\, and others interested in the latest advances in the security and privacy of computer systems and networks. \nThe full symposium program will be available soon; view the Cycle 1 accepted papers. The Early Bird Registration deadline is Monday\, July 20\, 2026. Register today and save! \nApply for a Grant\nSee the USENIX Security ’26 grant opportunities page for more information. The application deadline is Monday\, July 6\, 2026. \nREGISTER HERE
URL:https://semiwiki.com/event/35th-usenix-security-symposium/
LOCATION:Baltimore Marriott Waterfront\, Baltimore Marriott Waterfront\, 700 Aliceanna St.\, Baltimore\, MD\, 21202\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/Screenshot-2026-06-16-134257.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260819
DTEND;VALUE=DATE:20260822
DTSTAMP:20260619T063613
CREATED:20260616T205304Z
LAST-MODIFIED:20260616T205304Z
UID:370373-1787097600-1787356799@semiwiki.com
SUMMARY:IEEE Hot Interconnects Symposium 2026
DESCRIPTION:Welcome to the 33rd iteration of the IEEE Hot Interconnects symposium. HotI’2026 will be held virtually. \n2026 Conference Theme\nScale-Up\, Scale-Out\, Scale-Across: Do they really differ? \nComplex high-capacity training and disaggregated inference workloads are being scaled-across multiple sites\, blurring the lines between contemporary scale-out and scale-up interconnection stacks. All the classical issues\, such as jitter\, bursts\, flow/congestion\, long-tail latencies\, etc.\, are amplified over long distances\, requiring deliberate interventions across the full interconnection stack: algorithms\, operational tools\, communication frameworks\, and network fabrics. This edition of Hot Interconnects will explore these interventions behind operationalizing interconnects over long\, short\, and shorter distances. \nHotI33 (2026) Overview\nIEEE Hot Interconnects is the premier international forum for researchers and developers of state of the art hardware and software architectures and implementations for interconnection networks of all scales\, ranging from multi-core on-chip interconnects to those within systems\, clusters\, and data centers. Leaders in industry and academia attend the conference to interact with individuals at the forefront of this field. \nOur objective is to address the data center networking and the supercomputing communities. We hope you can join us and benefit not only by the content but also by the prime networking opportunities this event always offers. \nREGISTER HERE
URL:https://semiwiki.com/event/ieee-hot-interconnects-symposium-2026/
LOCATION:Online
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/hoti_logo_150x75.png
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260823
DTEND;VALUE=DATE:20260826
DTSTAMP:20260619T063613
CREATED:20260616T205722Z
LAST-MODIFIED:20260616T205722Z
UID:370379-1787443200-1787702399@semiwiki.com
SUMMARY:Hot Chips 2026
DESCRIPTION:Hot Chips 2026 will be held Sunday\, August 23 – Tuesday\, August 25\, 2026 at Memorial Auditorium\, Stanford\, Palo Alto\, CA. \nEarly registration is now open; register by Friday\, July 31\, 2026\, for the best rate. \nAbout\n\nSince it started in 1989\, HOT CHIPS has been known as one of the semiconductor industry’s leading conferences on high-performance microprocessors and related integrated circuits. The conference is held once a year in August in the center of the world’s capital of electronics activity\, Silicon Valley. \nThe HOT CHIPS conference typically attracts more than 500 attendees from all over the world. It provides an opportunity for chip designers\, computer architects\, system engineers\, press and analysts\, as well as attendees from national laboratories and academia to mix\, mingle and see presentations on the latest technologies and products. The three days of the conference typically feature two tutorials\, two keynotes\, a panel discussion and around 25 presentations on a variety of subjects related to microprocessors and integrated circuits. It is widely covered by the media; last year\, we had about 25 members of the industry and national press covering the conference. \nPresentations at HOT CHIPS are in the form of 30-minute talks. Presentation slides are published in the HOT CHIPS proceedings and online in the archives section of the HOT CHIPS website. Participants are not required to submit written papers\, but a select group are invited to submit a paper for inclusion in a special issue of IEEE Micro. \nThe conference emphasis this year\, as in previous years\, is on real products and realizable technology. Submissions are invited from a variety of “hot” topics\, including embedded and reconfigurable processors\, quantum computing\, nano structures\, wireless chips\, network/security processors\, advanced packaging technology etc. For a complete list of topics\, refer to the official call for papers. \nThe program committee consisting of members from academia and industry\, is busy sorting through a record number of paper submissions this year. As usual\, the passionate and highly dedicated members of the program and organizing committees are working together to provide high quality content and experience to the HOT CHIPS conference attendees. \nThank you for your interest in HOT CHIPS. We hope to see you at the conference! \n\nREGISTER HERE
URL:https://semiwiki.com/event/hot-chips-2026/
LOCATION:Stanford Memorial Auditorium (MemAud)\, Stanford Memorial Auditorium (MemAud)\, 551 Jane Stanford Way\, Stanford\, CA\, 94305\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/hc_logo.png
END:VEVENT
END:VCALENDAR