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X-WR-CALDESC:Events for SemiWiki
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260219
DTEND;VALUE=DATE:20260221
DTSTAMP:20260509T034100
CREATED:20250624T160935Z
LAST-MODIFIED:20250624T160935Z
UID:357526-1771459200-1771631999@semiwiki.com
SUMMARY:Semitracks Course: Defect-Based Testing
DESCRIPTION:Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example\, today’s application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately\, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease\, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior\, fault models\, and test techniques. This course is a must for every manager\, engineer\, and technician working in IC test\, IC design\, or supplying test hardware and software tools to the industry. \nBy focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior\, participants will learn how to design\, write\, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline. \n\n\nWhat Will I Learn By Taking This Class?\nParticipants will learn basic\, but powerful\, aspects about defect-based testing. This skill-building series is divided into four segments: \n\nElectrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits\, resistive vias\, shorts\, and transistor variations affect the electrical behavior of the individual transistor\, as well as gate elements and larger blocks.\nFault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models\, including IDDQ testing\, at-speed testing\, and delay testing.\nProduction Test Methods. Participants will learn about standard digital testing\, SAF testing\, IDDQ\, timing\, low voltage tests\, and other types of stress tests. They will explore the strengths and weaknesses of each test type.\nThe Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.\n\n\n\n\n\nCourse Objectives\n\nThis course will provide participants with an in-depth understanding of defect-based testing and its technical issues.\nParticipants will understand the basic concepts of test economics\, yield\, test time\, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.\nThis course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.\nThis course will offer the opportunity to discuss specific test problems with our expert instructors.\nParticipants will be able to identify basic and advanced principles for defect-based test.\nParticipants will understand the difficulties in extending IDDQ testing to leading edge products\, and how to overcome some of these limitations.\nParticipants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.\nThis course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.\nParticipants will learn what tools are available today to implement defect-based testing.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semitracks-course-defect-based-testing/
LOCATION:Munich\, Germany\, Munich\, Germany
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/06/Screenshot-2025-06-24-085557.png
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20260218
DTEND;VALUE=DATE:20260221
DTSTAMP:20260509T034100
CREATED:20250828T045643Z
LAST-MODIFIED:20250828T045643Z
UID:361034-1771372800-1771631999@semiwiki.com
SUMMARY:Wafer-Level Packaging Symposium 2026
DESCRIPTION:Formatting Advanced Packaging for the Next Generation\nThe evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically\, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless\, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package technologies beyond conventional limits. The Wafer-Level Packaging Symposium will bring together the foremost experts in the semiconductor industry to examine all aspects of wafer and panel-level packaging\, 3D device packaging\, advanced manufacturing\, and testing technologies. Positioned at the forefront of packaging technology evolution\, this conference offers global attendees the chance to engage with the latest technological and business trends in the heart of Silicon Valley. \nREGISTER HERE
URL:https://semiwiki.com/event/wafer-level-packaging-symposium-2026/
LOCATION:Hyatt Regency San Francisco Airport\, 1333 Bayshore Highway\, Burlingame\, CA\, 94010\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/WLPS_2026_Masthead.png
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260217T100000
DTEND;TZID=America/Los_Angeles:20260217T110000
DTSTAMP:20260509T034100
CREATED:20260113T043754Z
LAST-MODIFIED:20260113T043754Z
UID:365670-1771322400-1771326000@semiwiki.com
SUMMARY:Webinar: How Secure Are Your Critical Aerospace & Defense Systems?
DESCRIPTION:Aerospace\, defense\, and other mission-critical technologies face rapidly evolving hardware threats. A hobbyist can add a single board computer to a consumer device. A nation-state can scale an exploit across critical infrastructure. The attack surface widens fast\, and the security implications are real. \nAdversaries are continuously developing techniques that can compromise mission-critical components\, sometimes before they even reach deployment. From side-channel analysis to fault injection\, attackers are finding new ways to extract sensitive data\, disrupt operations\, and manipulate critical systems. \nJoin us for a technical deep dive into how modern hardware attacks work in practice and what engineering teams can do to build more resilient systems. \nIn this session\, we’ll cover: \n\nReal attack examples on complex systems\, like satellite terminals and commercial drones.\nHow side-channel analysis techniques reveal power\, electromagnetic\, and unintended RF leakage that expose cryptographic operations.\nHow fault injection induces glitches to bypass authentication and break security logic.\n\nYou’ll also see a demo of our Fault Injection Laser System with our Inspector software. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-how-secure-are-your-critical-aerospace-defense-systems/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203709.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260217
DTEND;VALUE=DATE:20260220
DTSTAMP:20260509T034100
CREATED:20250828T045454Z
LAST-MODIFIED:20250828T045454Z
UID:361030-1771286400-1771545599@semiwiki.com
SUMMARY:Chiplet Summit 2026
DESCRIPTION:All the Solutions for Developing Chiplets\n2025 Keynote Addresses from Industry Leaders: \nAlphawave Semi\, Arm\, Cadence Design Systems\, Keysight\, Open Compute Project\, Synopsys\, Teradyne \n2025’s Main Topics Included: \nAI/ML Acceleration\, Open Chiplet Economy\, Advanced Packaging Methods\, Die-to-die Interfaces\, Working with Foundries \nsignup to be a 2026 SPONSOR / Exhibitor \nREGISTER HERE
URL:https://semiwiki.com/event/chiplet-summit-2026/
LOCATION:Santa Clara Convention Center\, Santa Clara Convention Center\, 5001 Great America Pkwy\, Santa Clara\, CA\, United States
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2025/08/cropped-Chiplet-Logo.jpg
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260215
DTEND;VALUE=DATE:20260220
DTSTAMP:20260509T034100
CREATED:20250828T045208Z
LAST-MODIFIED:20250828T045208Z
UID:361021-1771113600-1771545599@semiwiki.com
SUMMARY:2026 IEEE International Solid-State Circuits Conference (ISSCC)
DESCRIPTION:About ISSCC\nThe International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency\, and to network with leading experts. \nWhat’s New\n\nDownload the ISSCC 2026 Plenary/Educational Events Flyer\nThe ISSCC 2026 paper submission site is now open\nDownload the ISSCC 2026 Call for Papers\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/2026-ieee-international-solid-state-circuits-conference-isscc/
LOCATION:San Francisco Marriott Marquis\, San Francisco Marriott Marquis\, 780 Mission Street\, San Francisco\, CA\, 94103\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2025/08/Screenshot-2025-08-27-215048.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260211
DTEND;VALUE=DATE:20260214
DTSTAMP:20260509T034100
CREATED:20260107T031917Z
LAST-MODIFIED:20260107T031917Z
UID:365313-1770768000-1771027199@semiwiki.com
SUMMARY:SEMICON Korea 2026
DESCRIPTION:Date: Feburary 11-13\, 2026\nHours\n\nFebruary 11\, 2026 | 10:00-17:00 (Last entry 16:30)\nFebruary 12\, 2026 | 10:00-17:00 (Last entry 16:30)\nFebruary 13\, 2026 | 10:00-16:00 (Last entry 15:30)\n\nVenue\n\nCOEX (Hall A\, B\, C\, D\, E\, Grand Ballroom\, Platz and ASEM Ballroom)\nWestin Seoul Parnas\nGrand InterContinental Seoul Parnas\n\nScale\n\n550 Exhibitors\, 2411 booths (2025: 501 exhibitors\, 2301 booths)\n\nHighlights\nGlobal Supply Chain \nOver 550 semiconductor companies from around the world will participate with 2\,411 booths\, welcoming 70\,000 attendees. \nKeynote Speech \nLeaders in the semiconductor industry will provide valuable insights for the future. \nTech Conferences \nAt 30 technology programs\, 200 visionaries will share the most noteworthy tech trends shaping the industry. \nBusiness Programs \nInvestment forums will be held to explore investment opportunities in countries such as the United States and Netherlands. \nSupplier Search Program \nTo support the global expansion of Korea’s semiconductor materials\, components\, and equipment companies\, around 100 business meetings will be conducted with major chip makers. \nWorkforce Development \nMentoring programs for university students aspiring to pursue careers in the semiconductor industry will be offered. \n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/semicon-korea-2026/
LOCATION:COEX Auditorium\, 513\, Yeongdong-daero\, Seoul\, Gangnam-gu\, 06164\, Korea\, Republic of
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/01/images.jpg
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260210T110000
DTEND;TZID=America/Los_Angeles:20260210T120000
DTSTAMP:20260509T034100
CREATED:20260107T111533Z
LAST-MODIFIED:20260107T111533Z
UID:365423-1770721200-1770724800@semiwiki.com
SUMMARY:Webinar: Meet Compact-Q DEER Spectrometer\, Your Gateway to Quantum Innovation
DESCRIPTION:Intro\n\n\n\n\n\n\n\nThe Compact-Q DEER Spectrometer is designed to support researchers in academia and industry to efficiently characterize quantum materials\, develop devices for quantum sensing\, advance and validate algorithms to control qubits\, and other applications in spin-based quantum technologies. The Compact-Q DEER system features a modern microwave architecture\, high-resolution AWG\, and digital signal processing schemes enabling high flexibility in addressing modern challenges of quantum technologies. \n\n\n\n\n\n\n\n\n\n\n\n\n\nWebinar Overview\n\n\n\n\n\n\n\nThe focus of this webinar will be to highlight the capabilities of the Compact-Q DEER spectrometer towards the characterization and coherent control of qubits for quantum technologies. Modern experiments in Quantum Information Science (QIS) demand a state-of-the-art microwave architecture\, fast\, high-memory\, high-resolution AWGs\, large transmission and detection bandwidths\, and modern digital signal processing features to create the most sophisticated pulse shapes\, quantum gates and read-out sequences. Having all of those features incorporated\, as well as operating at an intermediate frequency of 500 MHz\, and utilizing a cryogen-free 1.5 T magnet with integrated Variable Temperature Insert (iVTI) enabling temperatures from 2 K to RT\, the Compact-Q system meets modern demands and provides a versatile and high-fidelity platform for probing qubit properties and execution of quantum algorithms driving innovations in quantum technologies. \n\n\n\n\nWhat to Expect\n\n\n\n\n\n\n\nDuring this webinar\, we will demonstrate how the Compact-Q DEER is ideally suited for applications in QIS. We will show how broad-band echo sequences can be used to manipulate spin states and how electron spin coherences can be created and detected. We will explain the different spectrometer features\, the data acquisition platform along with different experiments\, highlighting how the Compact-Q can elevate your research in quantum information science (QIS). \n\n\n\n\n\n\n\n\n\n\n\n\n\nKey Learning Points\n\n\n\n\n\n\n\nVersatility\, high-performance\, and user-friendly operation of the Compact-Q DEER spectrometer will be highlighted along with: \n\nEasy to use resonator bandwidth control\nAWG generated pulses\, digital down conversion\, and FIR filtering\nPulse shaping and quantum gate optimization\nBroadband and selective inversion pulse schemes\nStudying spin dephasing mechanisms and materials characterization\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nWho Should Attend?\n\n\n\n\n\n\n\n\nUndergraduate and graduate students in chemistry\, physics\, quantum information science\, material science\, and related fields\nEarly-career researchers\, postdoctoral fellows\, and instrument facility managers familiar or new to EPR spectroscopy\nProfessors and instructors teaching EPR spectroscopy or related courses\nSpectroscopy facility managers\nIndustry professionals\, scientists\, and engineers in materials science and quantum technologies industries\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-meet-compact-q-deer-spectrometer-your-gateway-to-quantum-innovation/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-07-031446.png
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