SEMICON Japan 2025
2025-12-17 - 2025-12-19 | Tokyo Big Sight, 3 Chome-11-1 Ariake, Koto City, Tokyo, Japan
SEMICON Japan is the premier event that brings together the semiconductor manufacturing supply chain for the latest insights, trends and innovations as the industry powers digital transformation. SEMICON Japan 2025 will highlight Smart applications powered by semiconductor technology such as automotive and Internet of Things (IoT).
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Webinar: From Silos to Systems, From Data to Insight (AM Session)
2025-12-17 10:00 - 11:00 (America/Los_Angeles) | Online
December 17, 2025 | 10:00 AM PST
Join us to discover how Keysight Design Data Management (SOS) Enterprise Collaboration, as the backbone for modern engineering enterprises, enables teams to build organizational knowledge, secure collaboration, and prepare their data for AI and agentic workflows that drive measurable competitive advantage. The biggest challenges today are managing complexity, ensuring governance, and preparing data for AI. That’s exactly why Keysight SOS becomes critical.
What You Can Learn:

How to transition from disconnected design data silos to a unified, governed platform that accelerates collaboration and reuse.
How structured, traceable data enables analytics, machine learning, and AI copilots to boost design productivity and reduce rework.
How Keysight SOS Enterprise Collaboration empowers organizations to scale globally with secure governance, hybrid deployment, and AI-ready infrastructure.

Who Should Attend?

Engineering Directors and VPs of R&D seeking to modernize design collaboration and build enterprise-wide data governance.
CAD/EDA Managers and Methodology Leads responsible for tool integration, data management, and multi-site standardization.
Design and Verification Leads looking to improve traceability, reuse, and cross-domain visibility in complex design workflows.
IT and Data Governance Executives focused on compliance, audit readiness, and secure access to sensitive design data.
AI/ML Engineers and Data Scientists aiming to leverage structured engineering data for analytics, modelling, and AI-driven design acceleration.

Not in the Americas? Our European friendly session is also available – join here.

Presenter

Pedro Pires
Product Manager – Keysight Technologies
Pedro Pires is a Product Leader at Keysight Technologies with deep expertise in data management, engineering productivity, and MLOps for electronic design automation (EDA). With over a decade of experience spanning product strategy, design infrastructure, and enterprise data lifecycle management, he has helped global semiconductor organizations modernize their engineering environments through scalable collaboration, governance, and process automation.
At Keysight, Pedro leads initiatives that connect design and data platforms across global teams, defining the architecture for next-generation solutions that unify design data and enable AI readiness through sound data foundations. He holds a Master’s in Microelectronics Engineering, an MSc in Finance and Big Data, and is pursuing an Executive MBA at IESE Business School in Barcelona.

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Essential Debugging Techniques Workshop
2025-12-17 10:00 - 16:00 | Online
Essential Debugging Techniques Workshop
This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with general debugging concepts, tools and techniques. Special topics include helping guide attendees through the differences of using ISE Design Suite based ChipScope in Vivado for migrating to 7 Series devices and onward.
Additionally, this workshop will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. The demonstrations utilizing actual AMD ZCU104 Evaluation Boards provide attendees with experience designing, expanding and modifying an embedded system, including techniques for triggering on boot and hardware-software co-debugging.

COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.

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Webinar: 5 Expectations for the Mobile Market in 2026
2026-01-05 11:00 - 12:00 | Online
January 5, 2026 – 11:00 AM EST
January 6, 2026 – 10:00 AM JST/KST
Discover the 5 Critical Mobile Market Trends Reshaping Semiconductors in 2026
Mobile AI, shifting supply chains, and new form factors—what’s next for the mobile semiconductor industry.
The mobile semiconductor market faces an inflection point in 2026. While trade and tariff uncertainties continue to disrupt global supply chains, breakthrough technologies promise to reinvigorate growth in an industry facing maturity pressures.
As Google, Apple, and new disruptors expand AI-driven mobile experiences, OEMs are rethinking hardware design, SoC innovation, and DRAM integration to meet rising consumer expectations. At the same time, geopolitical dynamics are reshaping long-term manufacturing strategies, and BRIC and emerging markets are exerting new influence over global demand.
In this live TechInsights webinar, our experts will break down five critical developments reshaping the mobile industry in 2026 and beyond.
Key Topics You’ll Learn

Mobile AI adoption – Google, Apple, and potential disruptors drive consumer traction.
Hardware & AI co-evolution – SoCs and DRAM innovation across Android OEMs.
Tariffs & trade impact – How pricing and supply chains are being reshaped.
Emerging market influence – BRIC nations and new growth regions take the stage.
Form-factor innovation – New designs promise to revitalize a stagnating market.

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CES 2026
2026-01-06 - 2026-01-09 | Las Vegas Convention Center, Las Vegas Convention Center, 3150 Paradise Rd, Las Vegas, NV, 89109, United States
The world’s most powerful tech event is your place to experience the innovations transforming how we live.

This is where global brands get business done, meet new partners and where the industry’s sharpest minds take the stage to unveil their latest releases and boldest breakthroughs. Get a real feel for the latest solutions to the world’s biggest challenges with immersive activations and demos. Engage with the greatest minds and most impactful brands of our time. Sign up to be notified when registration opens for CES 2026.

CES unites the brightest tech luminaries to pioneer the future and solve the world’s biggest challenges.

CES connects innovators, decision makers, media, influencers, visionaries, and potential customers across the entire tech ecosystem.
Don’t be left in the past as we shape the future.

Globally showcase your technology products
Stand side-by-side with the world’s most disruptive innovators
Promote your brand through curated opportunities to connect with influencers and prospective partners

REGISTER HERE

ISS 2026 Industry Strategy Symposium
2026-01-11 - 2026-01-14 | The Ritz-Carlton, Half Moon Bay, The Ritz-Carlton, 1 Miramontes Point Rd, Half Moon Bay, CA, 94019, United States
Join us at the Ritz-Carlton in Half Moon Bay, CA to get the latest insights on economic trends, market drivers, geopolitics, technology, and what these will mean for the near future to help drive your business forward. The cooperative platform of ISS and its tremendous collective assets will serve to help power your strategies for the coming months and years.
READY, SET, RAMP!

Building upon last year’s theme “Ready, Set, Ramp? “ of readiness and anticipation, this year marks a bold declaration of action and confidence as we propel forward with vigor and purpose.
“Ready, Set, Ramp! serves as a call to action for industry stakeholders to navigate these uncharted waters with agility and strategic vision.
It replaces the question marks of uncertainty with the exclamation points of determination and readiness!
As the semiconductor industry accelerates towards the monumental trillion-dollar milestone, it’s crucial to explore strategies for coping with the rapid acceleration. Understanding and maneuvering through the dynamic landscape becomes paramount for sustained prosperity.
ISS delves into the multifaceted dimensions of this journey, encompassing technological innovations, burgeoning demand, market diversification, global integration, R&D investments, workforce shortage, and sustainable practices. Addressing challenges and harnessing opportunities necessitates a holistic approach, requiring collaborative efforts from industry stakeholders, governments, and research institutions.

What are the demands and challenges inherent in this accelerated growth?
How is the industry allocating resources to facilitate this ramp-up?
How do we set the stage for all-time highs in semiconductor revenue and Wafer Fabrication Equipment (WFE) Investment?
Exploring the impact of emerging technologies and market diversification on the ramp-up trajectory.
Accelerated computing powering a new industrial revolution–Are we prepared?
What collaborative efforts and partnerships are necessary to overcome challenges and capitalize on opportunities as we surge toward the trillion-dollar milestone?

By engaging in these critical key questions and through collaborative discussions, ISS attendees gain actionable insights and strategies for capitalizing on the industry’s upward trajectory while mitigating risks and challenges along the way, positioning themselves for success in the race toward the trillion-dollar milestone.
KEYNOTES

AMD—Ramine Roane, Corporate VP, AI
Applied Materials—Omkaram Nalamasu, PhD, Senior Vice President and CTO; Prabu Raja, PhD, President, Semiconductor Products Group
KLA—Oreste Donzella, Executive Vice President – Electronics, Packaging and Components (EPC) Group
TSMC—Kevin Zhang, PhD, Senior Vice President of Business Development & Global Sales and Deputy Co-COO
Former U.S. Secretary of Commerce—The Honorable Wilbur Ross

ISS 2025 Organizing Committee
Thank you to these industry leaders for their time and expertise supporting the continued success of this annual conference.
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Terascale AI, 1.6T and Beyond Seminar: Santa Clara
2026-01-13 08:00 - 17:00 | Santa Clara, CA, Santa Clara, CA, United States
About this event
Next-generation AI systems are pushing electrical, optical, and packaging technologies to their limits. Join Keysight experts as they share insights on validating 224G / 448G SerDes, preparing for emerging IEEE 1.6T optical standards, advancing silicon photonics, and strengthening die-to-die interconnects for chiplet-based architectures.
This is your chance to learn directly from the engineers shaping the future of high-speed I / O design — all in one room. Sign up today.

Who should attend this event?
This seminar is ideal for engineers working on next-generation connectivity and AI infrastructure, including optical design, silicon photonics, high-speed digital, validation, test & measurement, signal integrity, compliance, and chiplet / die-to-die interconnect architectures.

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Webinar: PQShield with Microchip’s PolarFire® SoC FPGAs: Securing the Future of Embedded Systems in the Post-Quantum Era
2026-01-13 09:00 - 10:00 | Online
As the quantum threat moves from theory to reality, attacks put all long-lifecycle designs at risk. In this early PQC era, simply implementing the new NIST algorithms isn’t enough. Implementations will evolve, and new physical attacks like side-channel analysis present a major threat to the security of these complex new algorithms.
The solution requires both crypto-agility and deep hardware security. This webinar showcases PQShield’s hardware/software co-design as a side-channel secure PQC solution for Microchip’s PolarFire ® Series of products.

Speaker:

Sebastien Riou
Fellow, Product Security Architecture, PQShield

Sebastien has 15+ years experience in the semiconductor industry, focusing on achieving “banking grade security” on resource constrained ICs such as smart cards and mobile secure elements. Formerly of Tiempo-Secure, he helped create the world first integrated secure element IP achieving CC EAL5+ certification. He is the author of a semi-finalist algorithm at the Lightweight Cryptography NIST Standardisation process. He holds Master degrees in Computer Science and Cognitive Science from INPG.

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Webinar: 5 Expectations for the Manufacturing Market in 2026
2026-01-14 11:00 - 12:00 | This course will be held Online
Discover the 5 Critical Manufacturing Market Trends Reshaping Semiconductors in 2026
AI-driven investments, sustainability, and advanced materials—what’s next for semiconductor manufacturing.
The semiconductor manufacturing industry is undergoing a transformative period as AI-driven investments accelerate, sustainability pressures mount, and foundries navigate capacity expansion amid weak consumer demand.
In this live TechInsights webinar, our manufacturing experts will highlight five critical developments shaping semiconductor fabrication and equipment markets in 2026, offering actionable insights for strategists, foundry operators, and equipment suppliers.
Key Topics You’ll Learn

TSMC’s 2nm Mass Production Leadership – Achieving 7% of total capacity by 2026 while foundry/logic CAPEX rises for the first time since 2022.
China’s Role in Equipment Sales – Export control uncertainties and slower recovery extending into 2027, with fabrication emissions projected to reach 200M metric tons CO₂e.
Inventory Optimization & AI Growth – Leveraging oversupply in consumer, industrial, and automotive segments to focus on AI-driven production.
Glass Substrates Challenge Traditional Materials – Superior flatness, signal integrity, and sub-2-micron via capabilities for AI accelerators and HBM applications.
Wafer Fab Equipment Growth Focus – Concentration in microlithography for cutting-edge AI chips, with subsystem suppliers benefiting from Asian capacity expansions.

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Advanced Measurements Seminar - Calgary
2026-01-15 09:00 - 17:00 | Calgary, AB, Calgary, Alberta, Canada
About this event
Start the new year off right with fresh insights and sharp skills. Join Keysight experts in Calgary for an all-day Advanced Measurements Seminar and cocktail reception. This hands-on technical event features live demonstrations with the latest RF and high-speed digital technologies.
Gain practical, lab-ready insights to enhance accuracy, reduce uncertainty, and push your measurement capabilities further in 2026. Lunch and cocktails are on us.
Learn more and reserve your spot today!

Who should attend this event?
Ideal for RF and high-speed digital engineers looking to deepen their measurement expertise.

REGISTER HERE

Webinar: ASU-Silvaco Device TCAD Workshop: From Fundamentals to Applications
2026-01-16 09:30 - 17:30 | ASU Tempe Campus, ASU Tempe Campus, Old Main Building, 400 East Tyler Mall, Second Floor, Tempe, AZ, 85287, United States
This workshop is a fast-paced, one-day program led by Prof. Dragica Vasileska and Prof. Stephen M. Goodnick. Spend the morning grounding yourself in semiconductor physics and transport, then transition in the afternoon to instructor-led, hands-on Silvaco TCAD labs (e.g., MOS Capacitors, MOSFETs, SOI Devices, FinFETs).
The workshop is offered in a hybrid format. Participants have the option to join either in person at ASU or virtually via Zoom.
Attendees will learn to use Silvaco TCAD effectively and know how to select the appropriate physical models and material parameters for their devices. Whether you are an industry professional or student, you will leave with a practical grasp of semiconductor physics and the skills to use Silvaco TCAD effectively and efficiently. Complimentary lunch will be served, followed by a Silvaco overview and Digital Twin session from Silvaco’s VP of Worldwide Field Applications Engineering, Garrett Schlenvogt.
When: January 16, 2026
Time: 9:30am-5:30pm
Where: ASU Tempe Campus
Old Main Building
400 East Tyler Mall
Second Floor
Tempe, AZ, 85287
Seating is limited so register soon.
REGISTER HERE

SPIE Photonics West 2026
2026-01-17 - 2026-01-22 | San Francisco, CA, San Francisco, CA, United States
Share your work, insights, and breakthroughs. The 2026 call for papers is open.
SPIE Photonics West is the world’s largest optics and photonics technologies event. Present your research in biomedical optics, biophotonics, industrial lasers, optoelectronics, microfabrication, displays, quantum, and emerging vision technologies.
Conferences and Courses: 17–22 January
This is the place to be in January
Experience the benefits of attending SPIE Photonics West—networking with colleagues, learning the latest research, and experiencing the newest innovations make this the most exciting week in photonics. See for yourself.
Plan to take a course from an expert
Course offerings will give you the technical training you need to excel in your field. Choose from more than 55 courses in San Francisco during SPIE Photonics West. Adding a course to your registration adds to your entire event experience.
Five major exhibitions
Explore the companies that exhibit at the SPIE Photonics West Exhibition, BiOS Expo, AR | VR | MR Expo, and Quantum West Expo. These leading companies are providing new capabilities and innovative products to help move your projects forward. Plus, new this year, Vision Tech Expo is growing.
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IEEE Hybrid Bonding Symposium
2026-01-22 - 2026-01-23 | SEMI HQ, SEMI HQ, 673 S Milpitas Blvd., Milpitas, CA, 95035, United States
January 22-23, 2026, hosted by SEMI International, Silicon Valley, CA USA
Note: HBS’26 is a hybrid event, with both in-person and virtual participation via WebEx.
Download the Call for Presentations!
Hybrid Bonding has emerged as the technology of choice in the semiconductor and heterogeneous integration industries for ultra-fine-pitch interconnection. With significant benefits for interconnect density and device performance, it will become widely adopted for a broad range of high-performance semiconductor devices in the years to come. The success of Hybrid Bonding technology for high-volume manufacturing depends critically on the process technology as well as materials and equipment. Design, performance characterization, thermal management and reliability are also important considerations to enable applications in various areas.
Review the HBS’25 Program, and watch videos of most of the presentations.
Post-Symposium Report on the 2025 Hybrid Bonding Symposium
REGISTER HERE

Optical Design Engineering User Conference
2026-01-22 08:30 - 17:00 | San Francisco, CA, San Francisco, CA, United States
About this event
Stay connected with the latest optical design product innovations across CODE V, LightTools, RSoft, ImSym, and our optical scattering measurement solutions. Get tips and tricks on design best practices from our experts, and network with industry peers and the Keysight Optical Design Engineering team. The user conference is held in parallel with Photonics West, making it an ideal opportunity to deepen your expertise while connecting with the broader photonics community.

Who should attend this event?
Optical engineers using CODE V, LightTools, RSoft, ImSym, and our optical scattering measurement solutions.

REGISTER HERE

ESDA Webinar—When Devices Become Weapons: A Closer Look at the Pager Attacks
2026-01-22 10:00 - 11:00 | Online
On October 17-18, 2024, Israel launched a deadly attack on Hezbollah in Lebanon and Syria using tampered pager and walkie-talkie devices, nicknamed “Operation Grim Beeper.” The exploding pager attack illustrates the vulnerability of the electronics supply chain to a dedicated nation-state adversary. We will explain how the supply was compromised and focus specifically on the vulnerabilities of battery systems which lie at the core of modern operations—from EV fleets and energy storage sites to portable devices. Our talk translates cutting-edge research into a practical, field-ready playbook: how to rigorously evaluate suppliers, detect sophisticated counterfeits beyond visual or X-ray methods, and verify authenticity at both receipt and deployment.
We’ll also cover techniques for hardening Battery Management Systems (BMS) against denial-of-service and firmware manipulation, and for implementing lightweight anomaly detection to flag unsafe conditions in real time. Participants will learn how to map their battery security attack surface, implement immediate safeguards (procurement guardrails, acceptance testing, RF/PCB shielding, firmware controls), and plan near-term upgrades (battery “fingerprinting,” traceability, and zero-trust workflows). The session concludes with actionable checklists, Key Performance Indicators (KPIs), and validation steps to minimize recall risk, reduce downtime, and enhance safety—without disrupting production or delivery schedules.
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Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
2026-01-28 10:00 - 11:00 | Online
In this webinar, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks.
We will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout.
We will show you how these tools work on real designs as well.
WHO SHOULD ATTEND THIS WEBINAR?
If you are designing chips to deploy in networked environments, you need to understand the risks ahead and how to minimize them.
If you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions.
SPEAKERS
Beau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies
Dr. Paul Calzada will take you through a live demonstration of CODAx, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions.
* This webinar is in partnership with SemiWiki and Caspia Technologies
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2026 IEEE International Solid-State Circuits Conference (ISSCC)
2026-02-15 - 2026-02-19 | San Francisco Marriott Marquis, San Francisco Marriott Marquis, 780 Mission Street, San Francisco, CA, 94103, United States
About ISSCC
The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts.
What’s New

Download the ISSCC 2026 Plenary/Educational Events Flyer
The ISSCC 2026 paper submission site is now open
Download the ISSCC 2026 Call for Papers

REGISTER HERE

Chiplet Summit 2026
2026-02-17 - 2026-02-19 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
All the Solutions for Developing Chiplets
2025 Keynote Addresses from Industry Leaders:
Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne
2025’s Main Topics Included:
AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries
signup to be a 2026 SPONSOR / Exhibitor
REGISTER HERE

Wafer-Level Packaging Symposium 2026
2026-02-18 - 2026-02-20 | Hyatt Regency San Francisco Airport, 1333 Bayshore Highway, Burlingame, CA, 94010, United States
Formatting Advanced Packaging for the Next Generation
The evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package technologies beyond conventional limits. The Wafer-Level Packaging Symposium will bring together the foremost experts in the semiconductor industry to examine all aspects of wafer and panel-level packaging, 3D device packaging, advanced manufacturing, and testing technologies. Positioned at the forefront of packaging technology evolution, this conference offers global attendees the chance to engage with the latest technological and business trends in the heart of Silicon Valley.
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Semitracks Course: Defect-Based Testing
2026-02-19 - 2026-02-20 | Munich, Germany, Munich, Germany
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior, fault models, and test techniques. This course is a must for every manager, engineer, and technician working in IC test, IC design, or supplying test hardware and software tools to the industry.
By focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior, participants will learn how to design, write, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about defect-based testing. This skill-building series is divided into four segments:

Electrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits, resistive vias, shorts, and transistor variations affect the electrical behavior of the individual transistor, as well as gate elements and larger blocks.
Fault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models, including IDDQ testing, at-speed testing, and delay testing.
Production Test Methods. Participants will learn about standard digital testing, SAF testing, IDDQ, timing, low voltage tests, and other types of stress tests. They will explore the strengths and weaknesses of each test type.
The Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.

Course Objectives

This course will provide participants with an in-depth understanding of defect-based testing and its technical issues.
Participants will understand the basic concepts of test economics, yield, test time, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.
This course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.
This course will offer the opportunity to discuss specific test problems with our expert instructors.
Participants will be able to identify basic and advanced principles for defect-based test.
Participants will understand the difficulties in extending IDDQ testing to leading edge products, and how to overcome some of these limitations.
Participants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.
This course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.
Participants will learn what tools are available today to implement defect-based testing.

REGISTER HERE

SPIE Advanced Lithography + Patterning 2026
2026-02-22 - 2026-02-26 | San Jose McEnery Convention Center, San José McEnery Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
From materials to metrology: pushing the limits of lithography
Share your research, challenges, and breakthroughs at this leading semiconductor conference in San Jose
Submit your abstract and connect with leading researchers advancing solutions in optical lithography, EUVL, patterning technologies, metrology, and process integration for semiconductor manufacturing and related applications.
Call for papers is now open.
REGISTER HERE

Semitracks Course: Wafer Fab Processing
2026-02-23 - 2026-02-26 | Munich, Germany, Munich, Germany
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is a 4-day course that offers an in-depth look into the semiconductor manufacturing process, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique, and we delve into the current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.
By focusing on the basics of each processing step and the issues surrounding them, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about the semiconductor industry. This skill-building series is divided into three segments:

Basic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. Participants will learn the fundamentals of each processing step and why they are used in the industry today.
The Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants will learn how each technique has evolved for use in previous and current generation ICs.
Current Issues in Wafer Fab Processing. Participants will learn how many processing steps are increasingly constrained by physics and materials science. They will also learn about the impact of using new materials in the fabrication process, and how those materials may create problems for the manufacturers in the future.

This course is a must for every manager, engineer, and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

Course Objectives

This course will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.
Participants will understand the basic concepts behind the fundamental wafer fab processing steps.
This course will identify the key issues related to each of the processing techniques, and their impact on the continued scaling of the semiconductor industry.
This course will offer a wide variety of sample problems that participants will work to help them gain knowledge of the fundamentals of wafer fab processing.
Participants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition, ion implantation, lithography, and etching.
Participants will understand how processing, reliability, power consumption and device performance are interrelated.
Participants will be able to make decisions about how to construct and evaluate processing steps for CMOS, BiCMOS, and bipolar technologies.

REGISTER HERE

FLEX 2026 - Technology Summit
2026-02-24 - 2026-02-26 | The WIGWAM, The Wigwam, 300 E Wigwam Blvd, Litchfield Park, AZ, 85340, United States
FLEX 2026 | TECHNOLOGY SUMMIT | FEBRUARY 24-26, 2026
THE WIGWAM ARIZONA RESORT | PHOENIX, AZ
A 25th Anniversary Celebration
Escape the winter and celebrate 25 years of innovation with us at The Wigwam Arizona Resort in Phoenix, AZ.

FLEX—Technology Summit is a vibrant networking event designed to foster community building. Connect with like-minded professionals, share ideas, and forge lasting relationships that will drive the industry forward.
At FLEX, you’ll experience high-quality technical sessions led by industry-leading speakers who are at the forefront of their fields. Sessions include topics on wearable and harsh environment technologies, heterogeneous integration and advanced packaging, flexible hybrid electronics, printed electronics, additive manufacturing, integrated photonics, flexible displays, digital twins, artificial intelligence, and manufacturing. Additionally, you’ll gain valuable business insights and market trends that provide a comprehensive view of the state of the industry.
Explore the solution zone to see cutting-edge technologies and connect with innovations shaping the future. Don’t miss this chance to stay ahead in a rapidly evolving tech landscape.
REGISTER HERE

Semitracks Course: Failure and Yield Analysis
2026-03-02 - 2026-03-05 | Munich, Germany, Munich, Germany
Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. Failure and Yield Analysis is a 4-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure. This course is designed for every manager, engineer, and technician working in the semiconductor field, using semiconductor components or supplying tools to the industry.
By focusing on a Do It Right the First Time approach to the analysis, participants will learn the appropriate methodology to successfully locate defects, characterize them, and determine the root cause of failure.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what tools and techniques should be applied, and when they should be applied. This skill-building series is divided into three segments:

The Process of Failure and Yield Analysis. Participants will learn to recognize correct philosophical principles that lead to a successful analysis. This includes concepts like destructive vs. non-destructive techniques, fast techniques vs. brute force techniques, and correct verification.
The Tools and Techniques. Participants will learn the strengths and weaknesses of a variety of tools used for analysis, including electrical testing techniques, package analysis tools, light emission, electron beam tools, optical beam tools, decapping and sample preparation, and surface science tools.
Case Histories. Participants will identify how to use their knowledge through the case histories. They will learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed.

Course Objectives

This course will provide participants with an in-depth understanding of the tools, techniques and processes used in failure and yield analysis.
Participants will be able to determine how to proceed with a submitted request for analysis, ensuring that the analysis is done with the greatest probability of success.
This course will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.
This course will offer a wide variety of video demonstrations of analysis techniques, so the analyst can get an understanding of the types of results they might expect to see with their equipment.
Participants will be able to identify basic technology features on semiconductor devices.
Participants will be able to identify a variety of different failure mechanisms and how they manifest themselves.
Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

REGISTER HERE

DVCON U.S. 2026
2026-03-02 - 2026-03-05 | Hyatt Regency Hotel, Santa Clara, CA, Santa Clara, CA, United States
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well as general purpose languages such as C, C++, Python, PERL and Tcl. Tools and methodologies include the use of artificial intelligence, machine learning, open-source software, hardware and architecture, testbench automation, hardware-assisted verification, hardware/software co-verification, formal verification, functional safety and security, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP-based SoC design methods, reference flows and Mixed Signal design and verification.

Call for Submissions
The deadline to submit your proposal for an extended abstract, sponsored tutorial, or sponsored workshop is fast approaching! Be sure to get your submission in by September 7.

The Design & Verification Conference is looking for submissions for the in-person 2026 Conference and Exhibition. This conference focuses on the practical aspects of design and verification of electronic systems and integrated circuits. This could be applications of languages, tools, methodologies, and/or standards. This could be your chance to help the industry we are all a part of. For those familiar with DVCon, the submission timeline has changed for this year. Please see below for more details.
DVCon honors the Sutherland Best Paper submissions. The awards will be selected by the attendees at DVCon, based on the quality of both the paper and their presentation. Awards will be offered for both lecture and poster presentation formats. So please submit your abstract and join DVCon U.S. 2026!

REGISTER HERE

MWC 2026
2026-03-02 - 2026-03-05 | Fira Gran Via, Barcelona, Fira Gran Via, Av. Joan Carles I, 64, Barcelona, 08908, Spain
Making way for The IQ Era

Much can happen in a year within our ecosystem of innovation and connectivity. As we build on the success of MWC25 and engage with MWC26 to activate a new theme – The IQ Era – the world is already shifting to greater heights of digital awareness.
In this new age of intelligence, the way to a better future is through smarter connection: human ideas leading technology, commercial impact and societal progress. MWC is where leaders of nations, business and technology assemble, and collective knowledge collaborates – make your insight count in The IQ Era.
Why attend MWC Barcelona?
From eye-opening innovation to mind-expanding ideas, global policy to lasting partnerships, it all starts here. Whether you’re a key player in the connectivity ecosystem, adjacent industries or the wider world of tech, you’ll find all you need and more at MWC.

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Semitracks Course: Semiconductor Reliability and Product Qualification
2026-03-09 - 2026-03-12 | Munich, Germany, Munich, Germany
Product reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past, reliability meant discovering, characterizing and modeling failure mechanisms, and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability; assessing the impact of new materials; dealing with limited margins, and other factors. This requires information on subjects like: statistics, testing, technology, processing, materials science, chemistry, and customer expectations. While customers expect high reliability levels, incorrect testing, calculations, and qualification procedures can severely impact reliability. Semiconductor Reliability and Product Qualification is a 4-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and qualification. This course is designed for every manager, engineer, and technician concerned with reliability in the semiconductor field, qualifying semiconductor components, or supplying tools to the industry.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what failure mechanisms might occur, and how to test for them, develop models for them, and eliminate them from the product. This skill building series is divided into four segments:

Overview of Reliability and Statistics. Participants will learn the fundamentals of statistics, sample sizes, distributions and their parameters.
Failure Mechanisms. Participants will learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die and at the package level. These include: time-dependent dielectric breakdown, hot carrier degradation, electromigration, stress-induced voiding, moisture, corrosion, contamination, thermomechanical effects, interfacial fatigue, and others.
Qualification Principles. Participants will learn how test structures can be designed to help test for a particular failure mechanism.
Test Strategies. Participants will learn about the JEDEC test standards, how to design screening tests, and how to perform burn-in testing effectively.

Course Objectives

This course will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today’s high reliability components.
Participants will be able to gather data, determine how best to plot the data and make inferences from that data.
This course will identify the major failure mechanisms, explain how they are observed, how they are modeled, and how they are eliminated.
This course will offer a variety of video demonstrations of analysis techniques, so the participants can get an understanding of the types of results they might expect to see with their equipment.
Participants will be able to identify the steps and create a basic qualification process for semiconductor devices.
Participants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

REGISTER HERE

embedded world 2026
2026-03-10 - 2026-03-12 | Exhibition Centre Nuremberg, Exhibition Centre Nuremberg, Messezentrum 1, Nürnberg, 90471, Germany
Global platform for the embedded community
The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations. It offers unprecedented insight into the world of embedded systems, from components and modules to operating systems, hardware and software design, M2M communication, services, and various issues related to complex system design.
Its expertise and sharp focus on technologies, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers, system architects, product managers and technical management.

The No. 1 hub for the international embedded community

As the global platform and the industry place to meet for the embedded community, embedded world attracts the top experts, key players and industry associations from all over the world.
Become part of the community and use THE industry platform to network and make valuable business contacts!

REGISTER HERE

OFC 2026
2026-03-15 - 2026-03-19 | Los Angeles Convention Center, 1201 S Figueroa St, Los Angeles, 90015
Explore the Ever-Expanding Optical Networking and Communications Industry
Plenary Session
Esteemed industry luminaries from Coherent, NVIDIA and Tesat-Spacecom will headline the event Tuesday, 17 March. These distinguished speakers will explore cutting-edge technologies, and provide invaluable insights into the evolving landscape of optical networking and communications. Learn more.
The Exhibition
The exhibition features more than 700 industry-leading companies representing the entire ecosystem of optical networking and communications. At OFC, attendees have the opportunity to explore groundbreaking technologies, innovative optical networking solutions, specialty fiber products, optical components, devices, systems, test equipment and software.
As a global event, OFC provides startups with the opportunity to debut while industry leaders set the pace for the future. It includes unveiling pioneering trends that will define the industry’s trajectory and offer solutions to critical global issues such as quantum networking, artificial intelligence (AI), space optics and data center connectivity. View the exhibition floorplan.
Theater Programs
The business of networking-focused programming provides valuable insights into current market trends and emerging technologies. Market Watch, Network Operator Summit and the Data Center Summit offer perspectives from industry leaders and experts in the field, highlighting the industry’s current environment and its future. View the theater program listings.
The Conference
OFC’s technical conference has something for everyone. From interactive workshops to symposia, from special sessions to tutorials. OFC offers an array of industry discussions around hot topics like generative AI and ML for optical networking, subsea networks, data center architectures, space optics, quantum communications and more.
There has been a notable emphasis on energy efficiency to address the escalating power consumption challenges in data centers, particularly due to the increased capacity needs and the expansion of AI-driven applications. Look for special sessions, workshops, tutorials and invited speaker discussions that explore innovative technologies such as linear drive pluggable optics (LPO), co-packaged optics (CPO), optical switching and other emerging solutions aimed at reducing power consumption in optical interfaces within the network. View the conference program listings.
Online Access to Content
OFC is held in-person but offers on-demand content at the conclusion of the conference. All technical program sessions will be available on-demand to Full Conference registrants. View the OFC archives.
Future Dates
07 – 11 March 2027 | Los Angeles Convention Center | Los Angeles, California, USA
26 – 30 March 2028 | Los Angeles Convention Center | Los Angeles, California, USA
REGISTER HERE

Semitracks Course: EOS, ESD and How to Differentiate
2026-03-16 - 2026-03-17 | Munich, Germany, Munich, Germany
Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the field failures observed in the electronics industry. Although EOS and ESD damage can at times look quite similar to each other, the source each and the solution can be quite different. Therefore, it is important to be able to distinguish between the two mechanisms. The semiconductor industry needs knowledgeable engineers and scientists to understand these issues. EOS, ESD and How to Differentiate is a 2-day course that offers detailed instruction on EOS, ESD and how to distinguish between them. This course is designed for every manager, engineer, and technician concerned with EOS, ESD, analyzing field returns, determining impact, and developing mitigation techniques.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what constitutes good EOS and ESD design, how to recognize devices that can reduce EOS and ESD susceptibility, and how to design new EOS and ESD structures for a variety of technologies. This skill-building series is divided into five segments:

Overview of the EOS Failure Mechanism. Participants will learn the fundamentals of EOS, the physics behind overstress conditions, sources of EOS, test equipment, and the results of failure.
Overview of the ESD Failure Mechanism. Participants will learn the fundamentals of ESD, the physics behind static generation and discharge, test equipment, test protocols, and the results of failure.
ESD Circuit Design Issues. Participants will learn how designers develop circuits to protect against ESD damage. This includes MOSFETs, diodes, off-chip driver circuits, receiver circuits, and power clamps.
How to Differentiate. Participants will learn how to tell the difference between EOS and ESD. They will learn how to simulate damage and interpret pulse widths, amplitudes and polarity.
Resolving EOS and ESD on the Manufacturing Floor. Participants will see a number of common problems and their origins.

Course Objectives

This course will provide participants with an in-depth understanding of electrical overstress, the models used for EOS, and the manifestation of the mechanism.
Participants will be able to understand the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today’s components.
This course will identify the major issues associated with ESD, explain how they occur, how they are modeled, and how they are mitigated.
Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
Participants will be able to distinguish between EOS and ESD when performing a failure analysis.
Participants will be able to estimate a pulse width, pulse amplitude, and determine the polarity of an EOS or ESD event.
Participants will see examples of common problems that result in EOS and ESD in the manufacturing environment.

REGISTER HERE
