SemiWiki

Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
2026-01-28 10:00 - 11:00 (America/Los_Angeles) | Online
In this webinar, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks.
We will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout.
We will show you how these tools work on real designs as well.
WHO SHOULD ATTEND THIS WEBINAR?
If you are designing chips to deploy in networked environments, you need to understand the risks ahead and how to minimize them.
If you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions.
SPEAKERS
Beau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies
Dr. Paul Calzada will take you through a live demonstration of CODAx, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions.
* This webinar is in partnership with SemiWiki and Caspia Technologies
REGISTER HERE

2026 IEEE International Solid-State Circuits Conference (ISSCC)
2026-02-15 - 2026-02-19 | San Francisco Marriott Marquis, San Francisco Marriott Marquis, 780 Mission Street, San Francisco, CA, 94103, United States
About ISSCC
The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts.
What’s New

Download the ISSCC 2026 Plenary/Educational Events Flyer
The ISSCC 2026 paper submission site is now open
Download the ISSCC 2026 Call for Papers

REGISTER HERE

Chiplet Summit 2026
2026-02-17 - 2026-02-19 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
All the Solutions for Developing Chiplets
2025 Keynote Addresses from Industry Leaders:
Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne
2025’s Main Topics Included:
AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries
signup to be a 2026 SPONSOR / Exhibitor
REGISTER HERE

Wafer-Level Packaging Symposium 2026
2026-02-18 - 2026-02-20 | Hyatt Regency San Francisco Airport, 1333 Bayshore Highway, Burlingame, CA, 94010, United States
Formatting Advanced Packaging for the Next Generation
The evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package technologies beyond conventional limits. The Wafer-Level Packaging Symposium will bring together the foremost experts in the semiconductor industry to examine all aspects of wafer and panel-level packaging, 3D device packaging, advanced manufacturing, and testing technologies. Positioned at the forefront of packaging technology evolution, this conference offers global attendees the chance to engage with the latest technological and business trends in the heart of Silicon Valley.
REGISTER HERE

Semitracks Course: Defect-Based Testing
2026-02-19 - 2026-02-20 | Munich, Germany, Munich, Germany
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior, fault models, and test techniques. This course is a must for every manager, engineer, and technician working in IC test, IC design, or supplying test hardware and software tools to the industry.
By focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior, participants will learn how to design, write, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about defect-based testing. This skill-building series is divided into four segments:

Electrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits, resistive vias, shorts, and transistor variations affect the electrical behavior of the individual transistor, as well as gate elements and larger blocks.
Fault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models, including IDDQ testing, at-speed testing, and delay testing.
Production Test Methods. Participants will learn about standard digital testing, SAF testing, IDDQ, timing, low voltage tests, and other types of stress tests. They will explore the strengths and weaknesses of each test type.
The Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.

Course Objectives

This course will provide participants with an in-depth understanding of defect-based testing and its technical issues.
Participants will understand the basic concepts of test economics, yield, test time, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.
This course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.
This course will offer the opportunity to discuss specific test problems with our expert instructors.
Participants will be able to identify basic and advanced principles for defect-based test.
Participants will understand the difficulties in extending IDDQ testing to leading edge products, and how to overcome some of these limitations.
Participants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.
This course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.
Participants will learn what tools are available today to implement defect-based testing.

REGISTER HERE

SPIE Advanced Lithography + Patterning 2026
2026-02-22 - 2026-02-26 | San Jose McEnery Convention Center, San José McEnery Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
From materials to metrology: pushing the limits of lithography
Share your research, challenges, and breakthroughs at this leading semiconductor conference in San Jose
Submit your abstract and connect with leading researchers advancing solutions in optical lithography, EUVL, patterning technologies, metrology, and process integration for semiconductor manufacturing and related applications.
Call for papers is now open.
REGISTER HERE

2026 Florida Semiconductor Summit
2026-02-23 - 2026-02-25 | Rosen Shingle Creek, Rosen Shingle Creek, 9939 Universal Blvd, Orlando, FL, 32819, United States
FSI presents the 4th annual Florida Semiconductor Summit in 2026. Join industry leaders, innovators, and exhibitioners as we explore groundbreaking developments and the evolving future of semiconductor manufacturing in Florida.
You’re invited to the 2026 Florida Semiconductor Summit! From February 23rd – 25th, 2026, the Florida Semiconductor Institute is hosting the fourth annual Florida Semiconductor Summit at the Rosen Shingle Creek. This year’s summit theme is “Semiconductor Manufacturing in Florida: Power. Progress. Possibilities.” This summit offers a unique opportunity to connect with industry leaders, explore cutting-edge advancements, and delve into the evolving role of semiconductor manufacturing in the state of Florida.
What Makes this Year’s Summit the Biggest Yet?
This year, we are taking the summit to the next level! Not only are we bringing together industry leaders from top CEOs to leading academics, we are bringing together rising startups and industry pioneers who are shaping the future of semiconductor technology in our first ever interactive exposition hall. This is your chance to connect with key decision-makers, gain insights from cutting-edge research, and explore new business opportunities in one of Florida’s fastest-growing sectors. The summit offers invaluable networking, knowledge-sharing, and a front-row seat to innovations that will have deep impacts on the state of Florida. Don’t miss out, register today!
REGISTER HERE

Semitracks Course: Wafer Fab Processing
2026-02-23 - 2026-02-26 | Munich, Germany, Munich, Germany
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is a 4-day course that offers an in-depth look into the semiconductor manufacturing process, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique, and we delve into the current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.
By focusing on the basics of each processing step and the issues surrounding them, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about the semiconductor industry. This skill-building series is divided into three segments:

Basic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. Participants will learn the fundamentals of each processing step and why they are used in the industry today.
The Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants will learn how each technique has evolved for use in previous and current generation ICs.
Current Issues in Wafer Fab Processing. Participants will learn how many processing steps are increasingly constrained by physics and materials science. They will also learn about the impact of using new materials in the fabrication process, and how those materials may create problems for the manufacturers in the future.

This course is a must for every manager, engineer, and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

Course Objectives

This course will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.
Participants will understand the basic concepts behind the fundamental wafer fab processing steps.
This course will identify the key issues related to each of the processing techniques, and their impact on the continued scaling of the semiconductor industry.
This course will offer a wide variety of sample problems that participants will work to help them gain knowledge of the fundamentals of wafer fab processing.
Participants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition, ion implantation, lithography, and etching.
Participants will understand how processing, reliability, power consumption and device performance are interrelated.
Participants will be able to make decisions about how to construct and evaluate processing steps for CMOS, BiCMOS, and bipolar technologies.

REGISTER HERE

FLEX 2026 - Technology Summit
2026-02-24 - 2026-02-26 | The WIGWAM, The Wigwam, 300 E Wigwam Blvd, Litchfield Park, AZ, 85340, United States
FLEX 2026 | TECHNOLOGY SUMMIT | FEBRUARY 24-26, 2026
THE WIGWAM ARIZONA RESORT | PHOENIX, AZ
A 25th Anniversary Celebration
Escape the winter and celebrate 25 years of innovation with us at The Wigwam Arizona Resort in Phoenix, AZ.

FLEX—Technology Summit is a vibrant networking event designed to foster community building. Connect with like-minded professionals, share ideas, and forge lasting relationships that will drive the industry forward.
At FLEX, you’ll experience high-quality technical sessions led by industry-leading speakers who are at the forefront of their fields. Sessions include topics on wearable and harsh environment technologies, heterogeneous integration and advanced packaging, flexible hybrid electronics, printed electronics, additive manufacturing, integrated photonics, flexible displays, digital twins, artificial intelligence, and manufacturing. Additionally, you’ll gain valuable business insights and market trends that provide a comprehensive view of the state of the industry.
Explore the solution zone to see cutting-edge technologies and connect with innovations shaping the future. Don’t miss this chance to stay ahead in a rapidly evolving tech landscape.
REGISTER HERE

Semitracks Course: Failure and Yield Analysis
2026-03-02 - 2026-03-05 | Munich, Germany, Munich, Germany
Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. Failure and Yield Analysis is a 4-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure. This course is designed for every manager, engineer, and technician working in the semiconductor field, using semiconductor components or supplying tools to the industry.
By focusing on a Do It Right the First Time approach to the analysis, participants will learn the appropriate methodology to successfully locate defects, characterize them, and determine the root cause of failure.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what tools and techniques should be applied, and when they should be applied. This skill-building series is divided into three segments:

The Process of Failure and Yield Analysis. Participants will learn to recognize correct philosophical principles that lead to a successful analysis. This includes concepts like destructive vs. non-destructive techniques, fast techniques vs. brute force techniques, and correct verification.
The Tools and Techniques. Participants will learn the strengths and weaknesses of a variety of tools used for analysis, including electrical testing techniques, package analysis tools, light emission, electron beam tools, optical beam tools, decapping and sample preparation, and surface science tools.
Case Histories. Participants will identify how to use their knowledge through the case histories. They will learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed.

Course Objectives

This course will provide participants with an in-depth understanding of the tools, techniques and processes used in failure and yield analysis.
Participants will be able to determine how to proceed with a submitted request for analysis, ensuring that the analysis is done with the greatest probability of success.
This course will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.
This course will offer a wide variety of video demonstrations of analysis techniques, so the analyst can get an understanding of the types of results they might expect to see with their equipment.
Participants will be able to identify basic technology features on semiconductor devices.
Participants will be able to identify a variety of different failure mechanisms and how they manifest themselves.
Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

REGISTER HERE

DVCON U.S. 2026
2026-03-02 - 2026-03-05 | Hyatt Regency Hotel, Santa Clara, CA, Santa Clara, CA, United States
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well as general purpose languages such as C, C++, Python, PERL and Tcl. Tools and methodologies include the use of artificial intelligence, machine learning, open-source software, hardware and architecture, testbench automation, hardware-assisted verification, hardware/software co-verification, formal verification, functional safety and security, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP-based SoC design methods, reference flows and Mixed Signal design and verification.
REGISTER HERE

MWC 2026
2026-03-02 - 2026-03-05 | Fira Gran Via, Barcelona, Fira Gran Via, Av. Joan Carles I, 64, Barcelona, 08908, Spain
Making way for The IQ Era

Much can happen in a year within our ecosystem of innovation and connectivity. As we build on the success of MWC25 and engage with MWC26 to activate a new theme – The IQ Era – the world is already shifting to greater heights of digital awareness.
In this new age of intelligence, the way to a better future is through smarter connection: human ideas leading technology, commercial impact and societal progress. MWC is where leaders of nations, business and technology assemble, and collective knowledge collaborates – make your insight count in The IQ Era.
Why attend MWC Barcelona?
From eye-opening innovation to mind-expanding ideas, global policy to lasting partnerships, it all starts here. Whether you’re a key player in the connectivity ecosystem, adjacent industries or the wider world of tech, you’ll find all you need and more at MWC.

REGISTER HERE

Semitracks Course: Semiconductor Reliability and Product Qualification
2026-03-09 - 2026-03-12 | Munich, Germany, Munich, Germany
Product reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past, reliability meant discovering, characterizing and modeling failure mechanisms, and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability; assessing the impact of new materials; dealing with limited margins, and other factors. This requires information on subjects like: statistics, testing, technology, processing, materials science, chemistry, and customer expectations. While customers expect high reliability levels, incorrect testing, calculations, and qualification procedures can severely impact reliability. Semiconductor Reliability and Product Qualification is a 4-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and qualification. This course is designed for every manager, engineer, and technician concerned with reliability in the semiconductor field, qualifying semiconductor components, or supplying tools to the industry.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what failure mechanisms might occur, and how to test for them, develop models for them, and eliminate them from the product. This skill building series is divided into four segments:

Overview of Reliability and Statistics. Participants will learn the fundamentals of statistics, sample sizes, distributions and their parameters.
Failure Mechanisms. Participants will learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die and at the package level. These include: time-dependent dielectric breakdown, hot carrier degradation, electromigration, stress-induced voiding, moisture, corrosion, contamination, thermomechanical effects, interfacial fatigue, and others.
Qualification Principles. Participants will learn how test structures can be designed to help test for a particular failure mechanism.
Test Strategies. Participants will learn about the JEDEC test standards, how to design screening tests, and how to perform burn-in testing effectively.

Course Objectives

This course will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today’s high reliability components.
Participants will be able to gather data, determine how best to plot the data and make inferences from that data.
This course will identify the major failure mechanisms, explain how they are observed, how they are modeled, and how they are eliminated.
This course will offer a variety of video demonstrations of analysis techniques, so the participants can get an understanding of the types of results they might expect to see with their equipment.
Participants will be able to identify the steps and create a basic qualification process for semiconductor devices.
Participants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

REGISTER HERE

embedded world 2026
2026-03-10 - 2026-03-12 | Exhibition Centre Nuremberg, Exhibition Centre Nuremberg, Messezentrum 1, Nürnberg, 90471, Germany
Global platform for the embedded community
The embedded world Exhibition&Conference provides a global platform and a place to meet for the entire embedded community, including leading experts, key players and industry associations. It offers unprecedented insight into the world of embedded systems, from components and modules to operating systems, hardware and software design, M2M communication, services, and various issues related to complex system design.
Its expertise and sharp focus on technologies, processes and future-oriented products make it unparalleled in international comparisons – and THE must-attend event for developers, system architects, product managers and technical management.

The No. 1 hub for the international embedded community

As the global platform and the industry place to meet for the embedded community, embedded world attracts the top experts, key players and industry associations from all over the world.
Become part of the community and use THE industry platform to network and make valuable business contacts!

REGISTER HERE

OFC 2026
2026-03-15 - 2026-03-19 | Los Angeles Convention Center, 1201 S Figueroa St, Los Angeles, 90015
Explore the Ever-Expanding Optical Networking and Communications Industry
Plenary Session
Esteemed industry luminaries from Coherent, NVIDIA and Tesat-Spacecom will headline the event Tuesday, 17 March. These distinguished speakers will explore cutting-edge technologies, and provide invaluable insights into the evolving landscape of optical networking and communications. Learn more.
The Exhibition
The exhibition features more than 700 industry-leading companies representing the entire ecosystem of optical networking and communications. At OFC, attendees have the opportunity to explore groundbreaking technologies, innovative optical networking solutions, specialty fiber products, optical components, devices, systems, test equipment and software.
As a global event, OFC provides startups with the opportunity to debut while industry leaders set the pace for the future. It includes unveiling pioneering trends that will define the industry’s trajectory and offer solutions to critical global issues such as quantum networking, artificial intelligence (AI), space optics and data center connectivity. View the exhibition floorplan.
Theater Programs
The business of networking-focused programming provides valuable insights into current market trends and emerging technologies. Market Watch, Network Operator Summit and the Data Center Summit offer perspectives from industry leaders and experts in the field, highlighting the industry’s current environment and its future. View the theater program listings.
The Conference
OFC’s technical conference has something for everyone. From interactive workshops to symposia, from special sessions to tutorials. OFC offers an array of industry discussions around hot topics like generative AI and ML for optical networking, subsea networks, data center architectures, space optics, quantum communications and more.
There has been a notable emphasis on energy efficiency to address the escalating power consumption challenges in data centers, particularly due to the increased capacity needs and the expansion of AI-driven applications. Look for special sessions, workshops, tutorials and invited speaker discussions that explore innovative technologies such as linear drive pluggable optics (LPO), co-packaged optics (CPO), optical switching and other emerging solutions aimed at reducing power consumption in optical interfaces within the network. View the conference program listings.
Online Access to Content
OFC is held in-person but offers on-demand content at the conclusion of the conference. All technical program sessions will be available on-demand to Full Conference registrants. View the OFC archives.
Future Dates
07 – 11 March 2027 | Los Angeles Convention Center | Los Angeles, California, USA
26 – 30 March 2028 | Los Angeles Convention Center | Los Angeles, California, USA
REGISTER HERE

Semitracks Course: EOS, ESD and How to Differentiate
2026-03-16 - 2026-03-17 | Munich, Germany, Munich, Germany
Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the field failures observed in the electronics industry. Although EOS and ESD damage can at times look quite similar to each other, the source each and the solution can be quite different. Therefore, it is important to be able to distinguish between the two mechanisms. The semiconductor industry needs knowledgeable engineers and scientists to understand these issues. EOS, ESD and How to Differentiate is a 2-day course that offers detailed instruction on EOS, ESD and how to distinguish between them. This course is designed for every manager, engineer, and technician concerned with EOS, ESD, analyzing field returns, determining impact, and developing mitigation techniques.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what constitutes good EOS and ESD design, how to recognize devices that can reduce EOS and ESD susceptibility, and how to design new EOS and ESD structures for a variety of technologies. This skill-building series is divided into five segments:

Overview of the EOS Failure Mechanism. Participants will learn the fundamentals of EOS, the physics behind overstress conditions, sources of EOS, test equipment, and the results of failure.
Overview of the ESD Failure Mechanism. Participants will learn the fundamentals of ESD, the physics behind static generation and discharge, test equipment, test protocols, and the results of failure.
ESD Circuit Design Issues. Participants will learn how designers develop circuits to protect against ESD damage. This includes MOSFETs, diodes, off-chip driver circuits, receiver circuits, and power clamps.
How to Differentiate. Participants will learn how to tell the difference between EOS and ESD. They will learn how to simulate damage and interpret pulse widths, amplitudes and polarity.
Resolving EOS and ESD on the Manufacturing Floor. Participants will see a number of common problems and their origins.

Course Objectives

This course will provide participants with an in-depth understanding of electrical overstress, the models used for EOS, and the manifestation of the mechanism.
Participants will be able to understand the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today’s components.
This course will identify the major issues associated with ESD, explain how they occur, how they are modeled, and how they are mitigated.
Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
Participants will be able to distinguish between EOS and ESD when performing a failure analysis.
Participants will be able to estimate a pulse width, pulse amplitude, and determine the polarity of an EOS or ESD event.
Participants will see examples of common problems that result in EOS and ESD in the manufacturing environment.

REGISTER HERE

IRPS 2026
2026-03-22 - 2026-03-26 | Loews Ventana Canyon Resort, Loews Ventana Canyon Resort, 7000 N Resort Dr, Tuscon, AZ, 85750, United States
About IRPS
For over 60 years, IRPS has been the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all other parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic systems through an improved understanding of both the physics of failure as well as the application environment.
IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.
IRPS 2026 focus topics:

New materials: 2D transition metal dichalcogenides (TMDs), (semi)conducting oxides (IGZO, ITO, IWO, InOx, others), (anti)ferroelectrics, low-k dielectrics, reliability of capacitors, junctions, FETs
3D packaging and heterogeneous integration: Reliability of 3D, enhanced 2D, chiplets, Si bridge, interposer, RDL technology, hybrid bonding, micro-bump, Cu-pillar and other interconnects
Data Center Reliability: Emerging trends in Reliability/Availability/Serviceability, silent data corruption, reliability at scale, AI and HPC workloads, On-chip telemetry, thermals, SER

REGISTER HERE

MSEC 2026
2026-03-31 - 2026-04-02 | Hyatt Regency Boston / Cambridge, Hyatt Regency Boston / Cambridge, 575 Memorial Dr, Cambridge, MA, 02139, United States
SENSORIZATION: ENABLING A NEW INTELLIGENCE
The MEMS and Sensors Executive Conference 2024 is designed for senior executives across the MEMS and sensors supply chain and adjacent industries. Industry economic, business updates will be covered from different aspects of the ecosystem, together with forward-looking strategic and technology trends. The opportunities and challenges brought about by key technologies in bio-medical/MEMS healthcare, generative AI, positioning navigation and timing and sustainability will be explored. The growth in existing and emerging MEMS and sensors markets, together with the resulting new components, software, and systems needs, will also be discussed. The usual networking and deal making opportunities will be a key feature as usual.
Get a deep dive on—

Bio-Medical/MEMS Healthcare
Generative AI
Positioning, Navigation and Timing
Automotive
Testing
Machine Learning ML
Sustainability (smart buildings, spaces, cities, and agriculture)

WHO SHOULD ATTEND?
CEO ● Chairmen ● Presidents ● Senior Executives ● Executive Vice Presidents ● CTO ● Startup Founders ● Financial Analysts ● Market Researchers ● Consulting Firms
REGISTER HERE

SPIE Photonics Europe 2026
2026-04-12 - 2026-04-16 | Palais de la Musique et des Congrès, Palais de la Musique et des Congrès, Place de Bordeaux, Strasbourg, 67082, France
Make plans to share your work with other experts in April 2026

Present your research at the only cross-disciplinary event highlighting compelling optics and photonics technologies—from digital optics to quantum technologies to optical imaging, sensing, and metrology. Additional topics include THz photonics, 3D printed optics, photonic glasses, photosensitive materials, and biophotonics.
Call for papers is now open
SPIE Optical Systems Design is again co-located at SPIE Photonics Europe.

REGISTER HERE

DATE 2026
2026-04-20 - 2026-04-22 | Palazzo della Gran Guardia, Palazzo della Gran Guardia, Piazza Brà, Verona, 37121, Italy
Design, Automation and Test in Europe Conference |
The European Event for Electronic System Design & Test
Call for Papers

The DATE conference is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test, and manufacturing of electronic circuits and systems. DATE places a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware, and embedded systems, as well as embedded software.
The three-day event consists of a conference with regular papers, extended abstracts, and late breaking results, complemented by timely keynotes, special days, focus sessions, embedded tutorials, half-day workshops, and multi-partner project sessions. The event will also host the Young People Programme fostering networking and exchanges of information on relevant issues, recent research outcomes, and career opportunities for junior researchers. Poster-supported live interactions and pre-recorded videos are available to complement all research paper presentations before, during, and after the conference.
DATE 2026 is the 29th edition of an event that has always been the place for researchers, young professionals, and industrial partners to meet, present their research, and discuss current developments and upcoming trends, with high emphasis on social interaction.
Conference Scope
The conference addresses all aspects of research into technologies for electronic and systems engineering. It covers the design process, test, and tools for design automation of electronic products, ranging from integrated circuits to distributed large-scale systems. This domain includes both hardware and embedded software design issues. The conference scope also includes the specification of design requirements and new architectures for challenging application fields such as sustainable computing, smart societies and digital wellness, secure systems, autonomous systems and smart industry, and state-of-the-art applications of artificial intelligence. Engineers, scientists, and researchers involved in innovative industrial designs are particularly encouraged to submit papers to foster feedback ranging from design to research aspects.
Conference Sponsors
The event is sponsored by the European Design and Automation Association (EDAA), the Electronic System Design Alliance (ESDA), the IEEE Council on Electronic Design Automation (IEEE CEDA) and the ACM Special Interest Group on Design Automation (ACM SIGDA).
In cooperation with IEEE Computer Society Test Technology Technical Community (TTTC), IEEE Solid-State Circuits Society (SSCS) and IEEE Computer Society (IEEE CS).
Conference Committees
The conference leverages the support of multiple committees to support its organisation. The DATE Sponsors Committee supervises the overall structure and operations of the conference; the Executive Committee designs and implement the yearly programme of the conference, and the Technical Programme Committee is dedicated to develop reviews and select the research manuscripts to be published at the conference.

DATE Sponsors Committee (DSC)
DATE Executive Committee (DEC)
Technical Programme Committee (TPC)

REGISTER HERE

Embedded Vision Summit 2026
2026-05-11 - 2026-05-13 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
The premier conference for innovators incorporating computer vision and AI in products
The 2025 Summit has now concluded. Join us May 11-13, 2026!

Attend an Immersive Experience

At the premier conference for innovators incorporating computer vision and AI into products

Join 1,400+ product and application developers, business leaders, investors and customers—all focused on perceptual AI at the edge.
Special features and Summit themes include:

80+ sessions on embedded vision and deep learning techniques, technologies, tools and opportunities, including formats like: presentations, case studies and panel discussions
Multiple expert sessions on deep learning for vision, 3D perception and low-power vision implementation and much more
Keynote presentations by industry luminaries
Four tracks tailored for engineers and business executives, newcomers and experts
Practical sessions to help you create visually intelligent products and gain know-how about computer vision
Edge AI Deep Dive Day filled with in-depth learning from top technology suppliers
An intensive three-hour training session designed to introduce the latest techniques in vision-language models (VLMs) and their integration with traditional computer vision methods
Case studies from leading innovators
Learn from fast-paced panel discussions presenting an array of viewpoints
Ability to see technology in action with live demos of the latest enabling technologies and dig deep into the practical applications and techniques of computer vision and AI

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ASMC 2026
2026-05-11 - 2026-05-14 | Hilton Albany, 40 Lodge St, Albany, NY, 12207, United States
ASMC brings together manufacturers, equipment and materials suppliers, and academia to solve manufacturing challenges with innovative strategies and methodologies.

View the 2025 Agenda

Advancing Semiconductor Manufacturing Excellence
ASMC is the leading international technical conference for discussing solutions that improve the collective manufacturing expertise of the semiconductor industry. Solving the challenges presented by semiconductor manufacturing is a combined effort by device makers, equipment and materials suppliers, and academics. ASMC provides an unparalleled platform for semiconductor professionals to network and learn the latest in the practical application of advanced manufacturing strategies and methodologies. Technical presentations at ASMC highlight industry innovations with specific results and select ASMC manuscripts are published in the ASMC Special Section of IEEE Transactions on Semiconductor Manufacturing.
The ASMC Committee is composed of industry professionals representing the microelectronics supply chain. All papers presented at the conference are peer-reviewed by the ASMC Technical Committee.
WHO SHOULD ATTEND

Academia
Chief Technology Officers
Fab Managers
Equipment Manufacturers
IC Manufacturers
Materials Suppliers
Operations Managers
Process Engineers
Product Managers
Technical Experts

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DVCon China 2026
2026-05-13 08:00 - 17:00 | Shanghai Renaissance Pudong Hotel, Renaissance Shanghai Pudong, 719 Yingchun Rd,, Pudong, Shanghai, 201204, China
Hello everyone! Welcome to the 2026 DvCon China Conference! As the chair of this conference, l am truly honored to be here with all of you. lt’s exciting to gather together and discuss the latest trends and cutting-edge technologies in the field of design verification.
In recent years, we’ve seen tremendous growth in China’s chip development across various sectors, particularly in critical areas like CPUs, GPUs, artificial intelligence, automotive electronics, communications, and the Internet of Things (loT). lt’s inspiring to witness the rapid rise of domestic companies in these fields, which not only drives technological advancement but also enhances our overall market competitiveness.
About DVCon China
DVCon China is a technical conference in China targeting the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Hosted by Accellera Systems Initiative, the format of DVCon China is similar to the successful DVCon United States conference held for over 20 years in the Silicon Valley.
In order to boost the interest, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in China, this highly technical conference is organized to invite industry experts to learn and share best practices on:
1. The application of system-level design and verification languages such as SystemC, SystemVerilog or e 2.The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL) 3.Verification methodologies based on the Universal Verification Methodology (UVM)
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VOICE 2026
2026-05-18 - 2026-05-20 | Scottsdale, Arizona, Scottsdale, AZ, United States
VOICE is a developer conference, created by test engineers for test engineers.

Each year, the VOICE Developer Conference unites semiconductor test professionals representing the world’s leading integrated device manufacturers (IDMs), foundries, fabless semiconductor companies and outsourced semiconductor assembly and test (OSAT) providers to exchange information about the latest technology advancements, express new ideas, share best practices and network with one another.

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COMPUTEX Taipei 2026
2026-06-02 - 2026-06-05 | Taipei Nangang Exhibition Center, Taipei Nangang Exhibition Center, No. 1, Jingmao 2nd Rd, Taipei City, Nangang District, 115, Taiwan
Main Themes
COMPUTEX is a leading global exhibition focused on AIoT and startups.
The expo will continue with the position of “AI Next”,
featuring the latest tech trends: AI & Robotics, Next-Gen Tech, and Future Mobility.
Recognized for its adaptability to industry changes.
It has established itself as a premier platform for showcasing technological innovations.
About COMPUTEX

Established in 1981, COMPUTEX TAIPEI (also called COMPUTEX) is the leading global ICT and IoT show with a complete supply chain and ecosystems.
Co-organized by the Taiwan External Trade Development Council (TAITRA) and Taipei Computer Association (TCA), COMPUTEX, based upon Taiwan’s complete ICT clusters, covers the whole spectrum of ICT industry, from established brands to startups and from ICT supply chain to IoT ecosystems.
With strong R&D and manufacturing capabilities and IPR protection, Taiwan is a strategic destination for foreign companies and investors looking for partners in global technology ecosystems

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IMS2026
2026-06-07 - 2026-06-12 | Boston, MA, Boston, MA, United States
Welcome to IMS2026

The IEEE International MTT Symposia (IMS) (www.ims-ieee.org) is the world’s premier RF/microwave technical conference and industry exhibition. Attendees will appreciate that IMS2026 has been refreshed with the technical content reorganized, and new branding, new website, and new mobile app launched.
IMS2026 kicks off with the IEEE MTT-S RF Integrated Circuits (RFIC) Symposium, then introduces two new symposia formed out of traditional IMS technical content, the IEEE MTT-S RF Technology & Techniques (RFTT) Symposium and the IEEE MTT-S RF Systems & Applications (RFSA) Symposium, before concluding the week with the ARFTG Microwave Measurement Conference.

A Week of Opportunities
In historic Boston, IMS2026 kicks off with the IEEE MTT-S RF Integrated Circuits (RFIC) Symposium, then introduces two new symposia formed out of traditional IMS technical content, the IEEE MTT-S RF Systems & Applications (RFSA) Symposium and IEEE MTT-S RF Technology & Techniques (RFTT) Symposium, before concluding the week with the ARFTG Microwave Measurement Conference.

IMS2026 isn’t just about innovation — it’s about connection. It’s the best place to network with peers, learn from experts, uncover new opportunities, and tackle the challenges defining the future of our field. This is where the community comes together to learn about groundbreaking theories and practices, and explore cutting-edge products and services.
IMS by the Numbers

8,484 registered attendees representing 55 countries
500+ exhibiting companies, including 98 first timer exhibitors
14 Start-Up Pavilion participants
200+ education sessions

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2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
2026-06-14 - 2026-06-18 | Honolulu, Hawaii, Honolulu, HI, United States
New concepts and breakthroughs in VLSI processes and devices including Memory, Logic, I/O, and I/F (RF/Analog/MS, Imager, MEMS, etc.) – Advanced gate stack and interconnect in VLSI processes and devices – Advanced lithography and fine patternig technologies for high density VLSI – New functional devices beyond CMOS with a path for VLSI implantation – Packing of VLSI devices including 3D – system integration – Processes and devices modeling of VLSI devices – Reliability related to the above devices.
Honolulu, Hawaii, USA | Event Format : Hybrid (In-person and Virtual)
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Automobil-Elektronik Kongress 2026
2026-06-16 - 2026-06-17 | Forum am Schlosspark, Stuttgarter Str. 33, Ludwigsburg, 71638, Germany
We are excited to announce the 30th Automobil-Elektronik Kongress, set to take place on June 16 and 17, 2026 at the Forum am Schlosspark in Ludwigsburg, Germany. This prestigious technical conference will bring together industry experts, researchers, and innovators to discuss the latest advancements in automotive electronics. Join us to stay at the forefront of innovation in the automotive electronics industry and network with leading professionals in the field.
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ISC 2026
2026-06-22 - 2026-06-26 | Hamburg, Germany, Hamburg, Germany
CONFERENCE & EXHIBITION

HPC, AI, Quantum: Powering Innovation and Sustainability

ISC 2026 connects scientists, engineers, and technology leaders to explore the future of high performance computing. We will examine today’s breakthroughs in artificial intelligence, high performance computing and quantum technologies, as well as what lies ahead.
Additionally, we are committed to sustainability by promoting energy-efficient and cost-effective computing, while empowering the next-generation workforce to continue the community’s legacy of innovation.
ISC 2026 will bring together a mix of people from different backgrounds and areas of expertise to drive HPC. Whether you are just entering the field, in a mid-level position, a part of senior management, or a student, we welcome you to join our efforts to connect people and technologies.

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AI Infra Summit 2026
2026-09-15 - 2026-09-17 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
What is the AI Infra Summit?

The AI Infra Summit is the premier full-stack AI Infrastructure conference, arranged in a modular way that equally enables both enterprises and technology/solution providers to benefit from domain-specific content, all while doing business on the exhibition floor. Our 4 track event is divided into Hardware & Systems, Edge AI Infrastructure, Enterprise AI, & Datacenter Infrastructure.
The AI Infra Summit takes place Tuesday – Thursday, 15-17 September 2026.
Registration opens at 9am, Keynotes begin 10am, Exhibition Hall opens 12:30pm.
The event takes place at the Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA 95054, United States.

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