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AutoSens Europe 2025
2025-10-07 - 2025-10-09 | Palau de Congressos, Palau de Congressos, Av. de la Reina Maria Cristina, s/n, Sants-Montjuïc, Barcelona, 08004, Spain
We’re back in the vibrant city of Barcelona, bringing together experts from across the industry

From 7th-9th October 2025, we’re reuniting the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV.
With over 60 expert speakers, engaging panels, technical case studies, and exploration of 12 key themes, we delved into an exhibition with cutting-edge demos from sensor and computer vision leaders.

Why Attend?

Access to an expert community of over 500 experts and engineers
Extensive exhibition with over 50 stands showcasing the latest technology
Vehicle demos from leading Tier 1 and systems companies
High quality technical presentations from genuine experts
Thought-leader panel discussions that shape the industry’s future direction

REGISTER HERE

SEMICON West 2025
2025-10-07 - 2025-10-09 | Phoenix Convention Center, 100 N 3rd St, Phoenix, AZ, 85004, United States
SEMICON West 2025 makes its debut in Phoenix, October 7–9—positioning the city as a key hub for innovation and industry growth. This milestone event gathers global leaders across the microelectronics supply chain to explore transformative technologies, develop the future workforce, and drive strategic collaboration. Now more than ever, we are STRONGER TOGETHER.

Programs + Events
-CEO Summit/Keynotes
-Cybersecurity
-Design
-EHS & Sustainability
-Heterogeneous Integration
-Market Trends
-SEMI U Training Workshops
-SEMICON West’ern
-Smart Data/AI
-Smart Manufacturing
-Smart MedTech
-Smart Mobility
-Supply Chain
-TechTALKS
-Test Vision Symposium
-Workforce Development
-Networking Events
And More!

REGISTER HERE

it-sa Expo & Congress
2025-10-07 - 2025-10-09 | Nuremberg, Germany, Nuremburg, Germany
it-sa Expo&Congress in Nuremberg is Europe’s largest trade fair for IT security…
…and one of the most important dialogue platforms for IT security solutions.
The trade fair covers the entire range of products and services in the field of cybersecurity: hardware, software, training and consulting services as well as Security as a Service. Important topics at it-sa are cloud and mobile security, data and network security, the protection of critical infrastructures, and industrial Security.
Since 2009, it-sa Expo&Congress in Nuremberg has been the meeting place for decision-makers, experts and IT security officers from all sectors of the economy. Whether they represent industry, the service sector or public administration, the exhibitors at it-sa offer customised and individual solutions. On the exhibitor side, it-sa addresses the entire IT security market, including physical IT security. The event thus offers trade visitors a showcase of the IT security industry from Germany and abroad that is unique in Europe. Outstanding innovations by young companies in the field of cyber security will be honoured with the ATHENE Startup Award UP@it-sa.
The freely accessible lecture programme and product-neutral contributions and discussion panels from the it-sa insights series provide trade fair visitors to it-sa with the latest expertise in the industry. In addition, the congress programme Congress@it-sa, organised in cooperation with renowned associations and organisations, offers an intensive dialogue on current topics in IT security.

Welcome to the world of IT security.
REGISTER HERE

Webinar: Enabling Tomorrow’s Workloads with 1.6Tbps Ethernet
2025-10-02 12:00 - 13:00 (America/Los_Angeles) | Online
Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the need for robust pre-silicon verification has never been greater.
Join this webinar to see how the Veloce™ hardware-assisted verification platform extends support for 1.6Tbps Ethernet through its proven Ethernet Packet Generator and Monitor (EPGM). Trusted by leading enterprises worldwide, EPGM helps engineering teams validate complex SoCs, stress test performance, and accelerate time-to-market with confidence.
What you’ll learn:

Why Veloce leads in networking verification
How EPGM delivers scalable, high-performance emulation and debug
New support for 1.6Tbps Ethernet, including IEEE 802.3dj 200G/lane

Who should attend:

SoC and ASIC design engineers working on Ethernet-based products
Verification and validation teams focused on networking and HPC workloads
System architects designing next-gen data center, AI, and cloud infrastructure

Engineering managers and decision-makers seeking to accelerate verification cycles and reduce risk
Speaker

Anup Shah
Director of Product Management, Siemens Digital Industries Software

REGISTER HERE

Webinar: Why Choose PCIe 5.0 for Power, Performance, and Bandwidth at the Edge?
2025-10-02 09:00 - 10:00 | Online
Featured Speakers:

Gustavo Pimentel, Principal Product Marketing Manager, Synopsys

As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged as the optimal interconnect standard. Doubling the data rate of PCIe 4.0 while enabling lane reduction, PCIe 5.0 helps SoC designers achieve significant savings in power, area, and beachfront—critical advantages for space- and thermally-constrained environments such as ADAS, AIoT, and 5G edge devices.
In this Synopsys webinar, we will discuss how our high-performance, silicon-proven PCIe 5.0 IP enables scalable systems and energy efficiency across automotive, mobile, and edge use cases. We will explore:

Key benefits of migrating to PCIe 5.0
Architectural considerations for integrating PCIe 5.0 in edge SoCs
Low-power design techniques, including dynamic power gating
Real-world deployment examples and interoperability highlights

Join us to learn how to future-proof your SoC designs with PCIe 5.0 and meet the demands of the next wave of intelligent edge applications.

Featured Speakers

Gustavo Pimentel
Principal Product Marketing Manager, Synopsys
Gustavo is a Principal Product Marketing Manager at Synopsys, specializing in PCIe products. With 17 years of experience in embedded software, Gustavo has spent the last 8 years developing Linux device drivers for Synopsys IPs, including PCIe.

REGISTER HERE

2025 WLI WISH Conference
2025-10-01 08:00 - 17:00 | San Jose McEnery Convention Center, San José McEnery Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
Join us at WISH, GSA WLI’s premier technical conference that promises to be an inspiring celebration of innovation and empowerment. With around 1,000 attendees, including industry luminaries, visionary entrepreneurs, and brilliant university students in STEM, this event will showcase the evolving landscape of technology. Attendees can look forward to inspiring keynotes from trailblazers who are reshaping the tech world, as well as celebratory awards honoring extraordinary women who have broken the glass ceiling and those paving the way for future generations.

This is a unique opportunity to connect with like-minded professionals and forge valuable relationships that can propel your career forward. Join us in championing gender parity and celebrating the remarkable achievements of women in technology—be part of the movement transforming the industry!
REGISTER HERE

Silicon Photonics Workshop
2025-09-30 18:00 - 21:00 | 1 Hotel Copenhagen, 1 Hotel Copenhagen, Krystalgade 22 1172, Copenhagen, Denmark
Lighting the Future: Advancing Silicon Photonics for the AI Connectivity Era

Soitec is pleased to host a private workshop event in parallel of ECOC 2025, offering a forward-looking perspective on the expanding role of photonics in enabling next-generation AI architectures.

The workshop will bring together leading voices from across the value chain such as : Coherent, ST, Lightcounting, CEA Leti and Soitec.

Speaker lineup and detailed agenda will be announced early september.

Frequently asked questions

Is the event free to attend?

Yes the event is free to attend

What is the easiest way to reach the 1Hotel from the ECOC 2025 conference?

The easiest and fastest way will be to use the metro. Click on this link to get directions. It is an 11 mins metro ride.

Should I register to attend the event ?

Yes all the attendees have to register. The organizers will screen the registration and reserve the right to validate or decline any registrations.

Is there a reception following the event ?

Yes, a reception will be organized at the end of the workshop

Do you validate parking ?

No, the organizers are not validating parking

REGISTER HERE

CadenceTECHTALK: Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
2025-09-30 11:00 - 12:00 | Online
Overview

Join us for a series of expert-led webinars showcasing cutting-edge simulation and analysis tools—from RF/mmWave modeling to advanced thermal and electromagnetic solutions. While designed for a broad range of high-performance electronics applications, each session also highlights how these technologies can be adapted to meet the rigorous demands of aerospace and defense (A&D) systems.
Topics Highlights:

RF and mmWave Modeling: Discover how Modelithics’ advanced models improve accuracy and reduce risk in high-frequency A&D systems.
3D EM and Antenna Optimization: See how Cadence’s Clarity 3D Solver and Optimality Intelligent System Explorer enable fast, scalable simulation for complex RF and antenna designs.
Thermal Reliability with Cadence Celsius Studio: Explore AI-enabled thermal analysis for mission-critical electronics in extreme environments.

REGISTER HERE

Webinar: Hardware design of custom AI accelerators using High-Level Synthesis
2025-09-30 09:00 - 10:00 | Online
As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will cover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We will cover the step-by-step design and verification of the Wake Word algorithm using HLS. Not only will we be showcasing conventional HLS flows, but we are excited to share our new product Catapult AI/NN. This new product takes High-Level Synthesis and extends it to models trained in python. With this new development we will now be able to develop AI hardware even faster.
PS: Stick around till the end to learn about our hackathon. You will get the chance to have hands-on experience with using Catapult to design AI applications along with winning some pretty sweet prizes. Don’t forget bragging rights!
REGISTER HERE
Speakers:

Cameron Villone
High-Level Synthesis Technologist, Siemens EDA

Cameron Villone is a High-Level Synthesis Technologist working with the Catapult High-Level Synthesis product management and marketing team, focusing on AI hardware deployment. He previously worked as a product marketing engineer for PowerPro, Siemens’ power optimization and analysis product. He held previous roles at Texas Instruments and General Motors. Cameron studied and graduated from Rochester Institute of Technology, obtaining both a bachelor’s and master’s degree in electrical engineering, focusing on Robotics, Embedded Systems, and Computer Vision.

Russell Klein
HLS Program Director, Siemens EDA

Russell Klein is a Program Director at Siemens EDA’s (formerly Mentor Graphics) High-Level Synthesis Division focused on processor platforms. He is currently working on algorithm acceleration through the offloading of complex algorithms running as software on embedded CPUs into hardware accelerators using High-Level Synthesis. He has been with Mentor for over 25 years, holding a variety of engineering, marketing and management positions, primarily focused on the boundary between hardware and software. He holds six patents in the area of hardware/software verification and optimization. Prior to joining Mentor he worked for Synopsys, Logic Modeling, and Fairchild Semiconductor.

REGISTER HERE

IMAPS Symposium 2025
2025-09-29 - 2025-10-02 | Town & Country Resort, San Diego, 500 Hotel Cir N, San Deigo, CA, 92108, United States
September 29 – October 2, 2025
Co-located with Semiconductor thermal management
Town & Country resort
San Diego, California
The 58th International Symposium on Microelectronics is organized by the International Microelectronics Assembly and Packaging Society and held in San Diego, California. IMAPS Symposium offers one of the most robust programs for microelectronics and advanced packaging technical content. Each year, we welcome many repeat attendees as well as hundreds of first-time visitors – early career packaging professionals, those new to the industry, and students.
Our event kicks off with Professional Development Courses, followed by 3 days of technical sessions with emphasis on Advanced Package Structures (Heterogeneous Integration, HPC, AI); Advanced Interconnect, Bumping & Wirebond Technologies; RF, MEMS/Sensors, High Rel, WLCSP, Small Body FO; Enabling Materials & Advanced Equipment; and CPI, Modeling, Design, Metrology.
Conference: September 30 – October 2
Exhibition: September 30 – October 1
Professional Development Courses: September 29
All Symposium sessions will take place at the Town & Country Resort.
Organizing Committee:
General Chair: Benson Chan, Binghamton University
General Chair-elect: Karthik Dhandapani, Qualcomm
Past General Chair (2024): Tarak Railkar, Qorvo
REGISTER HERE

Semitracks Course: Failure and Yield Analysis
2025-09-29 - 2025-10-02 | Phoenix, AZ, Phoenix, AZ, United States
Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. Failure and Yield Analysis is a 4-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure. This course is designed for every manager, engineer, and technician working in the semiconductor field, using semiconductor components or supplying tools to the industry.
By focusing on a Do It Right the First Time approach to the analysis, participants will learn the appropriate methodology to successfully locate defects, characterize them, and determine the root cause of failure.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what tools and techniques should be applied, and when they should be applied. This skill-building series is divided into three segments:

The Process of Failure and Yield Analysis. Participants will learn to recognize correct philosophical principles that lead to a successful analysis. This includes concepts like destructive vs. non-destructive techniques, fast techniques vs. brute force techniques, and correct verification.
The Tools and Techniques. Participants will learn the strengths and weaknesses of a variety of tools used for analysis, including electrical testing techniques, package analysis tools, light emission, electron beam tools, optical beam tools, decapping and sample preparation, and surface science tools.
Case Histories. Participants will identify how to use their knowledge through the case histories. They will learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed.

Course Objectives

This course will provide participants with an in-depth understanding of the tools, techniques and processes used in failure and yield analysis.
Participants will be able to determine how to proceed with a submitted request for analysis, ensuring that the analysis is done with the greatest probability of success.
This course will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.
This course will offer a wide variety of video demonstrations of analysis techniques, so the analyst can get an understanding of the types of results they might expect to see with their equipment.
Participants will be able to identify basic technology features on semiconductor devices.
Participants will be able to identify a variety of different failure mechanisms and how they manifest themselves.
Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

REGISTER HERE

ECOC 2025
2025-09-28 - 2025-10-02 | Bella Center, Bella Center, Center Boulevard 5, Copenhagen, 2300, Denmark
The 51st European Conference on Optical Communication
Welcome to ECOC 2025 in Copenhagen

ECOC, the European Conference on Optical Communication, stands as Europe’s premier gathering for optical communications, holding a prominent position as one of the globe’s most significant events in this field. This conference unites pioneers and professionals from academia, research, and industry, fostering the exchange of cutting-edge discoveries and future-oriented perspectives.
At ECOC, you’ll find an optimal environment to enrich your knowledge, engage in dynamic discussions, and forge valuable connections. Its scope spans from the fundamental materials and devices enabling optical communication to the intricate systems and networks employing these technologies.
The ECOC Exhibition, in existence for nearly three decades, has evolved into Europe’s largest optical communications exhibition. It serves as a pivotal hub where industry leaders convene, making it a cornerstone for decision-makers in the fiber optic communications technology sector.

REGISTER HERE

CASPA 2025 Annual Conference and Dinner Banquet
2025-09-27 09:00 - 21:00 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
CASPA ACDB 2025 — A premier global summit uniting industry leaders, entrepreneurs, researchers, and investors to explore the future of Artificial Intelligence and Semiconductors
Theme:
🧠 “AI Ecosystem Revolution: Advancing Tomorrow’s Intelligence Together”
📌 A full-day experience featuring:
✨ Keynote Presentations
💡 Visionary Panel Discussions
🍽️ Formal Dinner Banquet
🤝 Exclusive Networking Opportunities
🎤 Keynote Speakers:
🔹 David Wang, Senior Vice President, AMD — Annual Conference Keynote
🔹 Dr. Lisa Su, CEO, AMD — Dinner Banquet Keynote
🚀 Don’t miss this unique opportunity to connect with the people, technologies, and ideas shaping the next generation of intelligent systems. click here to register
REGISTER HERE

Cloud Tech Day 2025
2025-09-25 10:00 - 14:00 | Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, CA, 95054, United States
Join industry leaders and Cadence cloud experts at this free must-attend Cloud event of the year to explore the latest cloud EDA innovations, share ideas, and grow your professional connections.
All attendees will receive a giveaway and a chance to win raffle prizes.
DATE: September 25, 2025
TIME: 10:00am – 1:45pm PDT
LOCATION: Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, CA 95054
Cloud technology is transforming EDA, enabling greater scalability, flexibility, and collaboration as design complexity rises and security concerns ease. Cadence OnCloud, built with leading foundries and partners, delivers industry-leading security, cost efficiency, and flexibility, supporting hundreds of successful tapeouts.
Check out the full agenda here.
Why this is THE Must-Attend Cloud Event of the Year!
This event is designed to empower you with the tools, insights, and strategies to stay ahead in the rapidly evolving world of EDA. Here’s what you’ll gain:

Exclusive Insights: Gain a sneak peek at new Cadence OnCloud features, including game-changing Cloud 3.0 for industry-leading cost efficiency.
Actionable Strategies: Learn how to implement an all-cloud or hybrid cloud environment to optimize your design flow and infrastructure and seamlessly transition from an evaluation to a production environment.
Live Demonstrations: See Cadence OnCloud in action and experience how effortlessly you can run your design flows in a cloud or hybrid setup.
Direct Access to Experts: Meet the R&D and business teams behind the Cadence Cloud portfolio and get your questions answered.
Networking Opportunities: Connect with industry leaders, peers, and Cadence experts to exchange ideas and grow your professional network.

Whether you’re a design/CAD engineer, CAD manager, IT manager, or business leader, this event will provide you with the knowledge and connections to transform your design processes and drive innovation.
REGISTER HERE

Webinar: Static Verification of RTL DFT Connectivity – Getting it Right the First Time!
2025-09-25 09:00 - 10:00 | Online
Featured Speakers:

Kiran Vittal, Synopsys
Ayush Goyal, Synopsys

As System-on-Chip (SoC) designs become increasingly complex, ensuring reliable Design-for-Test (DFT) connectivity at the RTL stage is more important than ever. This Synopsys webinar will demonstrate how static verification techniques, powered by TestMAX™ Advisor on the VC SpyGlass® platform, can help you address connectivity challenges efficiently and accurately. Learn how robust connectivity checks can improve design quality and streamline your verification process.
Why You Should Attend:

Discover best practices for verifying RTL DFT connectivity in modern SoC designs.
See practical demonstrations of customizable connectivity checks and advanced GUI analysis tools.
Learn how to detect both DFT and functional connectivity issues early in the design cycle.
Gain insights from Synopsys experts on leveraging static verification for faster, more reliable design closure.

Don’t miss this opportunity to enhance your verification workflow—secure your spot today!
REGISTER HERE

Featured Speakers

Kiran Vittal
Executive Director, Synopsys
Kiran Vittal is the executive director of product management for the Synopsys Design-for-Test line of business in the Product Management and Markets Group. He has 25+ years of experience in EDA and semiconductor design.

Ayush Goyal
Senior Staff R&D Engineer, Synopsys
Ayush Goyal is Senior Staff R&D Engineer in the Hardware Analytics and Test Group at Synopsys. He joined Synopsys in 2016. He has been working in the EDA industry for the last 9 years focused in the areas of software-driven automation technologies.

REGISTER HERE

Andes RISC-V CON Seoul
2025-09-24 13:00 - 17:00 | EL Tower, EL Tower, 213 Gangnam-daero, Seoul, Seocho District, Korea, Republic of
Andes RISC-V CON Seoul
REGISTER HERE

Webinar: Getting Started with the Vitis Unified IDE
2025-09-24 11:00 - 12:00 | Online
Description
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating complex workflows can feel overwhelming. The AMD Vitis™ Unified IDE simplifies the process by integrating Vitis IDE, Vitis Analyzer, and Vitis HLS into a single, structured environment. In this session, you’ll learn how to create and manage projects, build and debug applications, and utilize the Python-based command line for a more efficient workflow. Whether you are transitioning from Vitis Classic or starting fresh, this webinar will help you improve accuracy and streamline your development process.
This webinar includes a live demonstration and Q&A.
If you are unable to attend, a recording will be sent one week after the live event.
To see our complete list of webinars, visit our website: www.bltinc.com.
REGISTER HERE

Webinar: 448G PAM4: The Future of 3.2T Data Centers
2025-09-24 10:00 - 11:00 | Online
About this event
Join industry experts from NTT Innovative Devices, Lumentum, and Keysight to discuss their historic demonstration of 448g / lane signaling over PAM4 — a cross-continental collaboration that’s laying the foundation for the next generation of AI data centers and high-speed Ethernet.

Who should attend this event?
R&D engineers at network equipment manufacturers who are building high-speed interconnects and transceivers for AI-ready data centers.
REGISTER HERE

2025 TSMC Open Innovation Platform Ecosystem Forum - Santa Clara
2025-09-24 08:30 - 18:00 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM
Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event; it’s a dynamic hub where the brightest minds converge to ignite the next wave of innovation.
As the AI revolution proliferates from the data center to the edge and becomes integrated into every application, the need for high-performance and energy-efficient designs is becoming paramount. Through a series of compelling, multi-track presentations, you’ll gain a firsthand understanding of how the ecosystem is collaboratively tackling these critical design requirements.
AI is also transforming how chip and multi-die designs are done. This year, the forum will highlight how the ecosystem is harnessing the immense potential of AI in next generation of design solutions for TSMC’s advanced process and packaging technologies. Prepare to be immersed in a wealth of knowledge as industry trailblazers and TSMC’s ecosystem partners offer valuable insights into the latest breakthroughs.
The event provides a unique opportunity for you to engage with thought leaders and innovators, whether you join in-person at locations across North America, Japan, Taiwan, China, and Europe, or participate online.
Don’t miss this opportunity to connect with the leading players of semiconductor technology and be part of shaping tomorrow’s innovations, today!
NA OIP Ecosystem Forum (In-Person Event)
Date: September 24, 2025 (Wednesday)
Time: 8:30a.m. – 6:00p.m.
Venue: Santa Clara Convention Center
5001 Great America Parkway, Santa Clara, CA 95054
NA OIP Ecosystem Forum (Online VOD Event)
Date: October 9, 2025 (Thursday)
Website link to be provided in October
Learn About:

Solutions needed to address energy efficiency and other challenges impacting the next-generation AI chips and corresponding design flows and methodologies for TSMC A16™, N2, and N3 processes.
Consistent progress in design enablement and solution development for TSMC’s advanced processes including A14, TSMC A16™ and N2.
Latest advancements in design solutions on TSMC 3DFabric® chip stacking (including InFO, CoWoS®, TSMC-SoIC®, TSMC-SoW™), as well as updates on the TSMC 3DFabric Alliance.
AI-assisted design flows for 2D and 3DIC design productivity and optimization.
Design enablement technologies, IPs and solutions targeting the latest HPC, AI/ML, automotive, mobile/5G and IoT applications.
Comprehensive design solutions for specialty technologies including ultra-low power, ultra-low voltage, analog migration, RF, and mmWave.
Successful, real-life applications of design technologies, IP solutions, and cloud-based designs from TSMC’s Open Innovation Platform® Ecosystem members and TSMC customers to speed up time-to-design and time-to-market.

For more information on the TSMC OIP Ecosystem Forum, e-mail us at: tsmcevents@tsmc.com.
We look forward to seeing you at the 2025 TSMC OIP Ecosystem Forum!
REGISTER HERE

The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2025
2025-09-24 - 2025-09-26 | Maison MINATEC Congress Center, Maison MINATEC Congress Center, 3 parvis Louis Néel, Grenoble, 38054, France
The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) provides an international forum for the presentation of leading-edge research and development results in the area of process and device simulation. SISPAD is one of the longest-running conferences devoted to technology computer-aided design (TCAD) and advanced modeling of novel semiconductor devices and nano electronic structures. SISPAD2025 will be held in-person in Grenoble, France, from September 24 to 26, 2025.
A satellite workshop will be offered on the day before the main conference starts (September 23).
Details on the SISPAD 2025 technical program and workshop will be announced here as soon as they are available.
REGISTER HERE

Microelectronics UK 2025
2025-09-24 - 2025-09-25 | ExCeL London, Royal Victoria Dock, 1 Western Gateway, London, E16 1XL, United Kingdom
The Premier Event for the UK Microelectronics Industry

Join thousands of your peers at the premier event uniting the entire value chains across the microelectronics, semiconductor, photonics and embedded systems industries, uniquely showcasing the UK’s world-class expertise in R&D, design innovation, and advanced manufacturing.
Microelectronics UK is where innovation thrives, connections flourish, and trade accelerates. By bringing the world to the UK, the event empowers businesses to shape the future of microelectronics on a global stage.

Access world-class expertise and networking opportunities – all for free. Register your interest today and be the first to know when free and VIP tickets are released!

REGISTER HERE

GPDIS 2025
2025-09-23 - 2025-09-25 | Hilton Phoenix Tapatio Cliffs Resort, Hilton Phoenix Tapatio Cliffs Resort, 11111 N 7th St, Phoenix, AZ, 85020, United States
The Focus:
The Global Product Data Interoperability Summit (GPDIS) functions as a communications hub for industry principals to foster knowledge through the exchange of ideas, solutions, and methods.
It is a place to build consensus on the data, tool and process standards based on the experience of liked minded professionals.
Unlike any other conference, GPDIS represents the core data representations and delivery systems that drive our industries.
The format is vendor-neutral, but all solution providers are encouraged to demonstrate both their technologies and their success stories.
The range of process methods encompasses MBE, MBD, MBSE, CAM, Product Analysis, Support, the emerging technologies and more.
The depth of experience extends from a vibrant vendor community, through the large OEMs and engaged lower tiered suppliers, to the family manufacturing business.
2025 GPDIS Theme
The Digital Thread for Manufacturing: Digitally Transformed or a Work in Progress?
Supply chain stability is the lifeblood of any manufacturing organization. Disruptions are far reaching, slow to recover, and expensive. The news is full of stories regarding the challenges faced by multiple industries to adapt to changing conditions in the manufacturing domain and its integrated supply chain. How does the enterprise cope? The advent of digital twin / digital thread technologies and linked data across company boundaries in manufacturing has emerged as a key value proposition to streamline transactions and accelerate recovery.
Digital transformation has matured to the point where we are actively implementing digital twins, digital threads, and exploring artificial intelligence on a variety of fronts. Where is the factory in this journey? Join us as we examine the critical role manufacturing’s digital thread plays in interoperability. With a renewed focus on manufacturing, we will explore the digital thread, practical applications of linked data, and relationship of that data to the other product lifecycle domains.
We will examine this important topic and more with key insights from industry leaders and solution providers alike. Our industry leading technical discussions delivered in a multi-track format includes the standards centric, model-based domains of Engineering, Manufacturing, Supply Chain, Digital Twin/Thread, and Emergent Technology. We will also host the wildly popular MBSE Working Group in a pre-event workshop to progress the state of the art for our Systems Engineering community.
REGISTER HERE

North American Supply Chain Executive Summit (NASCES) 2025
2025-09-22 - 2025-09-24 | The Red Rock Casino Resort & Spa, The Red Rock Casino Resort & Spa, 11011 W Charleston Blvd, Las Vegas, NV, 89135, United States
The North American Supply Chain Executive Summit is a premier gathering of industry leaders, supply chain executives, and experts dedicated to exploring innovative strategies, emerging trends, and best practices in the dynamic world of supply chain management.

Join This Year’s Conversation

NASCES gathers Chief Supply Chain Officers, Chief Procurement Officers, EVPs, SVPs, VPs, and Directors of Supply Chain, Sourcing, Procurement, Transportation, Logistics, Operations, Planning, Manufacturing, Sustainability, Inventory and Fulfillment to share insights, foster innovation, and build invaluable connections. Dive into a thoughtfully curated environment that brings together today’s thought leaders, allowing you to explore new ideas and engage in meaningful discussions. Join the conversation at NASCES and be part of a community dedicated to pushing the limits of supply chain success.
REGISTER HERE

International Test Conference - ITC 2025
2025-09-21 - 2025-09-26 | Hilton San Diego Bayfront, 1 Park Blvd, San Diego, CA, 92101, United States
About ITC

International Test Conference, the cornerstone of TestWeek™ events, is the world’s premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

REGISTER HERE

European Microwave Week (EuMW 2025)
2025-09-21 - 2025-09-26 | Jaarbeurs Convention Centre, Jaarbeurs Convention Centre, Jaarbeursplein 6, Utrecht, 3521 AL, Netherlands
The 28th edition of the European Microwave Week (EuMW 2025) will come to Utrecht to continue the annual series of highly successful microwave events that started back in 1998. EuMW 2025 comprises three co-located conferences:

The European Microwave Conference (EuMC)
The European Microwave Integrated Circuits Conference (EuMIC)
The European Radar Conference (EuRAD)

In addition, EuMW 2025 includes the Forum on Defence, Security and Space, the Automotive Forum, the 6G Forum, and an extensive trade show. EuMW 2025 provides the opportunity to participate in conferences, workshops, short courses, and special events such as Women in Microwave Engineering.

The annual European Microwave Exhibition, which is by far the largest RF and microwave trade show in Europe, is held in conjunction with the conferences. The exhibition also includes a series of technical seminars and exhibitor workshops describing commercial products and processes.
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SPIE Photomask Technology + Extreme Ultraviolet Lithography 2025
2025-09-21 - 2025-09-25 | Monterey, CA, Monterey, CA, United States
Share your research and join the outstanding program for 2025

Make plans to join the premier worldwide technical meeting for photomasks, patterning, metrology, materials, inspection/repair, mask business, extreme UV lithography, and emerging technologies.
We are still accepting post-deadline abstract submissions, which are subject to chair approval.

SPIE partners with researchers, educators, and industry to advance light-based research and technologies for the betterment of the human condition.

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