SemiWiki

RISC-V Summit North America 2025
2025-10-22 - 2025-10-23 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive, data center, space, IoT, embedded and more. Each day, thousands of engineers around the world collaborate and contribute to advance RISC-V. The RISC-V community shares the technical investment and helps shape the architecture’s strategic future so everyone may create more rapidly, enjoy a new level of design freedom, and substantially reduce the cost of innovation. Anyone, anywhere can benefit from these contributions.

This October, the global RISC-V community – including technical, industry, domain, ecosystem and special interest groups who define the architecture’s specifications – will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies, as well as to network and build relationships. Come be part of the RISC-V movement.

The festivities kick off with RISC-V Member Day, where technical and industry working groups meet in person to share updates on the status of various efforts.
Next, the RISC-V Summit North America features two days of compelling technical and industry keynotes and conference sessions, paired with an expo featuring dozens of community members showcasing their the latest solutions.

It’s community-curated content, research and innovation driving the next wave of growth for RISC-V.
Learn about software, systems, development tools, security, the latest use cases in key markets and more. It’s all here.
Define the future. Build your knowledge and expertise. Grow your network. It’s all during RISC-V Summit North America. Come join us!
REGISTER HERE

Semiconductor Traceability and Provenance Workshop
2025-10-21 08:30 - 17:00 (America/Los_Angeles) | NIST Gaithersburg, NIST Gaithersburg, 100 Bureau Drive, Gaithersburg, MD, 20899, United States
The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday, October 21, 2025, at its campus in Gaithersburg, Maryland. This in-person, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain, which identified traceability as the top priority of semiconductor industry stakeholders.
As semiconductor devices grow more complex and globally distributed, the risks from counterfeit components, malicious tampering, and opaque sourcing threaten the security, reliability, and resilience of critical systems. Strengthening traceability and provenance is essential to mitigating supply chain threats, supporting national security imperatives, and addressing the grand challenges in secure microelectronics (https://nvlpubs.nist.gov/nistpubs/CHIPS/NIST.CHIPS.1000.pdf).
The workshop will convene technical leaders across the semiconductor ecosystem (e.g., hyperscalers, auto and semiconductor companies, federal agencies, academia) to address the practical challenges and opportunities for implementing traceability in semiconductor chips. This one-day event will feature plenary, panel, and interactive breakout sessions. Participants will be encouraged to collaborate and discuss key questions and topics that will identify short-term (<1 year) and longer-term (2028-2029 time frame) activities related to semiconductor traceability and provenance. The topics that will be considered include but are not limited to:

Existing solutions
Technical, operational challenges to traceability adoption
Opportunities for public-private collaboration (e.g., hyperscalers, automobile,
semiconductor companies, government agencies, academia)
Roadblocks to alignment and paths to overcoming them
Economic drivers and pilot use cases for traceability
Frameworks for joint standards development and implementation
Roadmap for collaboration and path to success

Outcomes from the workshop will include a published roadmap and post-workshop report that advances shared goals in securing semiconductor supply chains.
REGISTER HERE

SPIE Optifab 2025
2025-10-20 - 2025-10-23 | Joseph A. Floreano Rochester Riverside Convention Center, Joseph A. Floreano Rochester Riverside Convention Center, 123 East Main Street, Rochester, NY, 14604, United States
Join colleagues at the largest optical manufacturing conference and exhibition in North America

SPIE Optifab is the premier event to meet with top companies and learn about the latest optical fabrication technologies. Organized jointly by SPIE and APOMA, Optifab is the largest optical manufacturing conference and exhibition held in North America.
In 2025 the meeting will be co-located with SPIE Laser Damage in Rochester, New York.
Enjoy four days of connecting with your community

Meet suppliers at the exhibition
Hear technical presentations
Enjoy invited speakers
Get training while onsite
Enjoy networking events

We look forward to gathering these two important communities in one location.
Exhibition: 21 – 23 October 2025
Technical program: 20 – 23 October 2025

REGISTER HERE

MICRO 2025 - 58th IEEE/ACM International Symposium on Microarchitecture
2025-10-18 - 2025-10-22 | Seoul, Korea, Seoul, Korea, Republic of
The IEEE/ACM International Symposium on Microarchitecture® is the premier forum for presenting, discussing, and debating innovative microarchitecture ideas and techniques for advanced computing and communication systems. This symposium brings together researchers in fields related to microarchitecture, compilers, chips, and systems for technical exchange on traditional microarchitecture topics and emerging research areas. The MICRO community has enjoyed a close interaction between academic researchers and industrial designers, and we aim to continue this tradition at MICRO-58. In 2025, MICRO goes to Seoul, Korea.
REGISTER HERE

2025 Embedded World China
2025-10-16 - 2025-10-17 | Shanghai World Expo Exhibition and Convention Center China, 1099 Guozhan Rd, Shanghai, Pudong, 200126
Conference Profile
The embedded world China Conference will take place on October 16 and 17, 2025 at the Shanghai World Expo Exhibition and Convention Centre.
The main topics of this year’s conference are：
· Embedded Technology & Applications
· Vehicle Electronic / Electrical Architecture & Technologies
· Embedded Vision Technologies Innovation and Development Conference using Edge AI
Check the Conference brochure here.
Interested speakers for all three tracks are invited to submit their proposals to contribute to the 3rd edition of the conference with a technical presentation or paper. The embedded world China Conference 2025 calls for future-oriented technologies and solutions, best practices, new ideas and smart concepts for efficient development and lifecycle processes. The presentations will be used to initiate discussions and help other engineers and managers to benefit from shared experiences.
Experts with insight into the embedded systems industry is given an equal opportunity to participate, whether through in-depth academic discussions, technological show cases or best practice studies from research and development.
Acceptance Criteria
Papers will be selected based on the following criteria:
· novelty
· technological soundness
· technological significance
· experience of the speaker
The selection will be made by a programme committee. The members of the programme committee are independent senior engineers and researchers with excellent scientific and business experience.
REGISTER HERE

Webinar: ML-Enhanced TCAD Calibration With 10x Reduction in Time to Results
2025-10-15 17:00 - 18:00 | Online
Date: Oct 15, 2025 | 5:00 PM PST

Featured Speakers:

Saurabh Suryavanshi, Product Manager, Synopsys
Youngkwon Cho, Senior Staff Engineer, Synopsys
Dipanjan Basu, Principal Engineer, Synopsys

Calibration is an essential part of enabling TCAD products usages inside Semiconductor fab. Synopsys has been leading the development of ML-enhanced calibration that reduce the time to results by 10x while improve the quality of results. In this Synopsys Webinar, our team will provide overview of TCAD calibration and recent advances in ML-based calibration.
Why You Should Attend:

Cut TCAD calibration time and accelerate project delivery by 10x.
Overcome accuracy challenges in semiconductor manufacturing.
Streamline calibration workflows for better efficiency.

REGISTER HERE

Featured Speakers

Saurabh Suryavanshi
Product Manager, Synopsys
Saurabh is a Product Manager in the Manufacturing Solutions group at Synopsys, specializing in Digital Twin, machine learning, and GenAI technologies to accelerate semiconductor innovation. He holds a PhD in Electrical Engineering from Stanford University. Saurabh is a recognized expert with over 30 publications, multiple patents, and a strong track record of helping engineers improve productivity and reduce R&D costs.

Youngkwon Cho
Senior Staff Engineer, Synopsys
Youngkwon Cho is a Senior Staff Engineer at Synopsys, leading development of machine learning-based calibration solutions for TCAD simulation. He holds a PhD in applied physics from Ajou University and has deep expertise in optical simulation, process optimization, and AI/ML tools.

Dipanjan Basu
Principal Engineer, Synopsys
Dipanjan is a technology evangelist dedicated to enhancing semiconductor manufacturing productivity through modeling and simulation. He has extensive experience in device physics, compact modeling, and quantum transport simulation, and leads initiatives to accelerate technology development using TCAD and DTCO strategies.

REGISTER HERE

Webinar: 5 Expectations for the AI Market in 2026
2025-10-15 11:00 - 12:00 | Online
October 15, 2025 – 11:00 AM EST
October 16, 2025 – 10:00 AM JST/KST
Discover the 5 Critical AI Market Trends Reshaping Semiconductors in 2026
From datacenter accelerators to 2nm process technology, learn what’s next for AI and the semiconductor industry.
The acceleration of artificial intelligence (AI) adoption is fueling one of the most transformative periods in the history of semiconductors. As AI workloads expand across datacenters, edge devices, and consumer applications, they are driving new requirements in process technology, advanced packaging, and global market dynamics.
By 2026, datacenter accelerator markets alone are projected to exceed $300 billion, creating massive opportunities across the semiconductor value chain. But the implications go far beyond datacenters, shaping how AI models evolve, how power demands drive innovation, and how geopolitics will impact global supply chains.
In this webinar, TechInsights experts will share their perspectives on five critical expectations for AI markets in 2026 and what they mean for your strategy, designs, and investments.
Key Topics You’ll Learn

AI model evolution – Where are workloads heading in 2026?
Edge AI vs. datacenter AI – The hidden opportunities beyond the headlines.
Power demand & technology innovation – How 2nm and co-packaged optics will reshape performance.
Geopolitical dynamics – US-China competition and its impact on the AI chip ecosystem.
Market outlook – What industry leaders need to anticipate now to stay ahead.

REGISTER HERE

Andes RISC-V CON Munich
2025-10-14 13:00 - 17:00 | Smartvillage Bogenhausen, Smartvillage Bogenhausen, Rosenkavalierpl. 13, Munich, 81925, Germany
Andes RISC-V CON Munich
Smartvillage Bogenhausen
REGISTER HERE

IEEE International Conference on PHYSICAL ASSURANCE and INSPECTION of ELECTRONICS (PAINE)
2025-10-14 - 2025-10-16 | Denver, CO, Denver, CO, United States
ABOUT PAINE
Physical inspection of electronics has grown significantly over the past decade and is becoming a major focus for the chip designers, original equipment manufacturers, and system developers. The complex long life of the electronic devices coupled with their diverse applications is making them increasingly vulnerable to various forms of threats and inspection. Large industry and government efforts have been put in place across the globe to address related supply chain security problems to offer solutions, training, and services. The number of programs introduced by the US government has increased over the years to analyze and develop relevant solutions. Although much focus is given to the digital domain, physical assurance and inspection of electronics as well as physical fingerprinting based on analog parameters are rapidly providing opportunities for unique countermeasures.
PAINE conference provides a unique venue for all researchers and practitioners from academia, industry, and government to have productive dialog on such topics. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. PAINE covers the broad topic of hardware security and trust; example topics of interest include but are not limited to:
Topics to be Covered:

New metrologies for characterization and assurance
Advanced packaging and heterogenous integration
Emerging topics in physical inspection and assurance
Image analysis and artificial intelligence for assurance and inspection
Metrologies characterization
Automated inspection and metrology for advanced packaging
Security primitives: Novel devices, materials, and systems
Test vehicles and performance quantification
Additive manufacturing assurance for electronics
Physical and design interface assurance
Trojans and backdoors: Detection and prevention

Workforce Development
Fault injection assessment and countermeasures
Side channel assessment (power, timing, EM) for assurance and countermeasures
Analog & mixed-signal circuits and systems security
FPGA Bitstream protection and vulnerabilities
Counterfeit Detection and Anti-Counterfeit Technique
Novel material and devices for assurance
Sample Preparation
PCB trust and assurance
Chip and PCB level decomposition for assurance
FIB/SEM for assurance

Electro-optical probing using PEM, EOP, EOFM, etc.
Physical/side channel fingerprinting
Mod-chip on PCB
Microprobing and nanoprobing
Bus-snooping
Field-based weakness
Countermeasures against tampering and decomposition
Functionality validation
Process improvements
Failure analysis and fault isolation
Physical/logical shielding etc.
Photonics Assurance

REGISTER HERE

2025 OCP Global Summit
2025-10-13 - 2025-10-16 | San Jose Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
The OCP Summit is the premier event uniting the most forward-thinking minds in open IT Ecosystem development. The Summit presents a unique platform for our Community from around the globe to share their insights, foster partnerships and showcase cutting-edge advancements in open hardware and software.
*Join us in San Jose October 13-16 for the 2025 OCP Global Summit.
REGISTER HERE

Connected Equipment Summit
2025-10-09 09:00 - 17:30 | Hilton Phoenix Chandler, Hilton Phoenix Chandler, 2929 W Frye Road, Chandler, AZ, 85224, United States
Join us for our inaugural Connected Equipment Summit!
Register here: Connected Equipment Summit
October 9, 2025 | 9AM PT
This summit will take place at the Hilton Phoenix Chandler and will bring together industry leaders from across the semiconductor ecosystem—including fabs, equipment OEMs, and fabless companies. This premier event will showcase PDF Solutions’ latest innovations in equipment connectivity, secure remote access and monitoring, and the transformative applications of AI and digital twin technology in semiconductor equipment management.
What you’ll experience:

Strategic Insights & Product Innovation
Real-World Applications & Success Stories
Technology Leadership & Future Vision.

Sign up to join us today!
REGISTER HERE

CadenceCONNECT: CFD Innovations for the Marine Industry
2025-10-07 08:30 - 18:30 | Cadence Design Systems Belgium, Cadence Design Systems Belgium, Chau. de la Hulpe 189, Bruxelles, 1170, Belgium
What does the future hold for marine CFD simulation? Join us at the CadenceCONNECT: CFD Innovations for Marine Applications seminar to find out!
Historic software uses methods for solving that simply do not have the scalability to meet the needs of marine evolution. Cadence CFD analysis gives you an automatic and efficient computation setup. Additionally, our adaptive grid refinement allows for the constant improvement of simulation accuracy in an already highly capable solver environment.

Here are some of the topics we will cover:

What’s New and What’s Next: Cadence and Fine Marine: Latest developments and roadmap highlights.
Meshing Innovations in Fidelity CFD Software for Marine Applications: Explore V2S updates, S2V without far field, and other meshing enhancements.
C-Wizard and Automation in Fidelity: Streamlining workflows and boosting productivity.
Universal Setup for Ship Simulations in All Wave Conditions: Standardizing simulation setups for consistency and efficiency.
Coupling with MoorDyn: Simulating Cable Dynamics in Interaction with Ships: Integrating open-source tools for advanced marine simulations.
Optimization for Marine Applications with Optimality Intelligent Explorer: Leveraging optimization to improve design and performance.
Accelerating Mono-Fluid Simulations: Techniques and tools to reduce turnaround time.
PLUS User Sessions that discuss real-life case studies and success stories.
Plenty of opportunities to network during the happy hour.

Chau. de la Hulpe 189, 1170 Bruxelles, Belgium

REGISTER HERE

AutoSens Europe 2025
2025-10-07 - 2025-10-09 | Palau de Congressos, Palau de Congressos, Av. de la Reina Maria Cristina, s/n, Sants-Montjuïc, Barcelona, 08004, Spain
We’re back in the vibrant city of Barcelona, bringing together experts from across the industry

From 7th-9th October 2025, we’re reuniting the AutoSens community at the Palau de Congressos in Barcelona to shape the future of ADAS and AV.
With over 60 expert speakers, engaging panels, technical case studies, and exploration of 12 key themes, we delved into an exhibition with cutting-edge demos from sensor and computer vision leaders.

Why Attend?

Access to an expert community of over 500 experts and engineers
Extensive exhibition with over 50 stands showcasing the latest technology
Vehicle demos from leading Tier 1 and systems companies
High quality technical presentations from genuine experts
Thought-leader panel discussions that shape the industry’s future direction

REGISTER HERE

SEMICON West 2025
2025-10-07 - 2025-10-09 | Phoenix Convention Center, 100 N 3rd St, Phoenix, AZ, 85004, United States
SEMICON West 2025 makes its debut in Phoenix, October 7–9—positioning the city as a key hub for innovation and industry growth. This milestone event gathers global leaders across the microelectronics supply chain to explore transformative technologies, develop the future workforce, and drive strategic collaboration. Now more than ever, we are STRONGER TOGETHER.

Programs + Events
-CEO Summit/Keynotes
-Cybersecurity
-Design
-EHS & Sustainability
-Heterogeneous Integration
-Market Trends
-SEMI U Training Workshops
-SEMICON West’ern
-Smart Data/AI
-Smart Manufacturing
-Smart MedTech
-Smart Mobility
-Supply Chain
-TechTALKS
-Test Vision Symposium
-Workforce Development
-Networking Events
And More!

REGISTER HERE

it-sa Expo & Congress
2025-10-07 - 2025-10-09 | Nuremberg, Germany, Nuremburg, Germany
it-sa Expo&Congress in Nuremberg is Europe’s largest trade fair for IT security…
…and one of the most important dialogue platforms for IT security solutions.
The trade fair covers the entire range of products and services in the field of cybersecurity: hardware, software, training and consulting services as well as Security as a Service. Important topics at it-sa are cloud and mobile security, data and network security, the protection of critical infrastructures, and industrial Security.
Since 2009, it-sa Expo&Congress in Nuremberg has been the meeting place for decision-makers, experts and IT security officers from all sectors of the economy. Whether they represent industry, the service sector or public administration, the exhibitors at it-sa offer customised and individual solutions. On the exhibitor side, it-sa addresses the entire IT security market, including physical IT security. The event thus offers trade visitors a showcase of the IT security industry from Germany and abroad that is unique in Europe. Outstanding innovations by young companies in the field of cyber security will be honoured with the ATHENE Startup Award UP@it-sa.
The freely accessible lecture programme and product-neutral contributions and discussion panels from the it-sa insights series provide trade fair visitors to it-sa with the latest expertise in the industry. In addition, the congress programme Congress@it-sa, organised in cooperation with renowned associations and organisations, offers an intensive dialogue on current topics in IT security.

Welcome to the world of IT security.
REGISTER HERE

Webinar: Enabling Tomorrow’s Workloads with 1.6Tbps Ethernet
2025-10-02 12:00 - 13:00 | Online
Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the need for robust pre-silicon verification has never been greater.
Join this webinar to see how the Veloce™ hardware-assisted verification platform extends support for 1.6Tbps Ethernet through its proven Ethernet Packet Generator and Monitor (EPGM). Trusted by leading enterprises worldwide, EPGM helps engineering teams validate complex SoCs, stress test performance, and accelerate time-to-market with confidence.
What you’ll learn:

Why Veloce leads in networking verification
How EPGM delivers scalable, high-performance emulation and debug
New support for 1.6Tbps Ethernet, including IEEE 802.3dj 200G/lane

Who should attend:

SoC and ASIC design engineers working on Ethernet-based products
Verification and validation teams focused on networking and HPC workloads
System architects designing next-gen data center, AI, and cloud infrastructure

Engineering managers and decision-makers seeking to accelerate verification cycles and reduce risk
Speaker

Anup Shah
Director of Product Management, Siemens Digital Industries Software

REGISTER HERE

Webinar: Why Choose PCIe 5.0 for Power, Performance, and Bandwidth at the Edge?
2025-10-02 09:00 - 10:00 | Online
Featured Speakers:

Gustavo Pimentel, Principal Product Marketing Manager, Synopsys

As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged as the optimal interconnect standard. Doubling the data rate of PCIe 4.0 while enabling lane reduction, PCIe 5.0 helps SoC designers achieve significant savings in power, area, and beachfront—critical advantages for space- and thermally-constrained environments such as ADAS, AIoT, and 5G edge devices.
In this Synopsys webinar, we will discuss how our high-performance, silicon-proven PCIe 5.0 IP enables scalable systems and energy efficiency across automotive, mobile, and edge use cases. We will explore:

Key benefits of migrating to PCIe 5.0
Architectural considerations for integrating PCIe 5.0 in edge SoCs
Low-power design techniques, including dynamic power gating
Real-world deployment examples and interoperability highlights

Join us to learn how to future-proof your SoC designs with PCIe 5.0 and meet the demands of the next wave of intelligent edge applications.

Featured Speakers

Gustavo Pimentel
Principal Product Marketing Manager, Synopsys
Gustavo is a Principal Product Marketing Manager at Synopsys, specializing in PCIe products. With 17 years of experience in embedded software, Gustavo has spent the last 8 years developing Linux device drivers for Synopsys IPs, including PCIe.

REGISTER HERE

2025 WLI WISH Conference
2025-10-01 08:00 - 17:00 | San Jose McEnery Convention Center, San José McEnery Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
Join us at WISH, GSA WLI’s premier technical conference that promises to be an inspiring celebration of innovation and empowerment. With around 1,000 attendees, including industry luminaries, visionary entrepreneurs, and brilliant university students in STEM, this event will showcase the evolving landscape of technology. Attendees can look forward to inspiring keynotes from trailblazers who are reshaping the tech world, as well as celebratory awards honoring extraordinary women who have broken the glass ceiling and those paving the way for future generations.

This is a unique opportunity to connect with like-minded professionals and forge valuable relationships that can propel your career forward. Join us in championing gender parity and celebrating the remarkable achievements of women in technology—be part of the movement transforming the industry!
REGISTER HERE

Silicon Photonics Workshop
2025-09-30 18:00 - 21:00 | 1 Hotel Copenhagen, 1 Hotel Copenhagen, Krystalgade 22 1172, Copenhagen, Denmark
Lighting the Future: Advancing Silicon Photonics for the AI Connectivity Era

Soitec is pleased to host a private workshop event in parallel of ECOC 2025, offering a forward-looking perspective on the expanding role of photonics in enabling next-generation AI architectures.

The workshop will bring together leading voices from across the value chain such as : Coherent, ST, Lightcounting, CEA Leti and Soitec.

Speaker lineup and detailed agenda will be announced early september.

Frequently asked questions

Is the event free to attend?

Yes the event is free to attend

What is the easiest way to reach the 1Hotel from the ECOC 2025 conference?

The easiest and fastest way will be to use the metro. Click on this link to get directions. It is an 11 mins metro ride.

Should I register to attend the event ?

Yes all the attendees have to register. The organizers will screen the registration and reserve the right to validate or decline any registrations.

Is there a reception following the event ?

Yes, a reception will be organized at the end of the workshop

Do you validate parking ?

No, the organizers are not validating parking

REGISTER HERE

CadenceTECHTALK: Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform
2025-09-30 11:00 - 12:00 | Online
Overview

Join us for a series of expert-led webinars showcasing cutting-edge simulation and analysis tools—from RF/mmWave modeling to advanced thermal and electromagnetic solutions. While designed for a broad range of high-performance electronics applications, each session also highlights how these technologies can be adapted to meet the rigorous demands of aerospace and defense (A&D) systems.
Topics Highlights:

RF and mmWave Modeling: Discover how Modelithics’ advanced models improve accuracy and reduce risk in high-frequency A&D systems.
3D EM and Antenna Optimization: See how Cadence’s Clarity 3D Solver and Optimality Intelligent System Explorer enable fast, scalable simulation for complex RF and antenna designs.
Thermal Reliability with Cadence Celsius Studio: Explore AI-enabled thermal analysis for mission-critical electronics in extreme environments.

REGISTER HERE

Webinar: Hardware design of custom AI accelerators using High-Level Synthesis
2025-09-30 09:00 - 10:00 | Online
As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will cover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We will cover the step-by-step design and verification of the Wake Word algorithm using HLS. Not only will we be showcasing conventional HLS flows, but we are excited to share our new product Catapult AI/NN. This new product takes High-Level Synthesis and extends it to models trained in python. With this new development we will now be able to develop AI hardware even faster.
PS: Stick around till the end to learn about our hackathon. You will get the chance to have hands-on experience with using Catapult to design AI applications along with winning some pretty sweet prizes. Don’t forget bragging rights!
REGISTER HERE
Speakers:

Cameron Villone
High-Level Synthesis Technologist, Siemens EDA

Cameron Villone is a High-Level Synthesis Technologist working with the Catapult High-Level Synthesis product management and marketing team, focusing on AI hardware deployment. He previously worked as a product marketing engineer for PowerPro, Siemens’ power optimization and analysis product. He held previous roles at Texas Instruments and General Motors. Cameron studied and graduated from Rochester Institute of Technology, obtaining both a bachelor’s and master’s degree in electrical engineering, focusing on Robotics, Embedded Systems, and Computer Vision.

Russell Klein
HLS Program Director, Siemens EDA

Russell Klein is a Program Director at Siemens EDA’s (formerly Mentor Graphics) High-Level Synthesis Division focused on processor platforms. He is currently working on algorithm acceleration through the offloading of complex algorithms running as software on embedded CPUs into hardware accelerators using High-Level Synthesis. He has been with Mentor for over 25 years, holding a variety of engineering, marketing and management positions, primarily focused on the boundary between hardware and software. He holds six patents in the area of hardware/software verification and optimization. Prior to joining Mentor he worked for Synopsys, Logic Modeling, and Fairchild Semiconductor.

REGISTER HERE

IMAPS Symposium 2025
2025-09-29 - 2025-10-02 | Town & Country Resort, San Diego, 500 Hotel Cir N, San Deigo, CA, 92108, United States
September 29 – October 2, 2025
Co-located with Semiconductor thermal management
Town & Country resort
San Diego, California
The 58th International Symposium on Microelectronics is organized by the International Microelectronics Assembly and Packaging Society and held in San Diego, California. IMAPS Symposium offers one of the most robust programs for microelectronics and advanced packaging technical content. Each year, we welcome many repeat attendees as well as hundreds of first-time visitors – early career packaging professionals, those new to the industry, and students.
Our event kicks off with Professional Development Courses, followed by 3 days of technical sessions with emphasis on Advanced Package Structures (Heterogeneous Integration, HPC, AI); Advanced Interconnect, Bumping & Wirebond Technologies; RF, MEMS/Sensors, High Rel, WLCSP, Small Body FO; Enabling Materials & Advanced Equipment; and CPI, Modeling, Design, Metrology.
Conference: September 30 – October 2
Exhibition: September 30 – October 1
Professional Development Courses: September 29
All Symposium sessions will take place at the Town & Country Resort.
Organizing Committee:
General Chair: Benson Chan, Binghamton University
General Chair-elect: Karthik Dhandapani, Qualcomm
Past General Chair (2024): Tarak Railkar, Qorvo
REGISTER HERE

Semitracks Course: Failure and Yield Analysis
2025-09-29 - 2025-10-02 | Phoenix, AZ, Phoenix, AZ, United States
Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. Failure and Yield Analysis is a 4-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure. This course is designed for every manager, engineer, and technician working in the semiconductor field, using semiconductor components or supplying tools to the industry.
By focusing on a Do It Right the First Time approach to the analysis, participants will learn the appropriate methodology to successfully locate defects, characterize them, and determine the root cause of failure.

What Will I Learn By Taking This Class?
Participants will learn to develop the skills to determine what tools and techniques should be applied, and when they should be applied. This skill-building series is divided into three segments:

The Process of Failure and Yield Analysis. Participants will learn to recognize correct philosophical principles that lead to a successful analysis. This includes concepts like destructive vs. non-destructive techniques, fast techniques vs. brute force techniques, and correct verification.
The Tools and Techniques. Participants will learn the strengths and weaknesses of a variety of tools used for analysis, including electrical testing techniques, package analysis tools, light emission, electron beam tools, optical beam tools, decapping and sample preparation, and surface science tools.
Case Histories. Participants will identify how to use their knowledge through the case histories. They will learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed.

Course Objectives

This course will provide participants with an in-depth understanding of the tools, techniques and processes used in failure and yield analysis.
Participants will be able to determine how to proceed with a submitted request for analysis, ensuring that the analysis is done with the greatest probability of success.
This course will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.
This course will offer a wide variety of video demonstrations of analysis techniques, so the analyst can get an understanding of the types of results they might expect to see with their equipment.
Participants will be able to identify basic technology features on semiconductor devices.
Participants will be able to identify a variety of different failure mechanisms and how they manifest themselves.
Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

REGISTER HERE

ECOC 2025
2025-09-28 - 2025-10-02 | Bella Center, Bella Center, Center Boulevard 5, Copenhagen, 2300, Denmark
The 51st European Conference on Optical Communication
Welcome to ECOC 2025 in Copenhagen

ECOC, the European Conference on Optical Communication, stands as Europe’s premier gathering for optical communications, holding a prominent position as one of the globe’s most significant events in this field. This conference unites pioneers and professionals from academia, research, and industry, fostering the exchange of cutting-edge discoveries and future-oriented perspectives.
At ECOC, you’ll find an optimal environment to enrich your knowledge, engage in dynamic discussions, and forge valuable connections. Its scope spans from the fundamental materials and devices enabling optical communication to the intricate systems and networks employing these technologies.
The ECOC Exhibition, in existence for nearly three decades, has evolved into Europe’s largest optical communications exhibition. It serves as a pivotal hub where industry leaders convene, making it a cornerstone for decision-makers in the fiber optic communications technology sector.

REGISTER HERE

CASPA 2025 Annual Conference and Dinner Banquet
2025-09-27 09:00 - 21:00 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
CASPA ACDB 2025 — A premier global summit uniting industry leaders, entrepreneurs, researchers, and investors to explore the future of Artificial Intelligence and Semiconductors
Theme:
🧠 “AI Ecosystem Revolution: Advancing Tomorrow’s Intelligence Together”
📌 A full-day experience featuring:
✨ Keynote Presentations
💡 Visionary Panel Discussions
🍽️ Formal Dinner Banquet
🤝 Exclusive Networking Opportunities
🎤 Keynote Speakers:
🔹 David Wang, Senior Vice President, AMD — Annual Conference Keynote
🔹 Dr. Lisa Su, CEO, AMD — Dinner Banquet Keynote
🚀 Don’t miss this unique opportunity to connect with the people, technologies, and ideas shaping the next generation of intelligent systems. click here to register
REGISTER HERE

Cloud Tech Day 2025
2025-09-25 10:00 - 14:00 | Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, CA, 95054, United States
Join industry leaders and Cadence cloud experts at this free must-attend Cloud event of the year to explore the latest cloud EDA innovations, share ideas, and grow your professional connections.
All attendees will receive a giveaway and a chance to win raffle prizes.
DATE: September 25, 2025
TIME: 10:00am – 1:45pm PDT
LOCATION: Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, CA 95054
Cloud technology is transforming EDA, enabling greater scalability, flexibility, and collaboration as design complexity rises and security concerns ease. Cadence OnCloud, built with leading foundries and partners, delivers industry-leading security, cost efficiency, and flexibility, supporting hundreds of successful tapeouts.
Check out the full agenda here.
Why this is THE Must-Attend Cloud Event of the Year!
This event is designed to empower you with the tools, insights, and strategies to stay ahead in the rapidly evolving world of EDA. Here’s what you’ll gain:

Exclusive Insights: Gain a sneak peek at new Cadence OnCloud features, including game-changing Cloud 3.0 for industry-leading cost efficiency.
Actionable Strategies: Learn how to implement an all-cloud or hybrid cloud environment to optimize your design flow and infrastructure and seamlessly transition from an evaluation to a production environment.
Live Demonstrations: See Cadence OnCloud in action and experience how effortlessly you can run your design flows in a cloud or hybrid setup.
Direct Access to Experts: Meet the R&D and business teams behind the Cadence Cloud portfolio and get your questions answered.
Networking Opportunities: Connect with industry leaders, peers, and Cadence experts to exchange ideas and grow your professional network.

Whether you’re a design/CAD engineer, CAD manager, IT manager, or business leader, this event will provide you with the knowledge and connections to transform your design processes and drive innovation.
REGISTER HERE

Webinar: Static Verification of RTL DFT Connectivity – Getting it Right the First Time!
2025-09-25 09:00 - 10:00 | Online
Featured Speakers:

Kiran Vittal, Synopsys
Ayush Goyal, Synopsys

As System-on-Chip (SoC) designs become increasingly complex, ensuring reliable Design-for-Test (DFT) connectivity at the RTL stage is more important than ever. This Synopsys webinar will demonstrate how static verification techniques, powered by TestMAX™ Advisor on the VC SpyGlass® platform, can help you address connectivity challenges efficiently and accurately. Learn how robust connectivity checks can improve design quality and streamline your verification process.
Why You Should Attend:

Discover best practices for verifying RTL DFT connectivity in modern SoC designs.
See practical demonstrations of customizable connectivity checks and advanced GUI analysis tools.
Learn how to detect both DFT and functional connectivity issues early in the design cycle.
Gain insights from Synopsys experts on leveraging static verification for faster, more reliable design closure.

Don’t miss this opportunity to enhance your verification workflow—secure your spot today!
REGISTER HERE

Featured Speakers

Kiran Vittal
Executive Director, Synopsys
Kiran Vittal is the executive director of product management for the Synopsys Design-for-Test line of business in the Product Management and Markets Group. He has 25+ years of experience in EDA and semiconductor design.

Ayush Goyal
Senior Staff R&D Engineer, Synopsys
Ayush Goyal is Senior Staff R&D Engineer in the Hardware Analytics and Test Group at Synopsys. He joined Synopsys in 2016. He has been working in the EDA industry for the last 9 years focused in the areas of software-driven automation technologies.

REGISTER HERE

Andes RISC-V CON Seoul
2025-09-24 13:00 - 17:00 | EL Tower, EL Tower, 213 Gangnam-daero, Seoul, Seocho District, Korea, Republic of
Andes RISC-V CON Seoul
REGISTER HERE

Webinar: Getting Started with the Vitis Unified IDE
2025-09-24 11:00 - 12:00 | Online
Description
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating complex workflows can feel overwhelming. The AMD Vitis™ Unified IDE simplifies the process by integrating Vitis IDE, Vitis Analyzer, and Vitis HLS into a single, structured environment. In this session, you’ll learn how to create and manage projects, build and debug applications, and utilize the Python-based command line for a more efficient workflow. Whether you are transitioning from Vitis Classic or starting fresh, this webinar will help you improve accuracy and streamline your development process.
This webinar includes a live demonstration and Q&A.
If you are unable to attend, a recording will be sent one week after the live event.
To see our complete list of webinars, visit our website: www.bltinc.com.
REGISTER HERE

Webinar: 448G PAM4: The Future of 3.2T Data Centers
2025-09-24 10:00 - 11:00 | Online
About this event
Join industry experts from NTT Innovative Devices, Lumentum, and Keysight to discuss their historic demonstration of 448g / lane signaling over PAM4 — a cross-continental collaboration that’s laying the foundation for the next generation of AI data centers and high-speed Ethernet.

Who should attend this event?
R&D engineers at network equipment manufacturers who are building high-speed interconnects and transceivers for AI-ready data centers.
REGISTER HERE
