Webinar: Automate PCB documentation with BluePrint-PCB
2025-12-09 13:00 - 14:00 (America/Los_Angeles) | Online
Streamlining fabrication and assembly documentation

December 9, 2025 at 06:00 AM Pacific Standard Time
December 9, 2025 at 01:00 PM Pacific Standard Time

BluePrint-PCB is a documentation automation tool that streamlines PCB fabrication, assembly, and inspection by generating intelligent, customizable electronic drawings directly from design data. BluePrint-PCB by Siemens integrates with PCB design workflows to produce comprehensive documentation packages tailored for fabrication and assembly processes. It supports direct imports from Siemens tools like Xpedition and PADS Professional, as well as industry-standard formats such as ODB++, IPC-2581, and PADS ASCII. Users can enhance documentation with additional formats including DXF, PDF, CSV, and JPEG.
Key capabilities include:

Automated drawing generation using drag-and-drop palettes for elements like drill charts, parts lists, and stackups, all populated with live design data.
Customizable documentation profiles that allow organizations to standardize symbols, tables, borders, and note blocks across teams.
Stackup Visualizer for interactive layer management, material assignment, and 3D visualization of PCB stackups and drill spans.
3D documentation export to Adobe PDF with interactive views, camera controls, and scrollable content.
Assembly panel design tools for creating optimized PCB arrays with features like mill tabs and fiducials.

A full set of Dimensioning tools; Auto Dim, Coordinate Dimensioning, Point to Point, and GD&T.
BluePrint-PCB enhances collaboration and reduces revision cycles by synchronizing all drawing content with the source PCB design file, ensuring accuracy and consistency throughout the documentation lifecycle.

Meet the speaker

Siemens
Ray Fugitt
Technical Marketing Engineer

Ray is a Technical Marketing Engineer at Siemens Digital Industries Software. He has 40 years of Printed circuit board experience, including 23 years at Downstream Technologies and 11 years at Hadco Corporation in Product and CAM engineering.
Starting on the Manufacturing floor in AOI and Electrical Test, He worked his way to the Engineering and CAM areas. Later he was CAM supervisor and was part of the move to Valor Genesis software.
He joined Downstream in technical marketing for CAM350 and later, technical sales positions. He has supported and provided training for the BluePrint PCB and CAM350 products for over 20 years. He continues in this role at Siemens Digital Industries Software.

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AI Everywhere 2025
2025-12-10 - 2025-12-11 | Online
Description

In the data center, the shift to inference is in full swing. Infrastructure for inference is being built out at scale around the world in what Jensen Huang calls “AI factories,” optimized for the best possible tokens per dollar performance on a small but growing number of open-source LLMs. Sovereign AI efforts are also gaining momentum. Several chip companies in this market have become AI cloud service providers, shifting their business models to providing APIs for fast tokens, where they have an advantage versus Nvidia. Is now the time for data center inference-only chips to shine? What’s the limitation on tokens per second, and what are the avenues for chip and system design that can break these bottlenecks? And will cutting-edge techniques like reasoning and agentic AI drive demand for more tokens? ​
At the edge, tokens per watt is becoming a dominant metric as all kinds of appliances get the ability to communicate in natural language. However, the rollout of AI-powered vision and audio analytics technologies, as well as time series sensor data analytics applications, is also becoming widespread in industrial, automotive, healthcare, and consumer electronics. Are edge chips keeping pace with the demands of new open-source models, and how do techniques like reasoning and agentic AI apply at the edge? How do we support edge AI applications from R&D to deployment and throughout the product’s life cycle? What challenges remain for chip and system design in the spectrum of edge use cases, and how can we discourage fragmentation and encourage efficiency, usability, and portability?​
These topics and more will be explored during this two-day virtual conference on December 10-11.
More information about the conference agenda will follow soon.
What to expect?
With a conference space and resource center, AI Everywhere functions similarly to a live exhibition and conference. The technical conference will include keynotes, panel discussions and technical presentations on a variety of subjects, including significant technical trends, design ideas and new application areas. Along with the conference, there will be a resource center with microsites from relevant businesses that will include useful links and AI-focused technical materials available for download.
Who should attend?
This event will cater for AI system designers across the spectrum of AI use cases, embedded engineers and software developers, data scientists and anyone with an interest in AI hardware, software and system design. The aim is to present the latest in hardware and software for this extremely fast-moving sector and discuss the challenges that remain and how the industry should respond to them.
Contact

Are you interested in getting involved? Please see our details below
For Companies
We are offering sponsor packages to generate leads, raise brand awareness and participate in the conference and exhibition. If you would like more information about sponsorship opportunities, please contact: sales@aspencore.com
For Attendees
If you want to register for the event as an attendee and you have any questions, technical issues, or want a certificate of attendance please contact: events@events.mail.eetimes.com

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Webinar: Trained Eyes on 64G UCIe: Scale Chiplet Integration for AI
2025-12-10 09:00 - 10:00 | Online
Join us to hear firsthand from the innovators at Siemens and Alphawave Semi and learn proven practices to enhance your UCIe-enabled AI system performance!
The semiconductor industry is shifting rapidly from monolithic SoC design to chiplet-based systems. At the same time, AI compute workloads have pushed into petaflop-class speeds, demanding higher throughput from die-to-die (D2D) connectivity. 64G UCIe (Universal Chiplet Interconnect Express) delivers the performance, power, and area (PPA) advantages to meet the demands of tomorrow’s AI workloads. However, to achieve the performance for next-gen UCIe-based systems, design engineers face significant signal integrity challenges — from crosstalk and reflections to process variation.
This webinar will explore the emerging D2D connectivity applications, and the bandwidth demands that make 64G signaling a necessity. You’ll also learn how to:

Optimize system performance, power, and area (PPA) with best-in-class IP
Reduce design risks for advanced architectures with shift-left design methodologies
Ensure design intent translates into reliable hardware via simulation-to-silicon correlation

Who Should Attend:

Design engineers and system architects involved in designing, simulating, and validating chiplet-based systems — especially those tackling die-to-die (D2D) connectivity, UCIe integration, or seeking system-level PPA optimization.

Don’t miss out on this incredible chance to learn how to implement a comprehensive 64G UCIe design flow and participate in a live Q&A session! Register today to secure your spot.
REGISTER HERE

Meet the speakers

Alphawave Semi
Archana Cheruliyil
Principal Product Marketing Manager

Archana Cheruliyil is the Product Line Manager for HBM, D2D, and 3DIO IP at Alphawave Semi, where she drives the development of next-generation interface IP solutions and oversees marketing efforts. With a deep passion for identifying optimal solutions within the dynamic and complex landscape of AI systems, she works to address the evolving needs of customers. Archana is an invited speaker at conferences and panels on 3DIO interconnects and technology, where she shares insights on emerging trends and practical implementations in advanced packaging.
Previously, Archana served as the IP Strategy and Planning Lead at Intel Corporation, where she played a key role in defining and advancing the interface IP roadmap for both the Client and Data Center business units. She has over a decade of experience in analog mixed-signal design, specializing in high-speed clocking circuits, and has successfully led a matrixed engineering team to deliver cutting-edge IP on leading-edge process nodes.
Archana holds a Master of Science in Electrical Engineering (MSEE) from the University at Buffalo.

Siemens
Bryan McDevitt
Applications Engineer,

Bryan McDevitt is an Applications Engineer at Siemens EDA, where he has spent 18 years supporting board- and package-level simulations with the HyperLynx suite of tools. Before moving into applications engineering, he worked as an electrical engineer designing single board computers.

Siemens
Kendall Hiles
Sr. Product Specialist – 3D IC Packaging flow

Kendall Hiles is a Sr. Product Specialist for the 3D IC Packaging flow at Siemens Digital Industries Software, bringing over 40 years of comprehensive experience in electronics design and test engineering. He specializes in customizing EDA tools and developing sophisticated automated workflows that effectively bridge traditional design methodologies with cutting-edge packaging innovations and advanced semiconductor technologies. Throughout his extensive career, his expertise encompasses developing robust batch processing capabilities and establishing streamlined handoffs across the entire IC Packaging toolchain, ensuring efficient data flow and maintaining design integrity throughout complex multi-tool workflows. His current work includes pioneering automation solutions for creating system-level test vehicle daisy chains specifically designed for chiplet-based architectures, as well as developing comprehensive automated analysis capabilities for DC Drop power analysis, Loop PDN analysis, and high-frequency S-Parameter extractions for advanced IC package designs. Kendall’s innovative approaches have significantly improved design productivity while reducing time-to-market for complex packaging solutions, making him a recognized expert in the intersection of traditional PCB design and modern IC packaging technologies.

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Webinar: 5 Expectations for the Consumer Electronics Market in 2026
2025-12-16 11:00 - 12:00 | Online
December 16, 2025 – 11:00 AM EST
December 17, 2025 – 10:00 AM JST/KST
Discover the 5 Critical Consumer Electronics Market Trends Reshaping Semiconductors in 2026
AI, tariffs, smart home, and display innovations—what’s next for consumer electronics.
The consumer electronics market is poised for transformation in 2026, driven by technology innovation, geopolitical dynamics, and rising consumer expectations for convenience, performance, and usability.
In this live TechInsights webinar, our consumer electronics experts will highlight five critical trends shaping the market, giving strategists, designers, and executives the insights needed to adapt, innovate, and lead.
Key Topics You’ll Learn

Transformer-Based AI Adoption – How device makers are using AI to enhance products and services.
Impact of US Import Tariffs – How tariffs affect both supply chains and consumer demand.
Matter Smart Home Standard – Advancements delivering true multi-brand interoperability.
Display Technology Innovations – How new approaches are transforming the smart TV market.
Momentum for Smart Glasses – AI-driven use cases and new entrants driving adoption.

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SEMICON Japan 2025
2025-12-17 - 2025-12-19 | Tokyo Big Sight, 3 Chome-11-1 Ariake, Koto City, Tokyo, Japan
SEMICON Japan is the premier event that brings together the semiconductor manufacturing supply chain for the latest insights, trends and innovations as the industry powers digital transformation. SEMICON Japan 2025 will highlight Smart applications powered by semiconductor technology such as automotive and Internet of Things (IoT).
REGISTER HERE

Webinar: From Silos to Systems, From Data to Insight (AM Session)
2025-12-17 10:00 - 11:00 | Online
December 17, 2025 | 10:00 AM PST
Join us to discover how Keysight Design Data Management (SOS) Enterprise Collaboration, as the backbone for modern engineering enterprises, enables teams to build organizational knowledge, secure collaboration, and prepare their data for AI and agentic workflows that drive measurable competitive advantage. The biggest challenges today are managing complexity, ensuring governance, and preparing data for AI. That’s exactly why Keysight SOS becomes critical.
What You Can Learn:

How to transition from disconnected design data silos to a unified, governed platform that accelerates collaboration and reuse.
How structured, traceable data enables analytics, machine learning, and AI copilots to boost design productivity and reduce rework.
How Keysight SOS Enterprise Collaboration empowers organizations to scale globally with secure governance, hybrid deployment, and AI-ready infrastructure.

Who Should Attend?

Engineering Directors and VPs of R&D seeking to modernize design collaboration and build enterprise-wide data governance.
CAD/EDA Managers and Methodology Leads responsible for tool integration, data management, and multi-site standardization.
Design and Verification Leads looking to improve traceability, reuse, and cross-domain visibility in complex design workflows.
IT and Data Governance Executives focused on compliance, audit readiness, and secure access to sensitive design data.
AI/ML Engineers and Data Scientists aiming to leverage structured engineering data for analytics, modelling, and AI-driven design acceleration.

Not in the Americas? Our European friendly session is also available – join here.

Presenter

Pedro Pires
Product Manager – Keysight Technologies
Pedro Pires is a Product Leader at Keysight Technologies with deep expertise in data management, engineering productivity, and MLOps for electronic design automation (EDA). With over a decade of experience spanning product strategy, design infrastructure, and enterprise data lifecycle management, he has helped global semiconductor organizations modernize their engineering environments through scalable collaboration, governance, and process automation.
At Keysight, Pedro leads initiatives that connect design and data platforms across global teams, defining the architecture for next-generation solutions that unify design data and enable AI readiness through sound data foundations. He holds a Master’s in Microelectronics Engineering, an MSc in Finance and Big Data, and is pursuing an Executive MBA at IESE Business School in Barcelona.

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Essential Debugging Techniques Workshop
2025-12-17 10:00 - 16:00 | Online
Essential Debugging Techniques Workshop
This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with general debugging concepts, tools and techniques. Special topics include helping guide attendees through the differences of using ISE Design Suite based ChipScope in Vivado for migrating to 7 Series devices and onward.
Additionally, this workshop will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. The demonstrations utilizing actual AMD ZCU104 Evaluation Boards provide attendees with experience designing, expanding and modifying an embedded system, including techniques for triggering on boot and hardware-software co-debugging.

COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.

REGISTER HERE

Webinar: 5 Expectations for the Mobile Market in 2026
2026-01-05 11:00 - 12:00 | Online
January 5, 2026 – 11:00 AM EST
January 6, 2026 – 10:00 AM JST/KST
Discover the 5 Critical Mobile Market Trends Reshaping Semiconductors in 2026
Mobile AI, shifting supply chains, and new form factors—what’s next for the mobile semiconductor industry.
The mobile semiconductor market faces an inflection point in 2026. While trade and tariff uncertainties continue to disrupt global supply chains, breakthrough technologies promise to reinvigorate growth in an industry facing maturity pressures.
As Google, Apple, and new disruptors expand AI-driven mobile experiences, OEMs are rethinking hardware design, SoC innovation, and DRAM integration to meet rising consumer expectations. At the same time, geopolitical dynamics are reshaping long-term manufacturing strategies, and BRIC and emerging markets are exerting new influence over global demand.
In this live TechInsights webinar, our experts will break down five critical developments reshaping the mobile industry in 2026 and beyond.
Key Topics You’ll Learn

Mobile AI adoption – Google, Apple, and potential disruptors drive consumer traction.
Hardware & AI co-evolution – SoCs and DRAM innovation across Android OEMs.
Tariffs & trade impact – How pricing and supply chains are being reshaped.
Emerging market influence – BRIC nations and new growth regions take the stage.
Form-factor innovation – New designs promise to revitalize a stagnating market.

REGISTER HERE

CES 2026
2026-01-06 - 2026-01-09 | Las Vegas Convention Center, Las Vegas Convention Center, 3150 Paradise Rd, Las Vegas, NV, 89109, United States
The world’s most powerful tech event is your place to experience the innovations transforming how we live.

This is where global brands get business done, meet new partners and where the industry’s sharpest minds take the stage to unveil their latest releases and boldest breakthroughs. Get a real feel for the latest solutions to the world’s biggest challenges with immersive activations and demos. Engage with the greatest minds and most impactful brands of our time. Sign up to be notified when registration opens for CES 2026.

CES unites the brightest tech luminaries to pioneer the future and solve the world’s biggest challenges.

CES connects innovators, decision makers, media, influencers, visionaries, and potential customers across the entire tech ecosystem.
Don’t be left in the past as we shape the future.

Globally showcase your technology products
Stand side-by-side with the world’s most disruptive innovators
Promote your brand through curated opportunities to connect with influencers and prospective partners

REGISTER HERE

ISS 2026 Industry Strategy Symposium
2026-01-11 - 2026-01-14 | The Ritz-Carlton, Half Moon Bay, The Ritz-Carlton, 1 Miramontes Point Rd, Half Moon Bay, CA, 94019, United States
Join us at the Ritz-Carlton in Half Moon Bay, CA to get the latest insights on economic trends, market drivers, geopolitics, technology, and what these will mean for the near future to help drive your business forward. The cooperative platform of ISS and its tremendous collective assets will serve to help power your strategies for the coming months and years.
READY, SET, RAMP!

Building upon last year’s theme “Ready, Set, Ramp? “ of readiness and anticipation, this year marks a bold declaration of action and confidence as we propel forward with vigor and purpose.
“Ready, Set, Ramp! serves as a call to action for industry stakeholders to navigate these uncharted waters with agility and strategic vision.
It replaces the question marks of uncertainty with the exclamation points of determination and readiness!
As the semiconductor industry accelerates towards the monumental trillion-dollar milestone, it’s crucial to explore strategies for coping with the rapid acceleration. Understanding and maneuvering through the dynamic landscape becomes paramount for sustained prosperity.
ISS delves into the multifaceted dimensions of this journey, encompassing technological innovations, burgeoning demand, market diversification, global integration, R&D investments, workforce shortage, and sustainable practices. Addressing challenges and harnessing opportunities necessitates a holistic approach, requiring collaborative efforts from industry stakeholders, governments, and research institutions.

What are the demands and challenges inherent in this accelerated growth?
How is the industry allocating resources to facilitate this ramp-up?
How do we set the stage for all-time highs in semiconductor revenue and Wafer Fabrication Equipment (WFE) Investment?
Exploring the impact of emerging technologies and market diversification on the ramp-up trajectory.
Accelerated computing powering a new industrial revolution–Are we prepared?
What collaborative efforts and partnerships are necessary to overcome challenges and capitalize on opportunities as we surge toward the trillion-dollar milestone?

By engaging in these critical key questions and through collaborative discussions, ISS attendees gain actionable insights and strategies for capitalizing on the industry’s upward trajectory while mitigating risks and challenges along the way, positioning themselves for success in the race toward the trillion-dollar milestone.
KEYNOTES

AMD—Ramine Roane, Corporate VP, AI
Applied Materials—Omkaram Nalamasu, PhD, Senior Vice President and CTO; Prabu Raja, PhD, President, Semiconductor Products Group
KLA—Oreste Donzella, Executive Vice President – Electronics, Packaging and Components (EPC) Group
TSMC—Kevin Zhang, PhD, Senior Vice President of Business Development & Global Sales and Deputy Co-COO
Former U.S. Secretary of Commerce—The Honorable Wilbur Ross

ISS 2025 Organizing Committee
Thank you to these industry leaders for their time and expertise supporting the continued success of this annual conference.
REGISTER HERE

Terascale AI, 1.6T and Beyond Seminar: Santa Clara
2026-01-13 08:00 - 17:00 | Santa Clara, CA, Santa Clara, CA, United States
About this event
Next-generation AI systems are pushing electrical, optical, and packaging technologies to their limits. Join Keysight experts as they share insights on validating 224G / 448G SerDes, preparing for emerging IEEE 1.6T optical standards, advancing silicon photonics, and strengthening die-to-die interconnects for chiplet-based architectures.
This is your chance to learn directly from the engineers shaping the future of high-speed I / O design — all in one room. Sign up today.

Who should attend this event?
This seminar is ideal for engineers working on next-generation connectivity and AI infrastructure, including optical design, silicon photonics, high-speed digital, validation, test & measurement, signal integrity, compliance, and chiplet / die-to-die interconnect architectures.

REGISTER HERE

Webinar: PQShield with Microchip’s PolarFire® SoC FPGAs: Securing the Future of Embedded Systems in the Post-Quantum Era
2026-01-13 09:00 - 10:00 | Online
As the quantum threat moves from theory to reality, attacks put all long-lifecycle designs at risk. In this early PQC era, simply implementing the new NIST algorithms isn’t enough. Implementations will evolve, and new physical attacks like side-channel analysis present a major threat to the security of these complex new algorithms.
The solution requires both crypto-agility and deep hardware security. This webinar showcases PQShield’s hardware/software co-design as a side-channel secure PQC solution for Microchip’s PolarFire ® Series of products.

Speaker:

Sebastien Riou
Fellow, Product Security Architecture, PQShield

Sebastien has 15+ years experience in the semiconductor industry, focusing on achieving “banking grade security” on resource constrained ICs such as smart cards and mobile secure elements. Formerly of Tiempo-Secure, he helped create the world first integrated secure element IP achieving CC EAL5+ certification. He is the author of a semi-finalist algorithm at the Lightweight Cryptography NIST Standardisation process. He holds Master degrees in Computer Science and Cognitive Science from INPG.

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Webinar: Advances in ATPG: From Power and Timing Awareness to Intelligent Pattern Search with AI
2026-01-14 10:00 - 11:00 | Online
Date: Jan 14, 2026 | 10:00 AM PST

Featured Speakers:

Srikanth Venkat Raman, Product Management Director, Synopsys
Khader Abdel-Hafez, Scientist, Synopsys
Theo Toulas, R&D Principal Engineer, Synopsys
Bruce Xue, Staff Engineer, Synopsys

As System-on-Chip (SoC) designs become increasingly complex, meeting test quality and cost goals requires advances in automatic test pattern generation (ATPG). Synopsys TestMAX™ ATPG is Synopsys’ state-of-the-art pattern generation solution. In this Synopsys webinar, we will showcase the latest ATPG advancements, from power- and timing-aware capabilities to leveraging AI for reducing test costs. Discover how you can meet the power constraints of your SoC tests with power-efficient ATPG patterns. Learn how timing-aware ATPG can enhance test quality. We will also explore Synopsys TSO.ai™ (Test Space Optimization AI), the industry’s first autonomous AI application for semiconductor testing, designed to minimize test cost and time-to-market for today’s complex designs.
Why You Should Attend:

Discover best practices for limiting power consumption during shift and capture operations.
See practical demonstrations of how you manage test power at the top-level of your SoC through a top-level budget and partition-level budgets.
Learn how advanced fault models (slack-based transition, path delay, and hold-time) can improve the quality of your tests from a timing standpoint.
Gain insights from Synopsys experts on how TestMAX™ ATPG leverages tighter connection with PrimeTime® to better handle timing exceptions (SDC) during test generation. See how ATPG can handle Muti-cycle paths (MCPs).
Learn how TSO.ai automatically searches for an optimal solution in a large test search space to minimize pattern count and ATPG turn-around time reducing test costs dramatically.

REGISTER HERE

Webinar: 5 Expectations for the Manufacturing Market in 2026
2026-01-14 11:00 - 12:00 | This course will be held Online
Discover the 5 Critical Manufacturing Market Trends Reshaping Semiconductors in 2026
AI-driven investments, sustainability, and advanced materials—what’s next for semiconductor manufacturing.
The semiconductor manufacturing industry is undergoing a transformative period as AI-driven investments accelerate, sustainability pressures mount, and foundries navigate capacity expansion amid weak consumer demand.
In this live TechInsights webinar, our manufacturing experts will highlight five critical developments shaping semiconductor fabrication and equipment markets in 2026, offering actionable insights for strategists, foundry operators, and equipment suppliers.
Key Topics You’ll Learn

TSMC’s 2nm Mass Production Leadership – Achieving 7% of total capacity by 2026 while foundry/logic CAPEX rises for the first time since 2022.
China’s Role in Equipment Sales – Export control uncertainties and slower recovery extending into 2027, with fabrication emissions projected to reach 200M metric tons CO₂e.
Inventory Optimization & AI Growth – Leveraging oversupply in consumer, industrial, and automotive segments to focus on AI-driven production.
Glass Substrates Challenge Traditional Materials – Superior flatness, signal integrity, and sub-2-micron via capabilities for AI accelerators and HBM applications.
Wafer Fab Equipment Growth Focus – Concentration in microlithography for cutting-edge AI chips, with subsystem suppliers benefiting from Asian capacity expansions.

REGISTER HERE

Advanced Measurements Seminar - Calgary
2026-01-15 09:00 - 17:00 | Calgary, AB, Calgary, Alberta, Canada
About this event
Start the new year off right with fresh insights and sharp skills. Join Keysight experts in Calgary for an all-day Advanced Measurements Seminar and cocktail reception. This hands-on technical event features live demonstrations with the latest RF and high-speed digital technologies.
Gain practical, lab-ready insights to enhance accuracy, reduce uncertainty, and push your measurement capabilities further in 2026. Lunch and cocktails are on us.
Learn more and reserve your spot today!

Who should attend this event?
Ideal for RF and high-speed digital engineers looking to deepen their measurement expertise.

REGISTER HERE

Webinar: Accelerate IC Layout Parasitic Analysis with ParagonX
2026-01-15 10:00 - 12:00 | Online
We are pleased to offer two webinar sessions for your convenience. Please choose the time that best fits your schedule:
10:00AM – 12:00PM CET (session #1 for EMEA/APAC)
10:00AM – 12:00PM PST (session #2 for NA)
Featured Speakers:

Kopal Kulshreshtha, Principal Product Specialist, Synopsys
Rob Dohanyos, Principal Product Specialist, Synopsys

Introducing ParagonX, a powerful tool for intelligent analysis, debugging, simulation, and visualization of IC layout parasitics. It is perfect for root-cause analysis in top-level analog, custom digital, and mixed-signal designs.
Why You Should Attend:

Assess and quantify the effects of layout parasitics early in the design process.
Elevate your productivity with rapid iterations that guide layout optimizations.
Seamlessly integrate ParagonX into your analog and custom design workflow.

REGISTER HERE

Webinar: ASU-Silvaco Device TCAD Workshop: From Fundamentals to Applications
2026-01-16 09:30 - 17:30 | ASU Tempe Campus, ASU Tempe Campus, Old Main Building, 400 East Tyler Mall, Second Floor, Tempe, AZ, 85287, United States
This workshop is a fast-paced, one-day program led by Prof. Dragica Vasileska and Prof. Stephen M. Goodnick. Spend the morning grounding yourself in semiconductor physics and transport, then transition in the afternoon to instructor-led, hands-on Silvaco TCAD labs (e.g., MOS Capacitors, MOSFETs, SOI Devices, FinFETs).
The workshop is offered in a hybrid format. Participants have the option to join either in person at ASU or virtually via Zoom.
Attendees will learn to use Silvaco TCAD effectively and know how to select the appropriate physical models and material parameters for their devices. Whether you are an industry professional or student, you will leave with a practical grasp of semiconductor physics and the skills to use Silvaco TCAD effectively and efficiently. Complimentary lunch will be served, followed by a Silvaco overview and Digital Twin session from Silvaco’s VP of Worldwide Field Applications Engineering, Garrett Schlenvogt.
When: January 16, 2026
Time: 9:30am-5:30pm
Where: ASU Tempe Campus
Old Main Building
400 East Tyler Mall
Second Floor
Tempe, AZ, 85287
Seating is limited so register soon.
REGISTER HERE

SPIE Photonics West 2026
2026-01-17 - 2026-01-22 | San Francisco, CA, San Francisco, CA, United States
Share your work, insights, and breakthroughs. The 2026 call for papers is open.
SPIE Photonics West is the world’s largest optics and photonics technologies event. Present your research in biomedical optics, biophotonics, industrial lasers, optoelectronics, microfabrication, displays, quantum, and emerging vision technologies.
Conferences and Courses: 17–22 January
This is the place to be in January
Experience the benefits of attending SPIE Photonics West—networking with colleagues, learning the latest research, and experiencing the newest innovations make this the most exciting week in photonics. See for yourself.
Plan to take a course from an expert
Course offerings will give you the technical training you need to excel in your field. Choose from more than 55 courses in San Francisco during SPIE Photonics West. Adding a course to your registration adds to your entire event experience.
Five major exhibitions
Explore the companies that exhibit at the SPIE Photonics West Exhibition, BiOS Expo, AR | VR | MR Expo, and Quantum West Expo. These leading companies are providing new capabilities and innovative products to help move your projects forward. Plus, new this year, Vision Tech Expo is growing.
REGISTER HERE

IEEE Hybrid Bonding Symposium
2026-01-22 - 2026-01-23 | SEMI HQ, SEMI HQ, 673 S Milpitas Blvd., Milpitas, CA, 95035, United States
January 22-23, 2026, hosted by SEMI International, Silicon Valley, CA USA
Note: HBS’26 is a hybrid event, with both in-person and virtual participation via WebEx.
Download the Call for Presentations!
Hybrid Bonding has emerged as the technology of choice in the semiconductor and heterogeneous integration industries for ultra-fine-pitch interconnection. With significant benefits for interconnect density and device performance, it will become widely adopted for a broad range of high-performance semiconductor devices in the years to come. The success of Hybrid Bonding technology for high-volume manufacturing depends critically on the process technology as well as materials and equipment. Design, performance characterization, thermal management and reliability are also important considerations to enable applications in various areas.
Review the HBS’25 Program, and watch videos of most of the presentations.
Post-Symposium Report on the 2025 Hybrid Bonding Symposium
REGISTER HERE

Optical Design Engineering User Conference
2026-01-22 08:30 - 17:00 | San Francisco, CA, San Francisco, CA, United States
About this event
Stay connected with the latest optical design product innovations across CODE V, LightTools, RSoft, ImSym, and our optical scattering measurement solutions. Get tips and tricks on design best practices from our experts, and network with industry peers and the Keysight Optical Design Engineering team. The user conference is held in parallel with Photonics West, making it an ideal opportunity to deepen your expertise while connecting with the broader photonics community.

Who should attend this event?
Optical engineers using CODE V, LightTools, RSoft, ImSym, and our optical scattering measurement solutions.

REGISTER HERE

Webinar: Solving Timing closure challenges using Gencellicon (previously Excellicon)
2026-01-27 09:00 - 10:00 | Online
Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process.
What you will learn

The breadth of the entire Gencellicon portfolio
How timing closure solutions can alleviate your design process using Siemens tools

Who should attend

Implementation engineers
SoC architects
Design Verification teams
Test engineers
Power architects
Physical designers

Speaker:

Himanshu Bhatnagar
Senior Director, Siemens EDA

Himanshu brings over 20 years of expertise in chip design, having developed complex SoCs across networking, communications, imaging, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis, a practical guide to synthesis and static timing analysis. Before founding Excellicon, now Gencellicon, Himanshu held key positions at leading semiconductor companies, including Mindspeed Technologies, Conexant Systems, and ST Microelectronics. At Conexant Systems, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally, Himanshu has served as an advisor to various EDA companies.

REGISTER HERE

Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
2026-01-28 10:00 - 11:00 | Online
In this webinar, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks.
We will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout.
We will show you how these tools work on real designs as well.
WHO SHOULD ATTEND THIS WEBINAR?
If you are designing chips to deploy in networked environments, you need to understand the risks ahead and how to minimize them.
If you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions.
SPEAKERS
Beau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies
Dr. Paul Calzada will take you through a live demonstration of CODAx, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions.
* This webinar is in partnership with SemiWiki and Caspia Technologies
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2026 IEEE International Solid-State Circuits Conference (ISSCC)
2026-02-15 - 2026-02-19 | San Francisco Marriott Marquis, San Francisco Marriott Marquis, 780 Mission Street, San Francisco, CA, 94103, United States
About ISSCC
The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts.
What’s New

Download the ISSCC 2026 Plenary/Educational Events Flyer
The ISSCC 2026 paper submission site is now open
Download the ISSCC 2026 Call for Papers

REGISTER HERE

Chiplet Summit 2026
2026-02-17 - 2026-02-19 | Santa Clara Convention Center, Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
All the Solutions for Developing Chiplets
2025 Keynote Addresses from Industry Leaders:
Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne
2025’s Main Topics Included:
AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries
signup to be a 2026 SPONSOR / Exhibitor
REGISTER HERE

Wafer-Level Packaging Symposium 2026
2026-02-18 - 2026-02-20 | Hyatt Regency San Francisco Airport, 1333 Bayshore Highway, Burlingame, CA, 94010, United States
Formatting Advanced Packaging for the Next Generation
The evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package technologies beyond conventional limits. The Wafer-Level Packaging Symposium will bring together the foremost experts in the semiconductor industry to examine all aspects of wafer and panel-level packaging, 3D device packaging, advanced manufacturing, and testing technologies. Positioned at the forefront of packaging technology evolution, this conference offers global attendees the chance to engage with the latest technological and business trends in the heart of Silicon Valley.
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Semitracks Course: Defect-Based Testing
2026-02-19 - 2026-02-20 | Munich, Germany, Munich, Germany
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior, fault models, and test techniques. This course is a must for every manager, engineer, and technician working in IC test, IC design, or supplying test hardware and software tools to the industry.
By focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior, participants will learn how to design, write, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about defect-based testing. This skill-building series is divided into four segments:

Electrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits, resistive vias, shorts, and transistor variations affect the electrical behavior of the individual transistor, as well as gate elements and larger blocks.
Fault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models, including IDDQ testing, at-speed testing, and delay testing.
Production Test Methods. Participants will learn about standard digital testing, SAF testing, IDDQ, timing, low voltage tests, and other types of stress tests. They will explore the strengths and weaknesses of each test type.
The Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.

Course Objectives

This course will provide participants with an in-depth understanding of defect-based testing and its technical issues.
Participants will understand the basic concepts of test economics, yield, test time, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.
This course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.
This course will offer the opportunity to discuss specific test problems with our expert instructors.
Participants will be able to identify basic and advanced principles for defect-based test.
Participants will understand the difficulties in extending IDDQ testing to leading edge products, and how to overcome some of these limitations.
Participants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.
This course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.
Participants will learn what tools are available today to implement defect-based testing.

REGISTER HERE

SPIE Advanced Lithography + Patterning 2026
2026-02-22 - 2026-02-26 | San Jose McEnery Convention Center, San José McEnery Convention Center, 150 W San Carlos St, San Jose, CA, 95113, United States
From materials to metrology: pushing the limits of lithography
Share your research, challenges, and breakthroughs at this leading semiconductor conference in San Jose
Submit your abstract and connect with leading researchers advancing solutions in optical lithography, EUVL, patterning technologies, metrology, and process integration for semiconductor manufacturing and related applications.
Call for papers is now open.
REGISTER HERE

2026 Florida Semiconductor Summit
2026-02-23 - 2026-02-25 | Rosen Shingle Creek, Rosen Shingle Creek, 9939 Universal Blvd, Orlando, FL, 32819, United States
FSI presents the 4th annual Florida Semiconductor Summit in 2026. Join industry leaders, innovators, and exhibitioners as we explore groundbreaking developments and the evolving future of semiconductor manufacturing in Florida.
You’re invited to the 2026 Florida Semiconductor Summit! From February 23rd – 25th, 2026, the Florida Semiconductor Institute is hosting the fourth annual Florida Semiconductor Summit at the Rosen Shingle Creek. This year’s summit theme is “Semiconductor Manufacturing in Florida: Power. Progress. Possibilities.” This summit offers a unique opportunity to connect with industry leaders, explore cutting-edge advancements, and delve into the evolving role of semiconductor manufacturing in the state of Florida.
What Makes this Year’s Summit the Biggest Yet?
This year, we are taking the summit to the next level! Not only are we bringing together industry leaders from top CEOs to leading academics, we are bringing together rising startups and industry pioneers who are shaping the future of semiconductor technology in our first ever interactive exposition hall. This is your chance to connect with key decision-makers, gain insights from cutting-edge research, and explore new business opportunities in one of Florida’s fastest-growing sectors. The summit offers invaluable networking, knowledge-sharing, and a front-row seat to innovations that will have deep impacts on the state of Florida. Don’t miss out, register today!
REGISTER HERE

Semitracks Course: Wafer Fab Processing
2026-02-23 - 2026-02-26 | Munich, Germany, Munich, Germany
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Wafer Fab Processing is a 4-day course that offers an in-depth look into the semiconductor manufacturing process, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique, and we delve into the current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.
By focusing on the basics of each processing step and the issues surrounding them, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

What Will I Learn By Taking This Class?
Participants will learn basic, but powerful, aspects about the semiconductor industry. This skill-building series is divided into three segments:

Basic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. Participants will learn the fundamentals of each processing step and why they are used in the industry today.
The Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants will learn how each technique has evolved for use in previous and current generation ICs.
Current Issues in Wafer Fab Processing. Participants will learn how many processing steps are increasingly constrained by physics and materials science. They will also learn about the impact of using new materials in the fabrication process, and how those materials may create problems for the manufacturers in the future.

This course is a must for every manager, engineer, and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

Course Objectives

This course will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.
Participants will understand the basic concepts behind the fundamental wafer fab processing steps.
This course will identify the key issues related to each of the processing techniques, and their impact on the continued scaling of the semiconductor industry.
This course will offer a wide variety of sample problems that participants will work to help them gain knowledge of the fundamentals of wafer fab processing.
Participants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition, ion implantation, lithography, and etching.
Participants will understand how processing, reliability, power consumption and device performance are interrelated.
Participants will be able to make decisions about how to construct and evaluate processing steps for CMOS, BiCMOS, and bipolar technologies.

REGISTER HERE

FLEX 2026 - Technology Summit
2026-02-24 - 2026-02-26 | The WIGWAM, The Wigwam, 300 E Wigwam Blvd, Litchfield Park, AZ, 85340, United States
FLEX 2026 | TECHNOLOGY SUMMIT | FEBRUARY 24-26, 2026
THE WIGWAM ARIZONA RESORT | PHOENIX, AZ
A 25th Anniversary Celebration
Escape the winter and celebrate 25 years of innovation with us at The Wigwam Arizona Resort in Phoenix, AZ.

FLEX—Technology Summit is a vibrant networking event designed to foster community building. Connect with like-minded professionals, share ideas, and forge lasting relationships that will drive the industry forward.
At FLEX, you’ll experience high-quality technical sessions led by industry-leading speakers who are at the forefront of their fields. Sessions include topics on wearable and harsh environment technologies, heterogeneous integration and advanced packaging, flexible hybrid electronics, printed electronics, additive manufacturing, integrated photonics, flexible displays, digital twins, artificial intelligence, and manufacturing. Additionally, you’ll gain valuable business insights and market trends that provide a comprehensive view of the state of the industry.
Explore the solution zone to see cutting-edge technologies and connect with innovations shaping the future. Don’t miss this chance to stay ahead in a rapidly evolving tech landscape.
REGISTER HERE
