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DTSTART;TZID=America/Los_Angeles:20260203T090000
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DTSTAMP:20260428T230146
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SUMMARY:Webinar: From C++ to Silicon: Fast\, Physically Aware\, AI-Driven Exploration with Rise Design Automation and Precision Innovations
DESCRIPTION:As hardware designs grow more complex\, architectural exploration is increasingly critical to delivering differentiated silicon. Teams frequently develop promising architectures only to discover late in the cycle that physical implementation is too costly or fails to meet key specifications. This challenge intensifies as designers integrate new accelerators — video\, audio\, ML\, or custom datapaths — rapidly expanding the search space. \nAI-based automation can help\, but only when each exploration trial provides cost metrics (area\, timing\, power) that are both fast and credible. Traditional parameter sweeps are slow. Full physical analysis is expensive. And without correlation to real implementation costs\, AI-guided exploration can simply produce the wrong answers faster. \nRise Design Automation and Precision Innovations are partnering to change this dynamic. Together\, they deliver fast\, accurate\, physically aware exploration loops — ideal for reinforcement learning\, iterative refinement\, and high-volume experimentation. \nRise Design Automation provides 10× faster High-Level Synthesis (HLS) with timing and area correlation within a few percent of downstream RTL-synthesis results. The Rise toolchain can also execute downstream tools “under the hood” and incorporate their feedback directly into HLS. Integrating Precision Innovations’ industry ready OpenROAD-based RTL→GDSII flow and OpenROAD Flow Scripts adds production-grade physical estimation with strong area and timing accuracy validated down to advanced nodes (including 2–3nm). \nCombined\, this integrated flow enables rapid exploration from high-level C++/SystemC/SystemVerilog through synthesized RTL to physically correlated PPA — supporting hundreds or thousands of trials without licensing barriers. \nThis session demonstrates how an integrated\, AI-driven architectural exploration solution from Rise Design Automation and Precision Innovations provides rapid\, actionable feedback to guide design decisions\, and how you benefit from these capabilities in your own design flow. \n\n\n\n\n\n\n\n\nWhat You’ll Learn\n\n\n\n\nIn this technical deep dive\, you’ll see how Rise Design Automation and Precision Innovations help you: \n\nRun AI-guided architectural exploration with fast\, physically grounded cost metrics\nModel and explore designs in C++\, SystemC\, or SystemVerilog and automatically generate multiple RTL variants\nUse Rise’s fast\, correlated HLS engine to accelerate exploration with credible RTL-level PPA\nLeverage Precision’s OpenROAD-based RTL→GDSII flow for production-grade physical estimation — enabling early visibility into area\, timing\, and implementation feasibility\nApply reinforcement learning and design agents to guide the search toward optimal architectures\nScale exploration across hundreds or thousands of trials without restrictive per-run licensing\n\nThis webinar highlights practical techniques to accelerate exploration\, increase confidence\, and improve architectural decisions earlier in the design process. \n\n\n\n\nLive Demonstration\n\n\n\n\nSee a complete exploration loop from high-level behavioral model through Rise Design Automation’s HLS\, through RTL synthesis\, and into Precision Innovations’ OpenROAD-based physical estimator — with AI-guided refinement driven by real PPA feedback \n\n\n\n\nWho Should Attend:\n\n\n\n\nHardware architects\, design engineers\, verification leads\, and research teams who want to: \n\nAccelerate architectural exploration for complex accelerators\nApply AI/ML or reinforcement-learning workflows to silicon design\nImprove correlation between high-level design\, RTL\, and physical estimates\nConfidently explore many architectural options without slow iteration loops\nShift verification and physical awareness earlier in the flow\nDeploy scalable exploration without restrictive per-run licensing\n\nWhether you’re adding a new accelerator to an SoC or exploring ML-driven design automation\, this session provides a practical foundation for leveraging Rise + Precision. \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-from-c-to-silicon-fast-physically-aware-ai-driven-exploration-with-rise-design-automation-and-precision-innovations/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-13-181938.png
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DTSTART;TZID=America/Los_Angeles:20260128T100000
DTEND;TZID=America/Los_Angeles:20260128T110000
DTSTAMP:20260428T230146
CREATED:20251211T205410Z
LAST-MODIFIED:20251211T205410Z
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SUMMARY:Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
DESCRIPTION:In this webinar\, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks. \nWe will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout. \nWe will show you how these tools work on real designs as well. \nWHO SHOULD ATTEND THIS WEBINAR?\nIf you are designing chips to deploy in networked environments\, you need to understand the risks ahead and how to minimize them. \nIf you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions. \nSPEAKERS\nBeau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies \nDr. Paul Calzada will take you through a live demonstration of CODAx\, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions. \n* This webinar is in partnership with SemiWiki and Caspia Technologies \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-why-ai-assisted-security-verification-for-chip-design-is-so-important/
LOCATION:Online
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DTSTART;TZID=America/Los_Angeles:20260128T090000
DTEND;TZID=America/Los_Angeles:20260128T170000
DTSTAMP:20260428T230146
CREATED:20260113T042846Z
LAST-MODIFIED:20260113T042846Z
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SUMMARY:Power Seminar - Burnaby
DESCRIPTION:About this event\nAs power levels rise and systems scale\, high-power testing becomes more complex and time-consuming. This hands-on Power Solutions Seminar focuses on practical test strategies for batteries\, fuel cells\, green energy\, and power conversion. \nYou will experience expert-led technical sessions with hands-on\, real-world application insights. Explore Keysight’s three new High-Power ATE System Supplies and demos across our power portfolio to improve test efficiency\, accuracy\, and development speed. \n\n\n\n\n\n\n\nWho should attend this event?\nThis event is designed for development engineers in power electronics\, battery systems\, and green energy. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/power-seminar-burnaby/
LOCATION:Burnaby\, BC\, Burnaby\, British Columbia\, Canada
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-202823.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260128
DTEND;VALUE=DATE:20260129
DTSTAMP:20260428T230146
CREATED:20260113T043124Z
LAST-MODIFIED:20260113T043124Z
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SUMMARY:Webinar: Powering the Future: Megawatt Charging Solutions for Heavy-Duty Electrification
DESCRIPTION:About this event\nJoin our upcoming webinar to discover how Keysight is powering the future of heavy-duty electric transportation with advanced megawatt-charging test solutions. \nLearn how to validate ultra-high-power delivery beyond 3 MW\, ensure compliance with MCS and ISO 15118-20\, and streamline interoperability testing\, all within a single\, fully controllable platform designed for both compliance and development debugging. \nWe’ll explore how seamless integration of software\, hardware\, and project services accelerates the deployment of safe\, scalable\, and standards-driven charging infrastructure for trucks\, ships\, and heavy machinery. \n\n\n\n\n\n\n\nWho should attend this event?\nThose involved in the shift towards a future-proven transportation\, logistics\, and construction ecosystem. Specific titles: OEM Electrification Leaders; EVSE Manufacturers & Charging Infrastructure Developers; Compliance & Standards Specialists; Fleet Electrification Managers: Grid Integration & Energy Management Specialists. \n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-powering-the-future-megawatt-charging-solutions-for-heavy-duty-electrification/
LOCATION:Virtual
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/01/Screenshot-2026-01-12-203022.png
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