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DTSTART;VALUE=DATE:20261027
DTEND;VALUE=DATE:20261030
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SUMMARY:IEEE International Conference on PHYSICAL ASSURANCE and INSPECTION of ELECTRONICS (PAINE)
DESCRIPTION:ABOUT PAINE\n\n\n\n\nPhysical inspection of electronics has grown significantly over the past decade and is becoming a major focus for the chip designers\, original equipment manufacturers\, and system developers. The complex long life of the electronic devices coupled with their diverse applications is making them increasingly vulnerable to various forms of threats and inspection. Large industry and government efforts have been put in place across the globe to address related supply chain security problems to offer solutions\, training\, and services. The number of programs introduced by the US government has increased over the years to analyze and develop relevant solutions. Although much focus is given to the digital domain\, physical assurance and inspection of electronics as well as physical fingerprinting based on analog parameters are rapidly providing opportunities for unique countermeasures. \nPAINE conference provides a unique venue for all researchers and practitioners from academia\, industry\, and government to have productive dialog on such topics. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. PAINE covers the broad topic of hardware security and trust; example topics of interest include but are not limited to: \n\n\n\n\n\n\n\n\n\nTopics to be Covered:\n\n\nNew metrologies for characterization and assurance\nAdvanced packaging and heterogeneous integration\nEmerging topics in physical inspection and assurance\nImage analysis and artificial intelligence for assurance and inspection\nMetrologies characterization\nAutomated inspection and metrology for advanced packaging\nSecurity primitives: Novel devices\, materials\, and systems\nTest vehicles and performance quantification\nAdditive manufacturing assurance for electronics\nPhysical and design interface assurance\nTrojans and backdoors: Detection and prevention\n\n\nWorkforce Development\nFault injection assessment and countermeasures\nSide channel assessment (power\, timing\, EM)\nAnalog & mixed-signal circuits and systems security\nFPGA Bitstream protection and vulnerabilities\nCounterfeit Detection and Anti-Counterfeit Technique\nNovel material and devices for assurance\nSample Preparation\nPCB trust and assurance\nChip and PCB level decomposition for assurance\nFIB/SEM for assurance\n\n\nElectro-optical probing using PEM\, EOP\, EOFM\, etc.\nPhysical/side channel fingerprinting\nMod-chip on PCB\nMicroprobing and nanoprobing\nBus-snooping\nField-based weakness\nCountermeasures against tampering and decomposition\nFunctionality validation\nProcess improvements\nFailure analysis and fault isolation\nPhysical/logical shielding etc.\nPhotonics Assurance\n\nREGISTER  HERE
URL:https://semiwiki.com/event/ieee-international-conference-on-physical-assurance-and-inspection-of-electronics-paine/
LOCATION:Phoenix\, AZ\, Phoenix\, AZ\, United States
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DTSTART;VALUE=DATE:20261027
DTEND;VALUE=DATE:20261030
DTSTAMP:20261023T082926Z
CREATED:20261023T082926Z
LAST-MODIFIED:20261023T082926Z
UID:375340-1793059200-1793318399@semiwiki.com
SUMMARY:C-TOUCH & DISPLAY 2026
DESCRIPTION:C-TOUCH & DISPLAY 2026\n\n\n\n\nC-TOUCH & DISPLAY 2026 will be held at Shenzhen World Convention and Exhibition Center from October 27 – 29\, 2026 \nAs Asia’s leading B2B trade show\, it focuses on the latest smart touch and display technologies\, bringing together top industry leaders\, innovative manufacturers\, and cutting-edge solutions. \nThe exhibition covers a wide range of applications\, including consumer electronics\, automotive displays\, Infotainment Screen\, Car Screen\,  industrial control\, medical technology\, and more. \nThis is a must-attend event for professionals looking to explore emerging trends\, network with global experts\, and drive business growth in the fast-evolving display technology sector. \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/c-touch-display-2026/
LOCATION:Shenzhen World Exhibition and Convention Center\, Shenzhen World Exhibition and Convention Center\, Shenzhen\, Baoan\, China
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/10/images-2.jpg
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BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20261028T080000
DTEND;TZID=America/Los_Angeles:20261028T090000
DTSTAMP:20261015T064436Z
CREATED:20261015T064436Z
LAST-MODIFIED:20261015T064436Z
UID:374921-1793174400-1793178000@semiwiki.com
SUMMARY:Webinar: The "bridge" to scale for AI and HPC applications
DESCRIPTION:Designing high-performance multi-chiplet semiconductor packages for hyperscale\, HPC and AI applications combines cutting-edge innovation with practical optimization. Embedded silicon bridge substrates enable cost-effective solutions by using base substrates such as organic laminates or redistribution-layer (RDL) buildup\, helping overcome the reticle-size and cost limitations of monolithic silicon substrates. \nEmbedded silicon bridges provide power-efficient\, high-speed connections between chiplets and memory\, delivering the massive bandwidth required for AI parallelism and hyperscale/HPC energy-efficiency demands. Key challenges remain\, including inter-chiplet connectivity\, thermal dissipation and power integrity. \nIn this webinar\, Siemens EDA and Intel Foundry will introduce embedded bridge technology and its market applications. Intel Foundry will present its EMIB and EMIB-T technology offerings\, followed by a demonstration of the Siemens reference flow for Intel Foundry EMIB and EMIB-T technologies. \nWhat you will learn: \n\nWhat is driving the demand for more than Moore in IC design\nHow substrate-embedded silicon bridges enable efficient\, cost-effective heterogeneous integration and silicon scaling\nAn introduction to Intel Foundry’s proven Embedded Multi-die Interconnect Bridge (EMIB) technologies\nHow a single-vendor\, integrated and certified workflow supports Intel Foundry EMIB and EMIB-T technologies\n\nWho should attend: \n\nIC and IC package verification managers and directors\nIC and IC package design managers and 3D IC program leads\nCAD and methodology managers\nIC\, chiplet\, semiconductor package and substrate designers\nSystem and micro architects\nVerification engineers working in physical verification\, SI/PI\, reliability\, thermal and stress analysis\n\nProducts covered: \n\nInnovator3D IC Integrator\nQuesta FormalPro\nCalibre 3DThermal\nCalibre 3DStack\nInnovator3D IC Layout\nHyperLynx SI/PI\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-the-bridge-to-scale-for-ai-and-hpc-applications/
LOCATION:Online
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DTSTART;TZID=America/Los_Angeles:20261028T100000
DTEND;TZID=America/Los_Angeles:20261028T110000
DTSTAMP:20261020T034311Z
CREATED:20261020T034311Z
LAST-MODIFIED:20261020T034311Z
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SUMMARY:Webinar: Accelerating Formal Verification Using Non-Determinism
DESCRIPTION:Webinar Overview:\nThe use of non-determinism with formal is how formal is able to manage large state spaces and still arrive at a quick solution. Non-determinism plays a part in writing our formal constraints\, formal targets\, and formal abstractions. \nThis webinar will explain what non-determinism is\, how it’s used\, and show lots of examples so you can take advantage of non-determinism to accelerate the verification of your designs. \nIt is partnered with Synopsys and all of the examples can be used in VC Formal. \nAttendance is FREE and live Q&A will be provided throughout the broadcast. \n\n\n\n\n\n\nDoug Smith – Design & Verification Expert – will present this training webinar\, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout. \n\n\n\n\n\n\n\n\nAttendance is free of charge \nIf you have any queries\, please contact webinars@doulos.com \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-accelerating-formal-verification-using-non-determinism/
LOCATION:Online
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