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DTSTART;VALUE=DATE:20260914
DTEND;VALUE=DATE:20260916
DTSTAMP:20260707T021443Z
CREATED:20260707T021443Z
LAST-MODIFIED:20260707T021443Z
UID:370970-1789344000-1789516799@semiwiki.com
SUMMARY:IC Packaging Technology
DESCRIPTION:Integrated Circuit packaging has always been integral to IC performance and functionality. An IC package serves many purposes: 1) pitch conversion between the fine features of the IC die and the system level interconnection; 2) chemical\, environmental and mechanical protection; 3) heat transfer; 4) power\, ground and signal distribution between the die and system; 5) handling robustness; and 6) die identification among many others. Numerous critical technologies have been developed to serve these functions; technologies that continue to advance with each new requirement for cost reduction\, space savings\, higher speed electrical performance\, finer pitch\, die surface fragility\, new reliability requirements\, and new applications. Packaging engineers must fully understand these technologies to design and fabricate future high-performance packages with high yields at exceptional low-costs to give their company a critical competitive advantage. \nIC Packaging Technology is a 2-day course that details the vital technologies required to construct IC packages in a reliable\, cost effective\, and quick time to market fashion. When completed\, the participant will understand the wide array of technologies available; how technologies interact; what choices must be made for a high-performance product vs. a consumer device; and how such choices impact the manufacturability\, functionality\, and reliability of the finished product. An emphasis will be given to manufacturing; processes; and materials selection\, tailoring\, and development. Each fundamental package family will be discussed\, including flip chip area array technologies\, Wafer Level Packaging (WLP)\, Fan-Out Wafer Level Packaging (FO-WLP)\, and the latest Through Silicon Via (TSV) developments. Additionally\, future directions for each package technology will be highlighted\, along with challenges that must be surmounted to succeed. \n\n\nWhat Will I Learn By Taking This Class?\nBy focusing on current issues in packaging technology\, participants will learn why advances in the industry are occurring along certain lines and not others. Participants will learn about semiconductor packaging without having to delve heavily into the complex physics and materials science that normally accompany this discipline. Participants will learn basic\, but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments: \n\nMolded Package Technologies. Participants will learn the fundamentals of molding critical to leaded\, leadless\, and area array packaging\, enabling them to eliminate problems such as flash\, incomplete fill\, and wire sweep.\nFlip Chip Technologies. Participants will learn the fundamentals of plating\, bumping\, reflow\, underfill\, and substrate technologies that are required for both high performance and portable products.\nWafer Level Packages. Participants will learn the newest technologies that enable the increasingly popular Wafer Chip Scale Packages (WCSPs) and Fan-Out Wafer Level Packages (FO-WLPs).\nThrough Silicon Via Packages and Future Directions. Participants will understand the latest advances in the recently productized TSV technology\, as well as future directions that will lead to the products of tomorrow.\n\n\n\n\n\nCourse Objectives\n\nThe course will supply participants with an in-depth understanding of package technologies\, current and future.\nPotential defects associated with each package technology will be highlighted to enable the participants to identify and eliminate such issues in product from both internal assembly and OSAT houses.\nCu and solder plating technologies will be described with special emphasis on package applications in Through Silicon Vias (TSVs) and Cu pillars for FO-WLPs. Emphasis will be placed on eliminating issues such as reliability\, non-uniformity\, void-free thermal aging performance\, and contamination-free interfaces.\nNew package processes employed in TSV production will be described\, along with current cost reduction thrusts\, to enable the participants to understand the advantages and limits of the technologies.\nTemporary bonding and wafer thinning processes will be highlighted\, as well as the cost reduction approaches currently being pursued to enable wider adoption of TSV packages.\nThe trade-offs between silicon\, glass\, and organic interposers will be highlighted\, along with the processes used for each.\nParticipants will gain an understanding of the surface mount technologies that enable today’s fine pitch products.\nThis course will provide detailed references for participants to study and further deepen their understanding.\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/ic-packaging-technology/
LOCATION:Online
ORGANIZER;CN="Semitracks%2C Inc.":MAILTO:info@semitracks.com
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DTSTART;TZID=America/Los_Angeles:20260914T093000
DTEND;TZID=America/Los_Angeles:20260914T133000
DTSTAMP:20260804T025958Z
CREATED:20260804T025958Z
LAST-MODIFIED:20260804T025958Z
UID:371918-1789378200-1789392600@semiwiki.com
SUMMARY:Advanced Measurements Seminar – Waterloo
DESCRIPTION:Hosted in collaboration with Professor Slim Boumaiza\, Director of the Centre for Intelligent Antenna and Radio Systems (CIARS) at the University of Waterloo. \nAs RF systems continue to evolve with wider bandwidths and higher frequencies\, engineers are navigating faster plays\, tighter margins\, and more complex signals than ever before. The challenge is no longer capturing signals\, it is turning those measurements into meaningful insights that accelerate design and validation. \nJoin Dr. Joel Dunsmore and fellow Keysight R&D experts for an interactive\, in-person seminar focused on the latest innovations in vector network analysis\, advanced signal generation\, and next-generation signal analysis. Through practical demonstrations\, application-focused sessions\, and expert best practices\, you’ll learn how to skate past signal complexity to score clearer insights. \nStep onto the ice with Keysight experts and explore: \n\nBreaking the 250 GHz Barrier with Keysight’s vector network analyzers\nCreating the Perfect Signal: Advanced signal generation for next-generation RF systems\nPrecision RF Validation for Next-Generation Wi-Fi Systems featuring the new Keysight XA5 Signal Analyzer\nCapturing the Full Signal: Wideband analysis for satellite communications featuring the new Keysight XA6 Signal Analyzer\n\nWhether you’re developing next-generation wireless\, aerospace and defense\, semiconductor\, or other advanced RF systems\, you’ll leave with practical techniques and a deeper understanding of the latest RF measurement technologies to help validate designs with greater speed\, accuracy\, and confidence. \nREGISTER HERE
URL:https://semiwiki.com/event/advanced-measurements-seminar-waterloo/
LOCATION:University of Waterloo – Centre for Environmental and Information Technology (EIT)\, University of Waterloo - Centre for Environmental and Information Technology (EIT)\, Ring Rd\, Waterloo\, Ontario\, N2L 3G1\, Canada
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