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X-WR-CALDESC:Events for SemiWiki
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DTSTART;VALUE=DATE:20260908
DTEND;VALUE=DATE:20260912
DTSTAMP:20260616T210718Z
CREATED:20260616T210718Z
LAST-MODIFIED:20260616T210718Z
UID:370385-1788825600-1789171199@semiwiki.com
SUMMARY:SPIE Photomask Technology + Extreme Ultraviolet Lithography
DESCRIPTION:Join your colleagues in Monterey for the premier worldwide photomask conference \n\nWe invite you to explore the latest advances and breakthroughs at this annual conference in Monterey\, California. Connect with leading scientists and engineers and discover new work across photomasks\, patterning\, metrology\, materials\, inspection and repair\, mask business\, extreme ultraviolet lithography\, and emerging technologies. \nConnect with top suppliers at the free two-day exhbition \nDiscuss your product requirements with top suppliers showcasing the newest products and innovations \nIndustry partners will be there to help solve problems\, cut costs\, and increase capabilities. \n\nREGISTER HERE
URL:https://semiwiki.com/event/spie-photomask-technology-extreme-ultraviolet-lithography/
LOCATION:Monterey\, CA\, Monterey\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/06/Screenshot-2026-06-16-140652.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260908
DTEND;VALUE=DATE:20260912
DTSTAMP:20260903T065917Z
CREATED:20260903T065917Z
LAST-MODIFIED:20260903T065917Z
UID:373086-1788825600-1789171199@semiwiki.com
SUMMARY:SPIE Photomask Technology + Extreme Ultraviolet Lithography 2026
DESCRIPTION:Join your colleagues in Monterey for the premier worldwide photomask conference \n\nWe invite you to explore the latest advances and breakthroughs at this annual conference in Monterey\, California. Connect with leading scientists and engineers and discover new work across photomasks\, patterning\, metrology\, materials\, inspection and repair\, mask business\, extreme ultraviolet lithography\, and emerging technologies. \nConnect with top suppliers at the free two-day exhbition \nDiscuss your product requirements with top suppliers showcasing the newest products and innovations \nIndustry partners will be there to help solve problems\, cut costs\, and increase capabilities. \nConferences: 8–11 September 2026 | Exhibition: 9–10 September 2026 | Courses: 9 September 2026 \n\nREGISTER HERE
URL:https://semiwiki.com/event/spie-photomask-technology-extreme-ultraviolet-lithography-2026/
LOCATION:Monterey\, CA\, Monterey\, CA\, United States
ATTACH;FMTTYPE=image/png:https://semiwiki.com/wp-content/uploads/2026/09/Screenshot-2026-09-02-235846.png
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260909
DTEND;VALUE=DATE:20260910
DTSTAMP:20260903T084456Z
CREATED:20260903T084456Z
LAST-MODIFIED:20260903T084456Z
UID:373219-1788912000-1788998399@semiwiki.com
SUMMARY:Webinar: One TMR tech\, two ways to sense: Infineon extends its TMR-based portfolio
DESCRIPTION:About the webinar\n\n\n\n\n\n\n\n\nInfineon is extending its XENSIV™ magnetic sensing portfolio with tunnel magnetoresistance (TMR)-based sensors designed to help engineers achieve high-precision\, low-noise and low-power magnetic sensing in compact systems. In this webinar\, we will give designers a crisp overview of the latest TMR product releases and explain how Infineon’s TMR technology can support position- and current-sensing applications where sensitivity\, signal quality\, fast response and design flexibility matter. Sign up to learn how you can increase performance across consumer\, industrial and automotive industries with the newest lineup. \nThe webinar will cover the fundamentals of TMR and the differences between compass mode and linear mode sensing. We will also show how the latest additions to Infineon’s TMR portfolio address key design needs such as \n\nhigh bandwidth and fast reaction time\,\nultra-low power consumption\,\nhigh resolution for speed sensing\, and\nhigh SNR and sensitivity for applications such as gaming and HMI.\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nKey takeaways:\n\n\n\n\n\n\n\n\n\nUnderstand how Infineon’s TMR technology complements our Hall\, AMR and GMR sensing portfolio and enables highly sensitive magnetic measurements with strong signal quality.\nGet a compact overview of the latest TMR-based product releases and how they enhance position\, speed and current sensing designs.\nLearn the practical design differences between compass mode and linear mode sensors\, including what they can detect\, their operating range considerations and their system value.\nExplore how linear TMR designs support precise position sensing\nDiscover which XENSIV™ TMR sensor characteristics matter most for different design goals\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-one-tmr-tech-two-ways-to-sense-infineon-extends-its-tmr-based-portfolio/
LOCATION:Online
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BEGIN:VEVENT
DTSTART;VALUE=DATE:20260909
DTEND;VALUE=DATE:20260911
DTSTAMP:20260904T083857Z
CREATED:20260904T083857Z
LAST-MODIFIED:20260904T083857Z
UID:373293-1788912000-1789084799@semiwiki.com
SUMMARY:Webinar: Introducing Ansys TPT\, Embedded Software Testing
DESCRIPTION:Discover how to transform your embedded software testing with Ansys TPT\, reducing cost\, improving quality\, and accelerating validation across all test levels. You’ll also explore how TPT\, combined with SCADE\, enables a seamless\, scalable design-to-test workflow for modern\, safety-critical systems. \n\n\n\n\nDate/Time: \nSession 1:\nSeptember 9\, 2026\n9 AM CET | 4 PM KST \nSession 2:\nSeptember 10\, 2026\n6 PM CET | 9 AM PST | 12 PM EST \n\n\nOverview\nEmbedded software testing is becoming increasingly complex\, costly\, and difficult to scale. As systems evolve and safety standards tighten\, traditional approaches struggle to keep pace\, leading to high maintenance effort\, fragmented tool chains\, and delayed feedback that slows development. \nIn this webinar\, discover Ansys TPT\, a next-generation test automation solution designed to accelerate embedded software validation. TPT supports the full testing lifecycle\, from model-in-the-loop (MiL) and software-in-the-loop (SiL) to system-level validation\, enabling teams to test models\, code\, and integrated systems in a unified environment. \nYou will learn how TPT reduces testing time through automation\, reusability\, and a unique architecture that minimizes maintenance overhead\, helping teams iterate faster and move validation earlier in the cycle. \nThe session will also highlight the combined value of TPT and SCADE. Requirement-based testing and the separation of stimuli and expected behavior enable rapid\, scalable test design\, while integrated workflows accelerate validation without compromising traceability and coverage. \nBy combining automation\, advanced test design\, and seamless integration\, TPT empowers engineering teams to deliver software faster\, turning testing into a driver of development speed and time-to-market. \nAutomatic traceability and test result reporting support functional safety standards such as ISO 26262 by ensuring end-to-end traceability between safety requirements\, test cases\, and test outcomes\, enabling complete verification coverage\, audit readiness\, and improved functional safety. \n\n\n\n\nWhat Attendees Will Learn\n\nHow to reduce testing cost and effort with scalable automation\nHow to unify testing across MiL\, SiL\, HiL\, and system levels\nHow to improve test coverage\, reuse\, and productivity\nWhy TPT + SCADE enables a seamless design-to-test workflow\nHow to enhance traceability and compliance for safety-critical systems\n\n\n\n\n\nWho Should Attend\n\nTest Engineers / Validation Engineers\nTest Managers / Heads of Testing Departments\nEmbedded Software Engineers / Developers\nSystem Engineers working with model-based design\nEngineering IT / Toolchain & CI/CD Specialists\nProject Managers overseeing software validation\nSCADE users and model-based design practitioners\nTeams involved in safety-critical software (automotive\, aerospace\, industrial)\n\n\n\n\n\nSpeakers\n\nNeeraja Vemulapalli – Product Management\, Director\, Synopsys\nStefan Lachmann – Technical Product Management\, Sr Staff Engineer\, Synopsys\nFrançoix-Xavier Dormoy – Product Management\, Sr Staff\, Synopsys\n\n\n\n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-introducing-ansys-tpt-embedded-software-testing/
LOCATION:Online
ATTACH;FMTTYPE=image/webp:https://semiwiki.com/wp-content/uploads/2026/09/tpt-featured-image.webp
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DTSTART;TZID=America/Los_Angeles:20260909T090000
DTEND;TZID=America/Los_Angeles:20260909T100000
DTSTAMP:20260804T025655Z
CREATED:20260804T025655Z
LAST-MODIFIED:20260804T025655Z
UID:371916-1788944400-1788948000@semiwiki.com
SUMMARY:Webinar: CODE V Discovery Training
DESCRIPTION:Online via Teams\n\n\n\nThis discovery training introduces CODE V\, a premium optical design software. \nCODE V enables engineers to design\, analyze\, and optimize optical systems such as camera lenses\, telescopes\, and photonics devices. It features advanced ray tracing\, diffraction analysis\, and powerful optimization engine. In addition\, CODE V offers fast and accurate tolerancing\, which helps engineers predict how well a design will perform once it is manufactured. \nWhat You Will Learn: \n\nUnderstand what CODE V is and how CODE V can help you\nIdentify key considerations in imaging system design\nGain a high-level view of the CODE V interface and workflow\n\nWho should attend this event? \nThis training is ideal for: \n\nOptical and lens designers\nImaging system engineers\nEngineering managers evaluating imaging design software\n\nNo prior CODE V experience required. A basic understanding of imaging systems or optics is recommended. \n\n\nREGISTER HERE
URL:https://semiwiki.com/event/webinar-code-v-discovery-training/
LOCATION:Online
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Los_Angeles:20260909T090000
DTEND;TZID=America/Los_Angeles:20260909T100000
DTSTAMP:20260817T225137Z
CREATED:20260817T225137Z
LAST-MODIFIED:20260817T225137Z
UID:372320-1788944400-1788948000@semiwiki.com
SUMMARY:Webinar: Cutting Full-Chip SoC Debug from Days to Minutes with AI
DESCRIPTION:COMPANY EMAIL REQUIRED FOR REGISTRATION \nFull-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms\, logs\, and across hundreds of thousands of lines of code. \nIn this webinar\, we will demonstrate how the Bronco AI Debug Agent performs root-cause analysis (RCA) on real production issues in under 15 minutes\, with a 70% success rate on customer regressions. You will see the agent operate end-to-end on a representative full-chip SoC\, from a failing regression to an annotated root cause\, while interoperating with customer’s standard commercial EDA flows. \nWHAT WE WILL COVER\n– Live demonstration of the Debug Agent on a full-chip SoC regression failure\n– How the agent navigates massive codebases\, logs\, and waveforms to isolate failure mechanisms\n– Deployment patterns at large public chip companies and as well as fast-moving startups\n– How bring-your-own-model and on-prem deployment keep customer IP inside your environment.\n– How Bronco gets better without ever training on customer data. \nWHO SHOULD ATTEND\n– DV engineers and managers responsible for regression triage and production debug\n– SoC verification leads evaluating AI-native tooling for their flows\n– VPs of Engineering and Silicon leaders tracking DV cycle time and engineering ROI\n– Security and infrastructure owners assessing on-prem AI deployment for chip design \nSPEAKER\nDavid Zhi LuoZhang\, Co-Founder and CEO of Bronco AI\, will walk through the live demonstration on a real design and take questions how customers deploy\, evaluate\, and scale Bronco within their silicon projects. David works tightly with customers to deploy Bronco and coordinates between the core R&D\, customer\, and industry-relations teams at Bronco. \n*This webinar is in partnership with SemiWiki and Bronco AI* \nREGISTER HERE
URL:https://semiwiki.com/event/webinar-cutting-full-chip-soc-debug-from-days-to-minutes-with-ai-2/
LOCATION:Online
ATTACH;FMTTYPE=image/jpeg:https://semiwiki.com/wp-content/uploads/2026/08/background.jpeg
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